196768914SSukadev Bhattiprolu /* 296768914SSukadev Bhattiprolu * Copyright 2016-17 IBM Corp. 396768914SSukadev Bhattiprolu * 496768914SSukadev Bhattiprolu * This program is free software; you can redistribute it and/or 596768914SSukadev Bhattiprolu * modify it under the terms of the GNU General Public License 696768914SSukadev Bhattiprolu * as published by the Free Software Foundation; either version 796768914SSukadev Bhattiprolu * 2 of the License, or (at your option) any later version. 896768914SSukadev Bhattiprolu */ 996768914SSukadev Bhattiprolu 1096768914SSukadev Bhattiprolu #ifndef _VAS_H 1196768914SSukadev Bhattiprolu #define _VAS_H 1296768914SSukadev Bhattiprolu #include <linux/atomic.h> 1396768914SSukadev Bhattiprolu #include <linux/idr.h> 1496768914SSukadev Bhattiprolu #include <asm/vas.h> 1596768914SSukadev Bhattiprolu 1696768914SSukadev Bhattiprolu /* 1796768914SSukadev Bhattiprolu * Overview of Virtual Accelerator Switchboard (VAS). 1896768914SSukadev Bhattiprolu * 1996768914SSukadev Bhattiprolu * VAS is a hardware "switchboard" that allows senders and receivers to 2096768914SSukadev Bhattiprolu * exchange messages with _minimal_ kernel involvment. The receivers are 2196768914SSukadev Bhattiprolu * typically NX coprocessor engines that perform compression or encryption 2296768914SSukadev Bhattiprolu * in hardware, but receivers can also be other software threads. 2396768914SSukadev Bhattiprolu * 2496768914SSukadev Bhattiprolu * Senders are user/kernel threads that submit compression/encryption or 2596768914SSukadev Bhattiprolu * other requests to the receivers. Senders must format their messages as 2696768914SSukadev Bhattiprolu * Coprocessor Request Blocks (CRB)s and submit them using the "copy" and 2796768914SSukadev Bhattiprolu * "paste" instructions which were introduced in Power9. 2896768914SSukadev Bhattiprolu * 2996768914SSukadev Bhattiprolu * A Power node can have (upto?) 8 Power chips. There is one instance of 3096768914SSukadev Bhattiprolu * VAS in each Power9 chip. Each instance of VAS has 64K windows or ports, 3196768914SSukadev Bhattiprolu * Senders and receivers must each connect to a separate window before they 3296768914SSukadev Bhattiprolu * can exchange messages through the switchboard. 3396768914SSukadev Bhattiprolu * 3496768914SSukadev Bhattiprolu * Each window is described by two types of window contexts: 3596768914SSukadev Bhattiprolu * 3696768914SSukadev Bhattiprolu * Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes 3796768914SSukadev Bhattiprolu * 3896768914SSukadev Bhattiprolu * OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes. 3996768914SSukadev Bhattiprolu * 4096768914SSukadev Bhattiprolu * A window context can be viewed as a set of 64-bit registers. The settings 4196768914SSukadev Bhattiprolu * in these registers configure/control/determine the behavior of the VAS 4296768914SSukadev Bhattiprolu * hardware when messages are sent/received through the window. The registers 4396768914SSukadev Bhattiprolu * in the HVWC are configured by the kernel while the registers in the UWC can 4496768914SSukadev Bhattiprolu * be configured by the kernel or by the user space application that is using 4596768914SSukadev Bhattiprolu * the window. 4696768914SSukadev Bhattiprolu * 4796768914SSukadev Bhattiprolu * The HVWCs for all windows on a specific instance of VAS are in a contiguous 4896768914SSukadev Bhattiprolu * range of hardware addresses or Base address region (BAR) referred to as the 4996768914SSukadev Bhattiprolu * HVWC BAR for the instance. Similarly the UWCs for all windows on an instance 5096768914SSukadev Bhattiprolu * are referred to as the UWC BAR for the instance. 5196768914SSukadev Bhattiprolu * 5296768914SSukadev Bhattiprolu * The two BARs for each instance are defined Power9 MMIO Ranges spreadsheet 5396768914SSukadev Bhattiprolu * and available to the kernel in the VAS node's "reg" property in the device 5496768914SSukadev Bhattiprolu * tree: 5596768914SSukadev Bhattiprolu * 5696768914SSukadev Bhattiprolu * /proc/device-tree/vasm@.../reg 5796768914SSukadev Bhattiprolu * 5896768914SSukadev Bhattiprolu * (see vas_probe() for details on the reg property). 5996768914SSukadev Bhattiprolu * 6096768914SSukadev Bhattiprolu * The kernel maps the HVWC and UWC BAR regions into the kernel address 6196768914SSukadev Bhattiprolu * space (hvwc_map and uwc_map). The kernel can then access the window 6296768914SSukadev Bhattiprolu * contexts of a specific window using: 6396768914SSukadev Bhattiprolu * 6496768914SSukadev Bhattiprolu * hvwc = hvwc_map + winid * VAS_HVWC_SIZE. 6596768914SSukadev Bhattiprolu * uwc = uwc_map + winid * VAS_UWC_SIZE. 6696768914SSukadev Bhattiprolu * 6796768914SSukadev Bhattiprolu * where winid is the window index (0..64K). 6896768914SSukadev Bhattiprolu * 6996768914SSukadev Bhattiprolu * As mentioned, a window context is used to "configure" a window. Besides 7096768914SSukadev Bhattiprolu * this configuration address, each _send_ window also has a unique hardware 7196768914SSukadev Bhattiprolu * "paste" address that is used to submit requests/CRBs (see vas_paste_crb()). 7296768914SSukadev Bhattiprolu * 7396768914SSukadev Bhattiprolu * The hardware paste address for a window is computed using the "paste 7496768914SSukadev Bhattiprolu * base address" and "paste win id shift" reg properties in the VAS device 7596768914SSukadev Bhattiprolu * tree node using: 7696768914SSukadev Bhattiprolu * 7796768914SSukadev Bhattiprolu * paste_addr = paste_base + ((winid << paste_win_id_shift)) 7896768914SSukadev Bhattiprolu * 7996768914SSukadev Bhattiprolu * (again, see vas_probe() for ->paste_base_addr and ->paste_win_id_shift). 8096768914SSukadev Bhattiprolu * 8196768914SSukadev Bhattiprolu * The kernel maps this hardware address into the sender's address space 8296768914SSukadev Bhattiprolu * after which they can use the 'paste' instruction (new in Power9) to 8396768914SSukadev Bhattiprolu * send a message (submit a request aka CRB) to the coprocessor. 8496768914SSukadev Bhattiprolu * 8596768914SSukadev Bhattiprolu * NOTE: In the initial version, senders can only in-kernel drivers/threads. 8696768914SSukadev Bhattiprolu * Support for user space threads will be added in follow-on patches. 8796768914SSukadev Bhattiprolu * 8896768914SSukadev Bhattiprolu * TODO: Do we need to map the UWC into user address space so they can return 8996768914SSukadev Bhattiprolu * credits? Its NA for NX but may be needed for other receive windows. 9096768914SSukadev Bhattiprolu * 9196768914SSukadev Bhattiprolu */ 9296768914SSukadev Bhattiprolu 9396768914SSukadev Bhattiprolu #define VAS_WINDOWS_PER_CHIP (64 << 10) 9496768914SSukadev Bhattiprolu 9596768914SSukadev Bhattiprolu /* 9696768914SSukadev Bhattiprolu * Hypervisor and OS/USer Window Context sizes 9796768914SSukadev Bhattiprolu */ 9896768914SSukadev Bhattiprolu #define VAS_HVWC_SIZE 512 9996768914SSukadev Bhattiprolu #define VAS_UWC_SIZE PAGE_SIZE 10096768914SSukadev Bhattiprolu 10196768914SSukadev Bhattiprolu /* 10296768914SSukadev Bhattiprolu * Initial per-process credits. 10396768914SSukadev Bhattiprolu * Max send window credits: 4K-1 (12-bits in VAS_TX_WCRED) 10496768914SSukadev Bhattiprolu * Max receive window credits: 64K-1 (16 bits in VAS_LRX_WCRED) 10596768914SSukadev Bhattiprolu * 10696768914SSukadev Bhattiprolu * TODO: Needs tuning for per-process credits 10796768914SSukadev Bhattiprolu */ 10896768914SSukadev Bhattiprolu #define VAS_WCREDS_MIN 16 10996768914SSukadev Bhattiprolu #define VAS_WCREDS_MAX ((64 << 10) - 1) 11096768914SSukadev Bhattiprolu #define VAS_WCREDS_DEFAULT (1 << 10) 11196768914SSukadev Bhattiprolu 11296768914SSukadev Bhattiprolu /* 11396768914SSukadev Bhattiprolu * VAS Window Context Register Offsets and bitmasks. 11496768914SSukadev Bhattiprolu * See Section 3.1.4 of VAS Work book 11596768914SSukadev Bhattiprolu */ 11696768914SSukadev Bhattiprolu #define VAS_LPID_OFFSET 0x010 11796768914SSukadev Bhattiprolu #define VAS_LPID PPC_BITMASK(0, 11) 11896768914SSukadev Bhattiprolu 11996768914SSukadev Bhattiprolu #define VAS_PID_OFFSET 0x018 12096768914SSukadev Bhattiprolu #define VAS_PID_ID PPC_BITMASK(0, 19) 12196768914SSukadev Bhattiprolu 12296768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_OFFSET 0x020 12396768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_DR PPC_BIT(0) 12496768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_TA PPC_BIT(1) 12596768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_PR PPC_BIT(2) 12696768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_US PPC_BIT(3) 12796768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_HV PPC_BIT(4) 12896768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_SF PPC_BIT(5) 12996768914SSukadev Bhattiprolu 13096768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_OFFSET 0x028 13196768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_PAGE_SIZE PPC_BITMASK(0, 2) 13296768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_ISL PPC_BIT(3) 13396768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_TC PPC_BIT(4) 13496768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_SC PPC_BIT(5) 13596768914SSukadev Bhattiprolu 13696768914SSukadev Bhattiprolu #define VAS_XLATE_CTL_OFFSET 0x030 13796768914SSukadev Bhattiprolu #define VAS_XLATE_MODE PPC_BITMASK(0, 1) 13896768914SSukadev Bhattiprolu 13996768914SSukadev Bhattiprolu #define VAS_AMR_OFFSET 0x040 14096768914SSukadev Bhattiprolu #define VAS_AMR PPC_BITMASK(0, 63) 14196768914SSukadev Bhattiprolu 14296768914SSukadev Bhattiprolu #define VAS_SEIDR_OFFSET 0x048 14396768914SSukadev Bhattiprolu #define VAS_SEIDR PPC_BITMASK(0, 63) 14496768914SSukadev Bhattiprolu 14596768914SSukadev Bhattiprolu #define VAS_FAULT_TX_WIN_OFFSET 0x050 14696768914SSukadev Bhattiprolu #define VAS_FAULT_TX_WIN PPC_BITMASK(48, 63) 14796768914SSukadev Bhattiprolu 14896768914SSukadev Bhattiprolu #define VAS_OSU_INTR_SRC_RA_OFFSET 0x060 14996768914SSukadev Bhattiprolu #define VAS_OSU_INTR_SRC_RA PPC_BITMASK(8, 63) 15096768914SSukadev Bhattiprolu 15196768914SSukadev Bhattiprolu #define VAS_HV_INTR_SRC_RA_OFFSET 0x070 15296768914SSukadev Bhattiprolu #define VAS_HV_INTR_SRC_RA PPC_BITMASK(8, 63) 15396768914SSukadev Bhattiprolu 15496768914SSukadev Bhattiprolu #define VAS_PSWID_OFFSET 0x078 15596768914SSukadev Bhattiprolu #define VAS_PSWID_EA_HANDLE PPC_BITMASK(0, 31) 15696768914SSukadev Bhattiprolu 15796768914SSukadev Bhattiprolu #define VAS_SPARE1_OFFSET 0x080 15896768914SSukadev Bhattiprolu #define VAS_SPARE2_OFFSET 0x088 15996768914SSukadev Bhattiprolu #define VAS_SPARE3_OFFSET 0x090 16096768914SSukadev Bhattiprolu #define VAS_SPARE4_OFFSET 0x130 16196768914SSukadev Bhattiprolu #define VAS_SPARE5_OFFSET 0x160 16296768914SSukadev Bhattiprolu #define VAS_SPARE6_OFFSET 0x188 16396768914SSukadev Bhattiprolu 16496768914SSukadev Bhattiprolu #define VAS_LFIFO_BAR_OFFSET 0x0A0 16596768914SSukadev Bhattiprolu #define VAS_LFIFO_BAR PPC_BITMASK(8, 53) 16696768914SSukadev Bhattiprolu #define VAS_PAGE_MIGRATION_SELECT PPC_BITMASK(54, 56) 16796768914SSukadev Bhattiprolu 16896768914SSukadev Bhattiprolu #define VAS_LDATA_STAMP_CTL_OFFSET 0x0A8 16996768914SSukadev Bhattiprolu #define VAS_LDATA_STAMP PPC_BITMASK(0, 1) 17096768914SSukadev Bhattiprolu #define VAS_XTRA_WRITE PPC_BIT(2) 17196768914SSukadev Bhattiprolu 17296768914SSukadev Bhattiprolu #define VAS_LDMA_CACHE_CTL_OFFSET 0x0B0 17396768914SSukadev Bhattiprolu #define VAS_LDMA_TYPE PPC_BITMASK(0, 1) 17496768914SSukadev Bhattiprolu #define VAS_LDMA_FIFO_DISABLE PPC_BIT(2) 17596768914SSukadev Bhattiprolu 17696768914SSukadev Bhattiprolu #define VAS_LRFIFO_PUSH_OFFSET 0x0B8 17796768914SSukadev Bhattiprolu #define VAS_LRFIFO_PUSH PPC_BITMASK(0, 15) 17896768914SSukadev Bhattiprolu 17996768914SSukadev Bhattiprolu #define VAS_CURR_MSG_COUNT_OFFSET 0x0C0 18096768914SSukadev Bhattiprolu #define VAS_CURR_MSG_COUNT PPC_BITMASK(0, 7) 18196768914SSukadev Bhattiprolu 18296768914SSukadev Bhattiprolu #define VAS_LNOTIFY_AFTER_COUNT_OFFSET 0x0C8 18396768914SSukadev Bhattiprolu #define VAS_LNOTIFY_AFTER_COUNT PPC_BITMASK(0, 7) 18496768914SSukadev Bhattiprolu 18596768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_OFFSET 0x0E0 18696768914SSukadev Bhattiprolu #define VAS_LRX_WCRED PPC_BITMASK(0, 15) 18796768914SSukadev Bhattiprolu 18896768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_ADDER_OFFSET 0x190 18996768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_ADDER PPC_BITMASK(0, 15) 19096768914SSukadev Bhattiprolu 19196768914SSukadev Bhattiprolu #define VAS_TX_WCRED_OFFSET 0x0F0 19296768914SSukadev Bhattiprolu #define VAS_TX_WCRED PPC_BITMASK(4, 15) 19396768914SSukadev Bhattiprolu 19496768914SSukadev Bhattiprolu #define VAS_TX_WCRED_ADDER_OFFSET 0x1A0 19596768914SSukadev Bhattiprolu #define VAS_TX_WCRED_ADDER PPC_BITMASK(4, 15) 19696768914SSukadev Bhattiprolu 19796768914SSukadev Bhattiprolu #define VAS_LFIFO_SIZE_OFFSET 0x100 19896768914SSukadev Bhattiprolu #define VAS_LFIFO_SIZE PPC_BITMASK(0, 3) 19996768914SSukadev Bhattiprolu 20096768914SSukadev Bhattiprolu #define VAS_WINCTL_OFFSET 0x108 20196768914SSukadev Bhattiprolu #define VAS_WINCTL_OPEN PPC_BIT(0) 20296768914SSukadev Bhattiprolu #define VAS_WINCTL_REJ_NO_CREDIT PPC_BIT(1) 20396768914SSukadev Bhattiprolu #define VAS_WINCTL_PIN PPC_BIT(2) 20496768914SSukadev Bhattiprolu #define VAS_WINCTL_TX_WCRED_MODE PPC_BIT(3) 20596768914SSukadev Bhattiprolu #define VAS_WINCTL_RX_WCRED_MODE PPC_BIT(4) 20696768914SSukadev Bhattiprolu #define VAS_WINCTL_TX_WORD_MODE PPC_BIT(5) 20796768914SSukadev Bhattiprolu #define VAS_WINCTL_RX_WORD_MODE PPC_BIT(6) 20896768914SSukadev Bhattiprolu #define VAS_WINCTL_RSVD_TXBUF PPC_BIT(7) 20996768914SSukadev Bhattiprolu #define VAS_WINCTL_THRESH_CTL PPC_BITMASK(8, 9) 21096768914SSukadev Bhattiprolu #define VAS_WINCTL_FAULT_WIN PPC_BIT(10) 21196768914SSukadev Bhattiprolu #define VAS_WINCTL_NX_WIN PPC_BIT(11) 21296768914SSukadev Bhattiprolu 21396768914SSukadev Bhattiprolu #define VAS_WIN_STATUS_OFFSET 0x110 21496768914SSukadev Bhattiprolu #define VAS_WIN_BUSY PPC_BIT(1) 21596768914SSukadev Bhattiprolu 21696768914SSukadev Bhattiprolu #define VAS_WIN_CTX_CACHING_CTL_OFFSET 0x118 21796768914SSukadev Bhattiprolu #define VAS_CASTOUT_REQ PPC_BIT(0) 21896768914SSukadev Bhattiprolu #define VAS_PUSH_TO_MEM PPC_BIT(1) 21996768914SSukadev Bhattiprolu #define VAS_WIN_CACHE_STATUS PPC_BIT(4) 22096768914SSukadev Bhattiprolu 22196768914SSukadev Bhattiprolu #define VAS_TX_RSVD_BUF_COUNT_OFFSET 0x120 22296768914SSukadev Bhattiprolu #define VAS_RXVD_BUF_COUNT PPC_BITMASK(58, 63) 22396768914SSukadev Bhattiprolu 22496768914SSukadev Bhattiprolu #define VAS_LRFIFO_WIN_PTR_OFFSET 0x128 22596768914SSukadev Bhattiprolu #define VAS_LRX_WIN_ID PPC_BITMASK(0, 15) 22696768914SSukadev Bhattiprolu 22796768914SSukadev Bhattiprolu /* 22896768914SSukadev Bhattiprolu * Local Notification Control Register controls what happens in _response_ 22996768914SSukadev Bhattiprolu * to a paste command and hence applies only to receive windows. 23096768914SSukadev Bhattiprolu */ 23196768914SSukadev Bhattiprolu #define VAS_LNOTIFY_CTL_OFFSET 0x138 23296768914SSukadev Bhattiprolu #define VAS_NOTIFY_DISABLE PPC_BIT(0) 23396768914SSukadev Bhattiprolu #define VAS_INTR_DISABLE PPC_BIT(1) 23496768914SSukadev Bhattiprolu #define VAS_NOTIFY_EARLY PPC_BIT(2) 23596768914SSukadev Bhattiprolu #define VAS_NOTIFY_OSU_INTR PPC_BIT(3) 23696768914SSukadev Bhattiprolu 23796768914SSukadev Bhattiprolu #define VAS_LNOTIFY_PID_OFFSET 0x140 23896768914SSukadev Bhattiprolu #define VAS_LNOTIFY_PID PPC_BITMASK(0, 19) 23996768914SSukadev Bhattiprolu 24096768914SSukadev Bhattiprolu #define VAS_LNOTIFY_LPID_OFFSET 0x148 24196768914SSukadev Bhattiprolu #define VAS_LNOTIFY_LPID PPC_BITMASK(0, 11) 24296768914SSukadev Bhattiprolu 24396768914SSukadev Bhattiprolu #define VAS_LNOTIFY_TID_OFFSET 0x150 24496768914SSukadev Bhattiprolu #define VAS_LNOTIFY_TID PPC_BITMASK(0, 15) 24596768914SSukadev Bhattiprolu 24696768914SSukadev Bhattiprolu #define VAS_LNOTIFY_SCOPE_OFFSET 0x158 24796768914SSukadev Bhattiprolu #define VAS_LNOTIFY_MIN_SCOPE PPC_BITMASK(0, 1) 24896768914SSukadev Bhattiprolu #define VAS_LNOTIFY_MAX_SCOPE PPC_BITMASK(2, 3) 24996768914SSukadev Bhattiprolu 25096768914SSukadev Bhattiprolu #define VAS_NX_UTIL_OFFSET 0x1B0 25196768914SSukadev Bhattiprolu #define VAS_NX_UTIL PPC_BITMASK(0, 63) 25296768914SSukadev Bhattiprolu 25396768914SSukadev Bhattiprolu /* SE: Side effects */ 25496768914SSukadev Bhattiprolu #define VAS_NX_UTIL_SE_OFFSET 0x1B8 25596768914SSukadev Bhattiprolu #define VAS_NX_UTIL_SE PPC_BITMASK(0, 63) 25696768914SSukadev Bhattiprolu 25796768914SSukadev Bhattiprolu #define VAS_NX_UTIL_ADDER_OFFSET 0x180 25896768914SSukadev Bhattiprolu #define VAS_NX_UTIL_ADDER PPC_BITMASK(32, 63) 25996768914SSukadev Bhattiprolu 26096768914SSukadev Bhattiprolu /* 26196768914SSukadev Bhattiprolu * Local Notify Scope Control Register. (Receive windows only). 26296768914SSukadev Bhattiprolu */ 26396768914SSukadev Bhattiprolu enum vas_notify_scope { 26496768914SSukadev Bhattiprolu VAS_SCOPE_LOCAL, 26596768914SSukadev Bhattiprolu VAS_SCOPE_GROUP, 26696768914SSukadev Bhattiprolu VAS_SCOPE_VECTORED_GROUP, 26796768914SSukadev Bhattiprolu VAS_SCOPE_UNUSED, 26896768914SSukadev Bhattiprolu }; 26996768914SSukadev Bhattiprolu 27096768914SSukadev Bhattiprolu /* 27196768914SSukadev Bhattiprolu * Local DMA Cache Control Register (Receive windows only). 27296768914SSukadev Bhattiprolu */ 27396768914SSukadev Bhattiprolu enum vas_dma_type { 27496768914SSukadev Bhattiprolu VAS_DMA_TYPE_INJECT, 27596768914SSukadev Bhattiprolu VAS_DMA_TYPE_WRITE, 27696768914SSukadev Bhattiprolu }; 27796768914SSukadev Bhattiprolu 27896768914SSukadev Bhattiprolu /* 27996768914SSukadev Bhattiprolu * Local Notify Scope Control Register. (Receive windows only). 28096768914SSukadev Bhattiprolu * Not applicable to NX receive windows. 28196768914SSukadev Bhattiprolu */ 28296768914SSukadev Bhattiprolu enum vas_notify_after_count { 28396768914SSukadev Bhattiprolu VAS_NOTIFY_AFTER_256 = 0, 28496768914SSukadev Bhattiprolu VAS_NOTIFY_NONE, 28596768914SSukadev Bhattiprolu VAS_NOTIFY_AFTER_2 28696768914SSukadev Bhattiprolu }; 28796768914SSukadev Bhattiprolu 28896768914SSukadev Bhattiprolu /* 28996768914SSukadev Bhattiprolu * One per instance of VAS. Each instance will have a separate set of 29096768914SSukadev Bhattiprolu * receive windows, one per coprocessor type. 29196768914SSukadev Bhattiprolu */ 29296768914SSukadev Bhattiprolu struct vas_instance { 29396768914SSukadev Bhattiprolu int vas_id; 29496768914SSukadev Bhattiprolu struct ida ida; 29596768914SSukadev Bhattiprolu struct list_head node; 29696768914SSukadev Bhattiprolu struct platform_device *pdev; 29796768914SSukadev Bhattiprolu 29896768914SSukadev Bhattiprolu u64 hvwc_bar_start; 29996768914SSukadev Bhattiprolu u64 uwc_bar_start; 30096768914SSukadev Bhattiprolu u64 paste_base_addr; 30196768914SSukadev Bhattiprolu u64 paste_win_id_shift; 30296768914SSukadev Bhattiprolu 30396768914SSukadev Bhattiprolu struct mutex mutex; 30496768914SSukadev Bhattiprolu struct vas_window *rxwin[VAS_COP_TYPE_MAX]; 30596768914SSukadev Bhattiprolu struct vas_window *windows[VAS_WINDOWS_PER_CHIP]; 30696768914SSukadev Bhattiprolu }; 30796768914SSukadev Bhattiprolu 30896768914SSukadev Bhattiprolu /* 30996768914SSukadev Bhattiprolu * In-kernel state a VAS window. One per window. 31096768914SSukadev Bhattiprolu */ 31196768914SSukadev Bhattiprolu struct vas_window { 31296768914SSukadev Bhattiprolu /* Fields common to send and receive windows */ 31396768914SSukadev Bhattiprolu struct vas_instance *vinst; 31496768914SSukadev Bhattiprolu int winid; 31596768914SSukadev Bhattiprolu bool tx_win; /* True if send window */ 31696768914SSukadev Bhattiprolu bool nx_win; /* True if NX window */ 31796768914SSukadev Bhattiprolu bool user_win; /* True if user space window */ 31896768914SSukadev Bhattiprolu void *hvwc_map; /* HV window context */ 31996768914SSukadev Bhattiprolu void *uwc_map; /* OS/User window context */ 32096768914SSukadev Bhattiprolu pid_t pid; /* Linux process id of owner */ 32196768914SSukadev Bhattiprolu 32296768914SSukadev Bhattiprolu /* Fields applicable only to send windows */ 32396768914SSukadev Bhattiprolu void *paste_kaddr; 32496768914SSukadev Bhattiprolu char *paste_addr_name; 32596768914SSukadev Bhattiprolu struct vas_window *rxwin; 32696768914SSukadev Bhattiprolu 32796768914SSukadev Bhattiprolu /* Feilds applicable only to receive windows */ 32896768914SSukadev Bhattiprolu enum vas_cop_type cop; 32996768914SSukadev Bhattiprolu atomic_t num_txwins; 33096768914SSukadev Bhattiprolu }; 33196768914SSukadev Bhattiprolu 33296768914SSukadev Bhattiprolu /* 33396768914SSukadev Bhattiprolu * Container for the hardware state of a window. One per-window. 33496768914SSukadev Bhattiprolu * 33596768914SSukadev Bhattiprolu * A VAS Window context is a 512-byte area in the hardware that contains 33696768914SSukadev Bhattiprolu * a set of 64-bit registers. Individual bit-fields in these registers 33796768914SSukadev Bhattiprolu * determine the configuration/operation of the hardware. struct vas_winctx 33896768914SSukadev Bhattiprolu * is a container for the register fields in the window context. 33996768914SSukadev Bhattiprolu */ 34096768914SSukadev Bhattiprolu struct vas_winctx { 34196768914SSukadev Bhattiprolu void *rx_fifo; 34296768914SSukadev Bhattiprolu int rx_fifo_size; 34396768914SSukadev Bhattiprolu int wcreds_max; 34496768914SSukadev Bhattiprolu int rsvd_txbuf_count; 34596768914SSukadev Bhattiprolu 34696768914SSukadev Bhattiprolu bool user_win; 34796768914SSukadev Bhattiprolu bool nx_win; 34896768914SSukadev Bhattiprolu bool fault_win; 34996768914SSukadev Bhattiprolu bool rsvd_txbuf_enable; 35096768914SSukadev Bhattiprolu bool pin_win; 35196768914SSukadev Bhattiprolu bool rej_no_credit; 35296768914SSukadev Bhattiprolu bool tx_wcred_mode; 35396768914SSukadev Bhattiprolu bool rx_wcred_mode; 35496768914SSukadev Bhattiprolu bool tx_word_mode; 35596768914SSukadev Bhattiprolu bool rx_word_mode; 35696768914SSukadev Bhattiprolu bool data_stamp; 35796768914SSukadev Bhattiprolu bool xtra_write; 35896768914SSukadev Bhattiprolu bool notify_disable; 35996768914SSukadev Bhattiprolu bool intr_disable; 36096768914SSukadev Bhattiprolu bool fifo_disable; 36196768914SSukadev Bhattiprolu bool notify_early; 36296768914SSukadev Bhattiprolu bool notify_os_intr_reg; 36396768914SSukadev Bhattiprolu 36496768914SSukadev Bhattiprolu int lpid; 36596768914SSukadev Bhattiprolu int pidr; /* value from SPRN_PID, not linux pid */ 36696768914SSukadev Bhattiprolu int lnotify_lpid; 36796768914SSukadev Bhattiprolu int lnotify_pid; 36896768914SSukadev Bhattiprolu int lnotify_tid; 36996768914SSukadev Bhattiprolu u32 pswid; 37096768914SSukadev Bhattiprolu int rx_win_id; 37196768914SSukadev Bhattiprolu int fault_win_id; 37296768914SSukadev Bhattiprolu int tc_mode; 37396768914SSukadev Bhattiprolu 37496768914SSukadev Bhattiprolu u64 irq_port; 37596768914SSukadev Bhattiprolu 37696768914SSukadev Bhattiprolu enum vas_dma_type dma_type; 37796768914SSukadev Bhattiprolu enum vas_notify_scope min_scope; 37896768914SSukadev Bhattiprolu enum vas_notify_scope max_scope; 37996768914SSukadev Bhattiprolu enum vas_notify_after_count notify_after_count; 38096768914SSukadev Bhattiprolu }; 38196768914SSukadev Bhattiprolu 3824dea2d1aSSukadev Bhattiprolu extern struct vas_instance *find_vas_instance(int vasid); 3834dea2d1aSSukadev Bhattiprolu 38496768914SSukadev Bhattiprolu #endif /* _VAS_H */ 385