1e2186023SMichael Ellerman /* 2e2186023SMichael Ellerman * Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation. 3e2186023SMichael Ellerman * 4e2186023SMichael Ellerman * This program is free software; you can redistribute it and/or 5e2186023SMichael Ellerman * modify it under the terms of the GNU General Public License 6e2186023SMichael Ellerman * as published by the Free Software Foundation; either version 7e2186023SMichael Ellerman * 2 of the License, or (at your option) any later version. 8e2186023SMichael Ellerman */ 9e2186023SMichael Ellerman 10e2186023SMichael Ellerman #define pr_fmt(fmt) "powernv: " fmt 11e2186023SMichael Ellerman 12e2186023SMichael Ellerman #include <linux/kernel.h> 13e2186023SMichael Ellerman #include <linux/cpu.h> 14e2186023SMichael Ellerman #include <linux/cpumask.h> 15e2186023SMichael Ellerman #include <linux/device.h> 16e2186023SMichael Ellerman #include <linux/gfp.h> 17e2186023SMichael Ellerman #include <linux/smp.h> 18e2186023SMichael Ellerman #include <linux/stop_machine.h> 19e2186023SMichael Ellerman 20e2186023SMichael Ellerman #include <asm/cputhreads.h> 21e2186023SMichael Ellerman #include <asm/kvm_ppc.h> 22e2186023SMichael Ellerman #include <asm/machdep.h> 23e2186023SMichael Ellerman #include <asm/opal.h> 24e2186023SMichael Ellerman #include <asm/smp.h> 25e2186023SMichael Ellerman 26e2186023SMichael Ellerman #include "subcore.h" 271217d34bSAnton Blanchard #include "powernv.h" 28e2186023SMichael Ellerman 29e2186023SMichael Ellerman 30e2186023SMichael Ellerman /* 31e2186023SMichael Ellerman * Split/unsplit procedure: 32e2186023SMichael Ellerman * 33e2186023SMichael Ellerman * A core can be in one of three states, unsplit, 2-way split, and 4-way split. 34e2186023SMichael Ellerman * 35e2186023SMichael Ellerman * The mapping to subcores_per_core is simple: 36e2186023SMichael Ellerman * 37e2186023SMichael Ellerman * State | subcores_per_core 38e2186023SMichael Ellerman * ------------|------------------ 39e2186023SMichael Ellerman * Unsplit | 1 40e2186023SMichael Ellerman * 2-way split | 2 41e2186023SMichael Ellerman * 4-way split | 4 42e2186023SMichael Ellerman * 43e2186023SMichael Ellerman * The core is split along thread boundaries, the mapping between subcores and 44e2186023SMichael Ellerman * threads is as follows: 45e2186023SMichael Ellerman * 46e2186023SMichael Ellerman * Unsplit: 47e2186023SMichael Ellerman * ---------------------------- 48e2186023SMichael Ellerman * Subcore | 0 | 49e2186023SMichael Ellerman * ---------------------------- 50e2186023SMichael Ellerman * Thread | 0 1 2 3 4 5 6 7 | 51e2186023SMichael Ellerman * ---------------------------- 52e2186023SMichael Ellerman * 53e2186023SMichael Ellerman * 2-way split: 54e2186023SMichael Ellerman * ------------------------------------- 55e2186023SMichael Ellerman * Subcore | 0 | 1 | 56e2186023SMichael Ellerman * ------------------------------------- 57e2186023SMichael Ellerman * Thread | 0 1 2 3 | 4 5 6 7 | 58e2186023SMichael Ellerman * ------------------------------------- 59e2186023SMichael Ellerman * 60e2186023SMichael Ellerman * 4-way split: 61e2186023SMichael Ellerman * ----------------------------------------- 62e2186023SMichael Ellerman * Subcore | 0 | 1 | 2 | 3 | 63e2186023SMichael Ellerman * ----------------------------------------- 64e2186023SMichael Ellerman * Thread | 0 1 | 2 3 | 4 5 | 6 7 | 65e2186023SMichael Ellerman * ----------------------------------------- 66e2186023SMichael Ellerman * 67e2186023SMichael Ellerman * 68e2186023SMichael Ellerman * Transitions 69e2186023SMichael Ellerman * ----------- 70e2186023SMichael Ellerman * 71e2186023SMichael Ellerman * It is not possible to transition between either of the split states, the 72e2186023SMichael Ellerman * core must first be unsplit. The legal transitions are: 73e2186023SMichael Ellerman * 74e2186023SMichael Ellerman * ----------- --------------- 75e2186023SMichael Ellerman * | | <----> | 2-way split | 76e2186023SMichael Ellerman * | | --------------- 77e2186023SMichael Ellerman * | Unsplit | 78e2186023SMichael Ellerman * | | --------------- 79e2186023SMichael Ellerman * | | <----> | 4-way split | 80e2186023SMichael Ellerman * ----------- --------------- 81e2186023SMichael Ellerman * 82e2186023SMichael Ellerman * Unsplitting 83e2186023SMichael Ellerman * ----------- 84e2186023SMichael Ellerman * 85e2186023SMichael Ellerman * Unsplitting is the simpler procedure. It requires thread 0 to request the 86e2186023SMichael Ellerman * unsplit while all other threads NAP. 87e2186023SMichael Ellerman * 88e2186023SMichael Ellerman * Thread 0 clears HID0_POWER8_DYNLPARDIS (Dynamic LPAR Disable). This tells 89e2186023SMichael Ellerman * the hardware that if all threads except 0 are napping, the hardware should 90e2186023SMichael Ellerman * unsplit the core. 91e2186023SMichael Ellerman * 92e2186023SMichael Ellerman * Non-zero threads are sent to a NAP loop, they don't exit the loop until they 93e2186023SMichael Ellerman * see the core unsplit. 94e2186023SMichael Ellerman * 95e2186023SMichael Ellerman * Core 0 spins waiting for the hardware to see all the other threads napping 96e2186023SMichael Ellerman * and perform the unsplit. 97e2186023SMichael Ellerman * 98e2186023SMichael Ellerman * Once thread 0 sees the unsplit, it IPIs the secondary threads to wake them 99e2186023SMichael Ellerman * out of NAP. They will then see the core unsplit and exit the NAP loop. 100e2186023SMichael Ellerman * 101e2186023SMichael Ellerman * Splitting 102e2186023SMichael Ellerman * --------- 103e2186023SMichael Ellerman * 104e2186023SMichael Ellerman * The basic splitting procedure is fairly straight forward. However it is 105e2186023SMichael Ellerman * complicated by the fact that after the split occurs, the newly created 106e2186023SMichael Ellerman * subcores are not in a fully initialised state. 107e2186023SMichael Ellerman * 108e2186023SMichael Ellerman * Most notably the subcores do not have the correct value for SDR1, which 109e2186023SMichael Ellerman * means they must not be running in virtual mode when the split occurs. The 110e2186023SMichael Ellerman * subcores have separate timebases SPRs but these are pre-synchronised by 111e2186023SMichael Ellerman * opal. 112e2186023SMichael Ellerman * 113e2186023SMichael Ellerman * To begin with secondary threads are sent to an assembly routine. There they 114e2186023SMichael Ellerman * switch to real mode, so they are immune to the uninitialised SDR1 value. 115e2186023SMichael Ellerman * Once in real mode they indicate that they are in real mode, and spin waiting 116e2186023SMichael Ellerman * to see the core split. 117e2186023SMichael Ellerman * 118e2186023SMichael Ellerman * Thread 0 waits to see that all secondaries are in real mode, and then begins 119e2186023SMichael Ellerman * the splitting procedure. It firstly sets HID0_POWER8_DYNLPARDIS, which 120e2186023SMichael Ellerman * prevents the hardware from unsplitting. Then it sets the appropriate HID bit 121e2186023SMichael Ellerman * to request the split, and spins waiting to see that the split has happened. 122e2186023SMichael Ellerman * 123e2186023SMichael Ellerman * Concurrently the secondaries will notice the split. When they do they set up 124e2186023SMichael Ellerman * their SPRs, notably SDR1, and then they can return to virtual mode and exit 125e2186023SMichael Ellerman * the procedure. 126e2186023SMichael Ellerman */ 127e2186023SMichael Ellerman 128e2186023SMichael Ellerman /* Initialised at boot by subcore_init() */ 129e2186023SMichael Ellerman static int subcores_per_core; 130e2186023SMichael Ellerman 131e2186023SMichael Ellerman /* 132e2186023SMichael Ellerman * Used to communicate to offline cpus that we want them to pop out of the 133e2186023SMichael Ellerman * offline loop and do a split or unsplit. 134e2186023SMichael Ellerman * 135e2186023SMichael Ellerman * 0 - no split happening 136e2186023SMichael Ellerman * 1 - unsplit in progress 137e2186023SMichael Ellerman * 2 - split to 2 in progress 138e2186023SMichael Ellerman * 4 - split to 4 in progress 139e2186023SMichael Ellerman */ 140e2186023SMichael Ellerman static int new_split_mode; 141e2186023SMichael Ellerman 142e2186023SMichael Ellerman static cpumask_var_t cpu_offline_mask; 143e2186023SMichael Ellerman 144e2186023SMichael Ellerman struct split_state { 145e2186023SMichael Ellerman u8 step; 146e2186023SMichael Ellerman u8 master; 147e2186023SMichael Ellerman }; 148e2186023SMichael Ellerman 149e2186023SMichael Ellerman static DEFINE_PER_CPU(struct split_state, split_state); 150e2186023SMichael Ellerman 151e2186023SMichael Ellerman static void wait_for_sync_step(int step) 152e2186023SMichael Ellerman { 153e2186023SMichael Ellerman int i, cpu = smp_processor_id(); 154e2186023SMichael Ellerman 155e2186023SMichael Ellerman for (i = cpu + 1; i < cpu + threads_per_core; i++) 156e2186023SMichael Ellerman while(per_cpu(split_state, i).step < step) 157e2186023SMichael Ellerman barrier(); 158e2186023SMichael Ellerman 159e2186023SMichael Ellerman /* Order the wait loop vs any subsequent loads/stores. */ 160e2186023SMichael Ellerman mb(); 161e2186023SMichael Ellerman } 162e2186023SMichael Ellerman 16377b54e9fSShreyas B. Prabhu static void update_hid_in_slw(u64 hid0) 16477b54e9fSShreyas B. Prabhu { 16577b54e9fSShreyas B. Prabhu u64 idle_states = pnv_get_supported_cpuidle_states(); 16677b54e9fSShreyas B. Prabhu 16777b54e9fSShreyas B. Prabhu if (idle_states & OPAL_PM_WINKLE_ENABLED) { 16877b54e9fSShreyas B. Prabhu /* OPAL call to patch slw with the new HID0 value */ 16977b54e9fSShreyas B. Prabhu u64 cpu_pir = hard_smp_processor_id(); 17077b54e9fSShreyas B. Prabhu 17177b54e9fSShreyas B. Prabhu opal_slw_set_reg(cpu_pir, SPRN_HID0, hid0); 17277b54e9fSShreyas B. Prabhu } 17377b54e9fSShreyas B. Prabhu } 17477b54e9fSShreyas B. Prabhu 175e2186023SMichael Ellerman static void unsplit_core(void) 176e2186023SMichael Ellerman { 177e2186023SMichael Ellerman u64 hid0, mask; 178e2186023SMichael Ellerman int i, cpu; 179e2186023SMichael Ellerman 180e2186023SMichael Ellerman mask = HID0_POWER8_2LPARMODE | HID0_POWER8_4LPARMODE; 181e2186023SMichael Ellerman 182e2186023SMichael Ellerman cpu = smp_processor_id(); 183e2186023SMichael Ellerman if (cpu_thread_in_core(cpu) != 0) { 184e2186023SMichael Ellerman while (mfspr(SPRN_HID0) & mask) 185e2186023SMichael Ellerman power7_nap(0); 186e2186023SMichael Ellerman 187e2186023SMichael Ellerman per_cpu(split_state, cpu).step = SYNC_STEP_UNSPLIT; 188e2186023SMichael Ellerman return; 189e2186023SMichael Ellerman } 190e2186023SMichael Ellerman 191e2186023SMichael Ellerman hid0 = mfspr(SPRN_HID0); 192e2186023SMichael Ellerman hid0 &= ~HID0_POWER8_DYNLPARDIS; 193e63dbd16SGautham R. Shenoy update_power8_hid0(hid0); 19477b54e9fSShreyas B. Prabhu update_hid_in_slw(hid0); 195e2186023SMichael Ellerman 196e2186023SMichael Ellerman while (mfspr(SPRN_HID0) & mask) 197e2186023SMichael Ellerman cpu_relax(); 198e2186023SMichael Ellerman 199e2186023SMichael Ellerman /* Wake secondaries out of NAP */ 200e2186023SMichael Ellerman for (i = cpu + 1; i < cpu + threads_per_core; i++) 201e2186023SMichael Ellerman smp_send_reschedule(i); 202e2186023SMichael Ellerman 203e2186023SMichael Ellerman wait_for_sync_step(SYNC_STEP_UNSPLIT); 204e2186023SMichael Ellerman } 205e2186023SMichael Ellerman 206e2186023SMichael Ellerman static void split_core(int new_mode) 207e2186023SMichael Ellerman { 208e2186023SMichael Ellerman struct { u64 value; u64 mask; } split_parms[2] = { 209e2186023SMichael Ellerman { HID0_POWER8_1TO2LPAR, HID0_POWER8_2LPARMODE }, 210e2186023SMichael Ellerman { HID0_POWER8_1TO4LPAR, HID0_POWER8_4LPARMODE } 211e2186023SMichael Ellerman }; 212e2186023SMichael Ellerman int i, cpu; 213e2186023SMichael Ellerman u64 hid0; 214e2186023SMichael Ellerman 215e2186023SMichael Ellerman /* Convert new_mode (2 or 4) into an index into our parms array */ 216e2186023SMichael Ellerman i = (new_mode >> 1) - 1; 217e2186023SMichael Ellerman BUG_ON(i < 0 || i > 1); 218e2186023SMichael Ellerman 219e2186023SMichael Ellerman cpu = smp_processor_id(); 220e2186023SMichael Ellerman if (cpu_thread_in_core(cpu) != 0) { 221e2186023SMichael Ellerman split_core_secondary_loop(&per_cpu(split_state, cpu).step); 222e2186023SMichael Ellerman return; 223e2186023SMichael Ellerman } 224e2186023SMichael Ellerman 225e2186023SMichael Ellerman wait_for_sync_step(SYNC_STEP_REAL_MODE); 226e2186023SMichael Ellerman 227e2186023SMichael Ellerman /* Write new mode */ 228e2186023SMichael Ellerman hid0 = mfspr(SPRN_HID0); 229e2186023SMichael Ellerman hid0 |= HID0_POWER8_DYNLPARDIS | split_parms[i].value; 230e63dbd16SGautham R. Shenoy update_power8_hid0(hid0); 23177b54e9fSShreyas B. Prabhu update_hid_in_slw(hid0); 232e2186023SMichael Ellerman 233e2186023SMichael Ellerman /* Wait for it to happen */ 234e2186023SMichael Ellerman while (!(mfspr(SPRN_HID0) & split_parms[i].mask)) 235e2186023SMichael Ellerman cpu_relax(); 236e2186023SMichael Ellerman } 237e2186023SMichael Ellerman 238e2186023SMichael Ellerman static void cpu_do_split(int new_mode) 239e2186023SMichael Ellerman { 240e2186023SMichael Ellerman /* 241e2186023SMichael Ellerman * At boot subcores_per_core will be 0, so we will always unsplit at 242e2186023SMichael Ellerman * boot. In the usual case where the core is already unsplit it's a 243e2186023SMichael Ellerman * nop, and this just ensures the kernel's notion of the mode is 244e2186023SMichael Ellerman * consistent with the hardware. 245e2186023SMichael Ellerman */ 246e2186023SMichael Ellerman if (subcores_per_core != 1) 247e2186023SMichael Ellerman unsplit_core(); 248e2186023SMichael Ellerman 249e2186023SMichael Ellerman if (new_mode != 1) 250e2186023SMichael Ellerman split_core(new_mode); 251e2186023SMichael Ellerman 252e2186023SMichael Ellerman mb(); 253e2186023SMichael Ellerman per_cpu(split_state, smp_processor_id()).step = SYNC_STEP_FINISHED; 254e2186023SMichael Ellerman } 255e2186023SMichael Ellerman 256e2186023SMichael Ellerman bool cpu_core_split_required(void) 257e2186023SMichael Ellerman { 258e2186023SMichael Ellerman smp_rmb(); 259e2186023SMichael Ellerman 260e2186023SMichael Ellerman if (!new_split_mode) 261e2186023SMichael Ellerman return false; 262e2186023SMichael Ellerman 263e2186023SMichael Ellerman cpu_do_split(new_split_mode); 264e2186023SMichael Ellerman 265e2186023SMichael Ellerman return true; 266e2186023SMichael Ellerman } 267e2186023SMichael Ellerman 26877b54e9fSShreyas B. Prabhu void update_subcore_sibling_mask(void) 26977b54e9fSShreyas B. Prabhu { 27077b54e9fSShreyas B. Prabhu int cpu; 27177b54e9fSShreyas B. Prabhu /* 27277b54e9fSShreyas B. Prabhu * sibling mask for the first cpu. Left shift this by required bits 27377b54e9fSShreyas B. Prabhu * to get sibling mask for the rest of the cpus. 27477b54e9fSShreyas B. Prabhu */ 27577b54e9fSShreyas B. Prabhu int sibling_mask_first_cpu = (1 << threads_per_subcore) - 1; 27677b54e9fSShreyas B. Prabhu 27777b54e9fSShreyas B. Prabhu for_each_possible_cpu(cpu) { 27877b54e9fSShreyas B. Prabhu int tid = cpu_thread_in_core(cpu); 27977b54e9fSShreyas B. Prabhu int offset = (tid / threads_per_subcore) * threads_per_subcore; 28077b54e9fSShreyas B. Prabhu int mask = sibling_mask_first_cpu << offset; 28177b54e9fSShreyas B. Prabhu 28277b54e9fSShreyas B. Prabhu paca[cpu].subcore_sibling_mask = mask; 28377b54e9fSShreyas B. Prabhu 28477b54e9fSShreyas B. Prabhu } 28577b54e9fSShreyas B. Prabhu } 28677b54e9fSShreyas B. Prabhu 287e2186023SMichael Ellerman static int cpu_update_split_mode(void *data) 288e2186023SMichael Ellerman { 289e2186023SMichael Ellerman int cpu, new_mode = *(int *)data; 290e2186023SMichael Ellerman 291e2186023SMichael Ellerman if (this_cpu_ptr(&split_state)->master) { 292e2186023SMichael Ellerman new_split_mode = new_mode; 293e2186023SMichael Ellerman smp_wmb(); 294e2186023SMichael Ellerman 295e2186023SMichael Ellerman cpumask_andnot(cpu_offline_mask, cpu_present_mask, 296e2186023SMichael Ellerman cpu_online_mask); 297e2186023SMichael Ellerman 298e2186023SMichael Ellerman /* This should work even though the cpu is offline */ 299e2186023SMichael Ellerman for_each_cpu(cpu, cpu_offline_mask) 300e2186023SMichael Ellerman smp_send_reschedule(cpu); 301e2186023SMichael Ellerman } 302e2186023SMichael Ellerman 303e2186023SMichael Ellerman cpu_do_split(new_mode); 304e2186023SMichael Ellerman 305e2186023SMichael Ellerman if (this_cpu_ptr(&split_state)->master) { 306e2186023SMichael Ellerman /* Wait for all cpus to finish before we touch subcores_per_core */ 307e2186023SMichael Ellerman for_each_present_cpu(cpu) { 308e2186023SMichael Ellerman if (cpu >= setup_max_cpus) 309e2186023SMichael Ellerman break; 310e2186023SMichael Ellerman 311e2186023SMichael Ellerman while(per_cpu(split_state, cpu).step < SYNC_STEP_FINISHED) 312e2186023SMichael Ellerman barrier(); 313e2186023SMichael Ellerman } 314e2186023SMichael Ellerman 315e2186023SMichael Ellerman new_split_mode = 0; 316e2186023SMichael Ellerman 317e2186023SMichael Ellerman /* Make the new mode public */ 318e2186023SMichael Ellerman subcores_per_core = new_mode; 319e2186023SMichael Ellerman threads_per_subcore = threads_per_core / subcores_per_core; 32077b54e9fSShreyas B. Prabhu update_subcore_sibling_mask(); 321e2186023SMichael Ellerman 322e2186023SMichael Ellerman /* Make sure the new mode is written before we exit */ 323e2186023SMichael Ellerman mb(); 324e2186023SMichael Ellerman } 325e2186023SMichael Ellerman 326e2186023SMichael Ellerman return 0; 327e2186023SMichael Ellerman } 328e2186023SMichael Ellerman 329e2186023SMichael Ellerman static int set_subcores_per_core(int new_mode) 330e2186023SMichael Ellerman { 331e2186023SMichael Ellerman struct split_state *state; 332e2186023SMichael Ellerman int cpu; 333e2186023SMichael Ellerman 334e2186023SMichael Ellerman if (kvm_hv_mode_active()) { 335e2186023SMichael Ellerman pr_err("Unable to change split core mode while KVM active.\n"); 336e2186023SMichael Ellerman return -EBUSY; 337e2186023SMichael Ellerman } 338e2186023SMichael Ellerman 339e2186023SMichael Ellerman /* 340e2186023SMichael Ellerman * We are only called at boot, or from the sysfs write. If that ever 341e2186023SMichael Ellerman * changes we'll need a lock here. 342e2186023SMichael Ellerman */ 343e2186023SMichael Ellerman BUG_ON(new_mode < 1 || new_mode > 4 || new_mode == 3); 344e2186023SMichael Ellerman 345e2186023SMichael Ellerman for_each_present_cpu(cpu) { 346e2186023SMichael Ellerman state = &per_cpu(split_state, cpu); 347e2186023SMichael Ellerman state->step = SYNC_STEP_INITIAL; 348e2186023SMichael Ellerman state->master = 0; 349e2186023SMichael Ellerman } 350e2186023SMichael Ellerman 351f9a69931SSebastian Andrzej Siewior cpus_read_lock(); 352e2186023SMichael Ellerman 353e2186023SMichael Ellerman /* This cpu will update the globals before exiting stop machine */ 354e2186023SMichael Ellerman this_cpu_ptr(&split_state)->master = 1; 355e2186023SMichael Ellerman 356e2186023SMichael Ellerman /* Ensure state is consistent before we call the other cpus */ 357e2186023SMichael Ellerman mb(); 358e2186023SMichael Ellerman 359f9a69931SSebastian Andrzej Siewior stop_machine_cpuslocked(cpu_update_split_mode, &new_mode, 360f9a69931SSebastian Andrzej Siewior cpu_online_mask); 361e2186023SMichael Ellerman 362f9a69931SSebastian Andrzej Siewior cpus_read_unlock(); 363e2186023SMichael Ellerman 364e2186023SMichael Ellerman return 0; 365e2186023SMichael Ellerman } 366e2186023SMichael Ellerman 367e2186023SMichael Ellerman static ssize_t __used store_subcores_per_core(struct device *dev, 368e2186023SMichael Ellerman struct device_attribute *attr, const char *buf, 369e2186023SMichael Ellerman size_t count) 370e2186023SMichael Ellerman { 371e2186023SMichael Ellerman unsigned long val; 372e2186023SMichael Ellerman int rc; 373e2186023SMichael Ellerman 374e2186023SMichael Ellerman /* We are serialised by the attribute lock */ 375e2186023SMichael Ellerman 376e2186023SMichael Ellerman rc = sscanf(buf, "%lx", &val); 377e2186023SMichael Ellerman if (rc != 1) 378e2186023SMichael Ellerman return -EINVAL; 379e2186023SMichael Ellerman 380e2186023SMichael Ellerman switch (val) { 381e2186023SMichael Ellerman case 1: 382e2186023SMichael Ellerman case 2: 383e2186023SMichael Ellerman case 4: 384e2186023SMichael Ellerman if (subcores_per_core == val) 385e2186023SMichael Ellerman /* Nothing to do */ 386e2186023SMichael Ellerman goto out; 387e2186023SMichael Ellerman break; 388e2186023SMichael Ellerman default: 389e2186023SMichael Ellerman return -EINVAL; 390e2186023SMichael Ellerman } 391e2186023SMichael Ellerman 392e2186023SMichael Ellerman rc = set_subcores_per_core(val); 393e2186023SMichael Ellerman if (rc) 394e2186023SMichael Ellerman return rc; 395e2186023SMichael Ellerman 396e2186023SMichael Ellerman out: 397e2186023SMichael Ellerman return count; 398e2186023SMichael Ellerman } 399e2186023SMichael Ellerman 400e2186023SMichael Ellerman static ssize_t show_subcores_per_core(struct device *dev, 401e2186023SMichael Ellerman struct device_attribute *attr, char *buf) 402e2186023SMichael Ellerman { 403e2186023SMichael Ellerman return sprintf(buf, "%x\n", subcores_per_core); 404e2186023SMichael Ellerman } 405e2186023SMichael Ellerman 406e2186023SMichael Ellerman static DEVICE_ATTR(subcores_per_core, 0644, 407e2186023SMichael Ellerman show_subcores_per_core, store_subcores_per_core); 408e2186023SMichael Ellerman 409e2186023SMichael Ellerman static int subcore_init(void) 410e2186023SMichael Ellerman { 411ce5732a2SMichael Neuling if (!cpu_has_feature(CPU_FTR_SUBCORE)) 412e2186023SMichael Ellerman return 0; 413e2186023SMichael Ellerman 414e2186023SMichael Ellerman /* 415e2186023SMichael Ellerman * We need all threads in a core to be present to split/unsplit so 416e2186023SMichael Ellerman * continue only if max_cpus are aligned to threads_per_core. 417e2186023SMichael Ellerman */ 418e2186023SMichael Ellerman if (setup_max_cpus % threads_per_core) 419e2186023SMichael Ellerman return 0; 420e2186023SMichael Ellerman 421e2186023SMichael Ellerman BUG_ON(!alloc_cpumask_var(&cpu_offline_mask, GFP_KERNEL)); 422e2186023SMichael Ellerman 423e2186023SMichael Ellerman set_subcores_per_core(1); 424e2186023SMichael Ellerman 425e2186023SMichael Ellerman return device_create_file(cpu_subsys.dev_root, 426e2186023SMichael Ellerman &dev_attr_subcores_per_core); 427e2186023SMichael Ellerman } 428e2186023SMichael Ellerman machine_device_initcall(powernv, subcore_init); 429