1 /* 2 * PowerNV setup code. 3 * 4 * Copyright 2011 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/cpu.h> 15 #include <linux/errno.h> 16 #include <linux/sched.h> 17 #include <linux/kernel.h> 18 #include <linux/tty.h> 19 #include <linux/reboot.h> 20 #include <linux/init.h> 21 #include <linux/console.h> 22 #include <linux/delay.h> 23 #include <linux/irq.h> 24 #include <linux/seq_file.h> 25 #include <linux/of.h> 26 #include <linux/of_fdt.h> 27 #include <linux/interrupt.h> 28 #include <linux/bug.h> 29 #include <linux/pci.h> 30 #include <linux/cpufreq.h> 31 32 #include <asm/machdep.h> 33 #include <asm/firmware.h> 34 #include <asm/xics.h> 35 #include <asm/rtas.h> 36 #include <asm/opal.h> 37 #include <asm/kexec.h> 38 39 #include "powernv.h" 40 41 static void __init pnv_setup_arch(void) 42 { 43 /* Initialize SMP */ 44 pnv_smp_init(); 45 46 /* Setup PCI */ 47 pnv_pci_init(); 48 49 /* Setup RTC and NVRAM callbacks */ 50 if (firmware_has_feature(FW_FEATURE_OPAL)) 51 opal_nvram_init(); 52 53 /* Enable NAP mode */ 54 powersave_nap = 1; 55 56 /* XXX PMCS */ 57 } 58 59 static void __init pnv_init_early(void) 60 { 61 /* 62 * Initialize the LPC bus now so that legacy serial 63 * ports can be found on it 64 */ 65 opal_lpc_init(); 66 67 #ifdef CONFIG_HVC_OPAL 68 if (firmware_has_feature(FW_FEATURE_OPAL)) 69 hvc_opal_init_early(); 70 else 71 #endif 72 add_preferred_console("hvc", 0, NULL); 73 } 74 75 static void __init pnv_init_IRQ(void) 76 { 77 xics_init(); 78 79 WARN_ON(!ppc_md.get_irq); 80 } 81 82 static void pnv_show_cpuinfo(struct seq_file *m) 83 { 84 struct device_node *root; 85 const char *model = ""; 86 87 root = of_find_node_by_path("/"); 88 if (root) 89 model = of_get_property(root, "model", NULL); 90 seq_printf(m, "machine\t\t: PowerNV %s\n", model); 91 if (firmware_has_feature(FW_FEATURE_OPALv3)) 92 seq_printf(m, "firmware\t: OPAL v3\n"); 93 else if (firmware_has_feature(FW_FEATURE_OPALv2)) 94 seq_printf(m, "firmware\t: OPAL v2\n"); 95 else if (firmware_has_feature(FW_FEATURE_OPAL)) 96 seq_printf(m, "firmware\t: OPAL v1\n"); 97 else 98 seq_printf(m, "firmware\t: BML\n"); 99 of_node_put(root); 100 } 101 102 static void pnv_prepare_going_down(void) 103 { 104 /* 105 * Disable all notifiers from OPAL, we can't 106 * service interrupts anymore anyway 107 */ 108 opal_notifier_disable(); 109 110 /* Soft disable interrupts */ 111 local_irq_disable(); 112 113 /* 114 * Return secondary CPUs to firwmare if a flash update 115 * is pending otherwise we will get all sort of error 116 * messages about CPU being stuck etc.. This will also 117 * have the side effect of hard disabling interrupts so 118 * past this point, the kernel is effectively dead. 119 */ 120 opal_flash_term_callback(); 121 } 122 123 static void __noreturn pnv_restart(char *cmd) 124 { 125 long rc = OPAL_BUSY; 126 127 pnv_prepare_going_down(); 128 129 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 130 rc = opal_cec_reboot(); 131 if (rc == OPAL_BUSY_EVENT) 132 opal_poll_events(NULL); 133 else 134 mdelay(10); 135 } 136 for (;;) 137 opal_poll_events(NULL); 138 } 139 140 static void __noreturn pnv_power_off(void) 141 { 142 long rc = OPAL_BUSY; 143 144 pnv_prepare_going_down(); 145 146 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 147 rc = opal_cec_power_down(0); 148 if (rc == OPAL_BUSY_EVENT) 149 opal_poll_events(NULL); 150 else 151 mdelay(10); 152 } 153 for (;;) 154 opal_poll_events(NULL); 155 } 156 157 static void __noreturn pnv_halt(void) 158 { 159 pnv_power_off(); 160 } 161 162 static void pnv_progress(char *s, unsigned short hex) 163 { 164 } 165 166 static int pnv_dma_set_mask(struct device *dev, u64 dma_mask) 167 { 168 if (dev_is_pci(dev)) 169 return pnv_pci_dma_set_mask(to_pci_dev(dev), dma_mask); 170 return __dma_set_mask(dev, dma_mask); 171 } 172 173 static void pnv_shutdown(void) 174 { 175 /* Let the PCI code clear up IODA tables */ 176 pnv_pci_shutdown(); 177 178 /* 179 * Stop OPAL activity: Unregister all OPAL interrupts so they 180 * don't fire up while we kexec and make sure all potentially 181 * DMA'ing ops are complete (such as dump retrieval). 182 */ 183 opal_shutdown(); 184 } 185 186 #ifdef CONFIG_KEXEC 187 static void pnv_kexec_wait_secondaries_down(void) 188 { 189 int my_cpu, i, notified = -1; 190 191 my_cpu = get_cpu(); 192 193 for_each_online_cpu(i) { 194 uint8_t status; 195 int64_t rc; 196 197 if (i == my_cpu) 198 continue; 199 200 for (;;) { 201 rc = opal_query_cpu_status(get_hard_smp_processor_id(i), 202 &status); 203 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED) 204 break; 205 barrier(); 206 if (i != notified) { 207 printk(KERN_INFO "kexec: waiting for cpu %d " 208 "(physical %d) to enter OPAL\n", 209 i, paca[i].hw_cpu_id); 210 notified = i; 211 } 212 } 213 } 214 } 215 216 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) 217 { 218 xics_kexec_teardown_cpu(secondary); 219 220 /* On OPAL v3, we return all CPUs to firmware */ 221 222 if (!firmware_has_feature(FW_FEATURE_OPALv3)) 223 return; 224 225 if (secondary) { 226 /* Return secondary CPUs to firmware on OPAL v3 */ 227 mb(); 228 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE; 229 mb(); 230 231 /* Return the CPU to OPAL */ 232 opal_return_cpu(); 233 } else if (crash_shutdown) { 234 /* 235 * On crash, we don't wait for secondaries to go 236 * down as they might be unreachable or hung, so 237 * instead we just wait a bit and move on. 238 */ 239 mdelay(1); 240 } else { 241 /* Primary waits for the secondaries to have reached OPAL */ 242 pnv_kexec_wait_secondaries_down(); 243 } 244 } 245 #endif /* CONFIG_KEXEC */ 246 247 static void __init pnv_setup_machdep_opal(void) 248 { 249 ppc_md.get_boot_time = opal_get_boot_time; 250 ppc_md.get_rtc_time = opal_get_rtc_time; 251 ppc_md.set_rtc_time = opal_set_rtc_time; 252 ppc_md.restart = pnv_restart; 253 ppc_md.power_off = pnv_power_off; 254 ppc_md.halt = pnv_halt; 255 ppc_md.machine_check_exception = opal_machine_check; 256 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery; 257 } 258 259 #ifdef CONFIG_PPC_POWERNV_RTAS 260 static void __init pnv_setup_machdep_rtas(void) 261 { 262 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) { 263 ppc_md.get_boot_time = rtas_get_boot_time; 264 ppc_md.get_rtc_time = rtas_get_rtc_time; 265 ppc_md.set_rtc_time = rtas_set_rtc_time; 266 } 267 ppc_md.restart = rtas_restart; 268 ppc_md.power_off = rtas_power_off; 269 ppc_md.halt = rtas_halt; 270 } 271 #endif /* CONFIG_PPC_POWERNV_RTAS */ 272 273 static int __init pnv_probe(void) 274 { 275 unsigned long root = of_get_flat_dt_root(); 276 277 if (!of_flat_dt_is_compatible(root, "ibm,powernv")) 278 return 0; 279 280 hpte_init_native(); 281 282 if (firmware_has_feature(FW_FEATURE_OPAL)) 283 pnv_setup_machdep_opal(); 284 #ifdef CONFIG_PPC_POWERNV_RTAS 285 else if (rtas.base) 286 pnv_setup_machdep_rtas(); 287 #endif /* CONFIG_PPC_POWERNV_RTAS */ 288 289 pr_debug("PowerNV detected !\n"); 290 291 return 1; 292 } 293 294 /* 295 * Returns the cpu frequency for 'cpu' in Hz. This is used by 296 * /proc/cpuinfo 297 */ 298 unsigned long pnv_get_proc_freq(unsigned int cpu) 299 { 300 unsigned long ret_freq; 301 302 ret_freq = cpufreq_quick_get(cpu) * 1000ul; 303 304 /* 305 * If the backend cpufreq driver does not exist, 306 * then fallback to old way of reporting the clockrate. 307 */ 308 if (!ret_freq) 309 ret_freq = ppc_proc_freq; 310 return ret_freq; 311 } 312 313 define_machine(powernv) { 314 .name = "PowerNV", 315 .probe = pnv_probe, 316 .init_early = pnv_init_early, 317 .setup_arch = pnv_setup_arch, 318 .init_IRQ = pnv_init_IRQ, 319 .show_cpuinfo = pnv_show_cpuinfo, 320 .get_proc_freq = pnv_get_proc_freq, 321 .progress = pnv_progress, 322 .machine_shutdown = pnv_shutdown, 323 .power_save = power7_idle, 324 .calibrate_decr = generic_calibrate_decr, 325 .dma_set_mask = pnv_dma_set_mask, 326 #ifdef CONFIG_KEXEC 327 .kexec_cpu_down = pnv_kexec_cpu_down, 328 #endif 329 }; 330