1 /* 2 * PowerNV setup code. 3 * 4 * Copyright 2011 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #undef DEBUG 13 14 #include <linux/cpu.h> 15 #include <linux/errno.h> 16 #include <linux/sched.h> 17 #include <linux/kernel.h> 18 #include <linux/tty.h> 19 #include <linux/reboot.h> 20 #include <linux/init.h> 21 #include <linux/console.h> 22 #include <linux/delay.h> 23 #include <linux/irq.h> 24 #include <linux/seq_file.h> 25 #include <linux/of.h> 26 #include <linux/of_fdt.h> 27 #include <linux/interrupt.h> 28 #include <linux/bug.h> 29 #include <linux/pci.h> 30 #include <linux/cpufreq.h> 31 32 #include <asm/machdep.h> 33 #include <asm/firmware.h> 34 #include <asm/xics.h> 35 #include <asm/xive.h> 36 #include <asm/opal.h> 37 #include <asm/kexec.h> 38 #include <asm/smp.h> 39 #include <asm/tm.h> 40 #include <asm/setup.h> 41 #include <asm/security_features.h> 42 43 #include "powernv.h" 44 45 46 static bool fw_feature_is(const char *state, const char *name, 47 struct device_node *fw_features) 48 { 49 struct device_node *np; 50 bool rc = false; 51 52 np = of_get_child_by_name(fw_features, name); 53 if (np) { 54 rc = of_property_read_bool(np, state); 55 of_node_put(np); 56 } 57 58 return rc; 59 } 60 61 static void init_fw_feat_flags(struct device_node *np) 62 { 63 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np)) 64 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31); 65 66 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np)) 67 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED); 68 69 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np)) 70 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30); 71 72 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np)) 73 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2); 74 75 if (fw_feature_is("enabled", "fw-l1d-thread-split", np)) 76 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV); 77 78 if (fw_feature_is("enabled", "fw-count-cache-disabled", np)) 79 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED); 80 81 /* 82 * The features below are enabled by default, so we instead look to see 83 * if firmware has *disabled* them, and clear them if so. 84 */ 85 if (fw_feature_is("disabled", "speculation-policy-favor-security", np)) 86 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); 87 88 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np)) 89 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); 90 91 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np)) 92 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV); 93 94 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np)) 95 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); 96 } 97 98 static void pnv_setup_rfi_flush(void) 99 { 100 struct device_node *np, *fw_features; 101 enum l1d_flush_type type; 102 bool enable; 103 104 /* Default to fallback in case fw-features are not available */ 105 type = L1D_FLUSH_FALLBACK; 106 107 np = of_find_node_by_name(NULL, "ibm,opal"); 108 fw_features = of_get_child_by_name(np, "fw-features"); 109 of_node_put(np); 110 111 if (fw_features) { 112 init_fw_feat_flags(fw_features); 113 of_node_put(fw_features); 114 115 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2)) 116 type = L1D_FLUSH_MTTRIG; 117 118 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30)) 119 type = L1D_FLUSH_ORI; 120 } 121 122 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \ 123 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \ 124 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV)); 125 126 setup_rfi_flush(type, enable); 127 } 128 129 static void __init pnv_setup_arch(void) 130 { 131 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); 132 133 pnv_setup_rfi_flush(); 134 setup_stf_barrier(); 135 136 /* Initialize SMP */ 137 pnv_smp_init(); 138 139 /* Setup PCI */ 140 pnv_pci_init(); 141 142 /* Setup RTC and NVRAM callbacks */ 143 if (firmware_has_feature(FW_FEATURE_OPAL)) 144 opal_nvram_init(); 145 146 /* Enable NAP mode */ 147 powersave_nap = 1; 148 149 /* XXX PMCS */ 150 } 151 152 static void __init pnv_init(void) 153 { 154 /* 155 * Initialize the LPC bus now so that legacy serial 156 * ports can be found on it 157 */ 158 opal_lpc_init(); 159 160 #ifdef CONFIG_HVC_OPAL 161 if (firmware_has_feature(FW_FEATURE_OPAL)) 162 hvc_opal_init_early(); 163 else 164 #endif 165 add_preferred_console("hvc", 0, NULL); 166 } 167 168 static void __init pnv_init_IRQ(void) 169 { 170 /* Try using a XIVE if available, otherwise use a XICS */ 171 if (!xive_native_init()) 172 xics_init(); 173 174 WARN_ON(!ppc_md.get_irq); 175 } 176 177 static void pnv_show_cpuinfo(struct seq_file *m) 178 { 179 struct device_node *root; 180 const char *model = ""; 181 182 root = of_find_node_by_path("/"); 183 if (root) 184 model = of_get_property(root, "model", NULL); 185 seq_printf(m, "machine\t\t: PowerNV %s\n", model); 186 if (firmware_has_feature(FW_FEATURE_OPAL)) 187 seq_printf(m, "firmware\t: OPAL\n"); 188 else 189 seq_printf(m, "firmware\t: BML\n"); 190 of_node_put(root); 191 if (radix_enabled()) 192 seq_printf(m, "MMU\t\t: Radix\n"); 193 else 194 seq_printf(m, "MMU\t\t: Hash\n"); 195 } 196 197 static void pnv_prepare_going_down(void) 198 { 199 /* 200 * Disable all notifiers from OPAL, we can't 201 * service interrupts anymore anyway 202 */ 203 opal_event_shutdown(); 204 205 /* Print flash update message if one is scheduled. */ 206 opal_flash_update_print_message(); 207 208 smp_send_stop(); 209 210 hard_irq_disable(); 211 } 212 213 static void __noreturn pnv_restart(char *cmd) 214 { 215 long rc = OPAL_BUSY; 216 217 pnv_prepare_going_down(); 218 219 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 220 rc = opal_cec_reboot(); 221 if (rc == OPAL_BUSY_EVENT) 222 opal_poll_events(NULL); 223 else 224 mdelay(10); 225 } 226 for (;;) 227 opal_poll_events(NULL); 228 } 229 230 static void __noreturn pnv_power_off(void) 231 { 232 long rc = OPAL_BUSY; 233 234 pnv_prepare_going_down(); 235 236 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 237 rc = opal_cec_power_down(0); 238 if (rc == OPAL_BUSY_EVENT) 239 opal_poll_events(NULL); 240 else 241 mdelay(10); 242 } 243 for (;;) 244 opal_poll_events(NULL); 245 } 246 247 static void __noreturn pnv_halt(void) 248 { 249 pnv_power_off(); 250 } 251 252 static void pnv_progress(char *s, unsigned short hex) 253 { 254 } 255 256 static void pnv_shutdown(void) 257 { 258 /* Let the PCI code clear up IODA tables */ 259 pnv_pci_shutdown(); 260 261 /* 262 * Stop OPAL activity: Unregister all OPAL interrupts so they 263 * don't fire up while we kexec and make sure all potentially 264 * DMA'ing ops are complete (such as dump retrieval). 265 */ 266 opal_shutdown(); 267 } 268 269 #ifdef CONFIG_KEXEC_CORE 270 static void pnv_kexec_wait_secondaries_down(void) 271 { 272 int my_cpu, i, notified = -1; 273 274 my_cpu = get_cpu(); 275 276 for_each_online_cpu(i) { 277 uint8_t status; 278 int64_t rc, timeout = 1000; 279 280 if (i == my_cpu) 281 continue; 282 283 for (;;) { 284 rc = opal_query_cpu_status(get_hard_smp_processor_id(i), 285 &status); 286 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED) 287 break; 288 barrier(); 289 if (i != notified) { 290 printk(KERN_INFO "kexec: waiting for cpu %d " 291 "(physical %d) to enter OPAL\n", 292 i, paca_ptrs[i]->hw_cpu_id); 293 notified = i; 294 } 295 296 /* 297 * On crash secondaries might be unreachable or hung, 298 * so timeout if we've waited too long 299 * */ 300 mdelay(1); 301 if (timeout-- == 0) { 302 printk(KERN_ERR "kexec: timed out waiting for " 303 "cpu %d (physical %d) to enter OPAL\n", 304 i, paca_ptrs[i]->hw_cpu_id); 305 break; 306 } 307 } 308 } 309 } 310 311 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) 312 { 313 u64 reinit_flags; 314 315 if (xive_enabled()) 316 xive_teardown_cpu(); 317 else 318 xics_kexec_teardown_cpu(secondary); 319 320 /* On OPAL, we return all CPUs to firmware */ 321 if (!firmware_has_feature(FW_FEATURE_OPAL)) 322 return; 323 324 if (secondary) { 325 /* Return secondary CPUs to firmware on OPAL v3 */ 326 mb(); 327 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE; 328 mb(); 329 330 /* Return the CPU to OPAL */ 331 opal_return_cpu(); 332 } else { 333 /* Primary waits for the secondaries to have reached OPAL */ 334 pnv_kexec_wait_secondaries_down(); 335 336 /* Switch XIVE back to emulation mode */ 337 if (xive_enabled()) 338 xive_shutdown(); 339 340 /* 341 * We might be running as little-endian - now that interrupts 342 * are disabled, reset the HILE bit to big-endian so we don't 343 * take interrupts in the wrong endian later 344 * 345 * We reinit to enable both radix and hash on P9 to ensure 346 * the mode used by the next kernel is always supported. 347 */ 348 reinit_flags = OPAL_REINIT_CPUS_HILE_BE; 349 if (cpu_has_feature(CPU_FTR_ARCH_300)) 350 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX | 351 OPAL_REINIT_CPUS_MMU_HASH; 352 opal_reinit_cpus(reinit_flags); 353 } 354 } 355 #endif /* CONFIG_KEXEC_CORE */ 356 357 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 358 static unsigned long pnv_memory_block_size(void) 359 { 360 return 256UL * 1024 * 1024; 361 } 362 #endif 363 364 static void __init pnv_setup_machdep_opal(void) 365 { 366 ppc_md.get_boot_time = opal_get_boot_time; 367 ppc_md.restart = pnv_restart; 368 pm_power_off = pnv_power_off; 369 ppc_md.halt = pnv_halt; 370 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */ 371 ppc_md.machine_check_exception = opal_machine_check; 372 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery; 373 ppc_md.hmi_exception_early = opal_hmi_exception_early; 374 ppc_md.handle_hmi_exception = opal_handle_hmi_exception; 375 } 376 377 static int __init pnv_probe(void) 378 { 379 if (!of_machine_is_compatible("ibm,powernv")) 380 return 0; 381 382 if (firmware_has_feature(FW_FEATURE_OPAL)) 383 pnv_setup_machdep_opal(); 384 385 pr_debug("PowerNV detected !\n"); 386 387 pnv_init(); 388 389 return 1; 390 } 391 392 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 393 void __init pnv_tm_init(void) 394 { 395 if (!firmware_has_feature(FW_FEATURE_OPAL) || 396 !pvr_version_is(PVR_POWER9) || 397 early_cpu_has_feature(CPU_FTR_TM)) 398 return; 399 400 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS) 401 return; 402 403 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n"); 404 cur_cpu_spec->cpu_features |= CPU_FTR_TM; 405 /* Make sure "normal" HTM is off (it should be) */ 406 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM; 407 /* Turn on no suspend mode, and HTM no SC */ 408 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \ 409 PPC_FEATURE2_HTM_NOSC; 410 tm_suspend_disabled = true; 411 } 412 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 413 414 /* 415 * Returns the cpu frequency for 'cpu' in Hz. This is used by 416 * /proc/cpuinfo 417 */ 418 static unsigned long pnv_get_proc_freq(unsigned int cpu) 419 { 420 unsigned long ret_freq; 421 422 ret_freq = cpufreq_get(cpu) * 1000ul; 423 424 /* 425 * If the backend cpufreq driver does not exist, 426 * then fallback to old way of reporting the clockrate. 427 */ 428 if (!ret_freq) 429 ret_freq = ppc_proc_freq; 430 return ret_freq; 431 } 432 433 define_machine(powernv) { 434 .name = "PowerNV", 435 .probe = pnv_probe, 436 .setup_arch = pnv_setup_arch, 437 .init_IRQ = pnv_init_IRQ, 438 .show_cpuinfo = pnv_show_cpuinfo, 439 .get_proc_freq = pnv_get_proc_freq, 440 .progress = pnv_progress, 441 .machine_shutdown = pnv_shutdown, 442 .power_save = NULL, 443 .calibrate_decr = generic_calibrate_decr, 444 #ifdef CONFIG_KEXEC_CORE 445 .kexec_cpu_down = pnv_kexec_cpu_down, 446 #endif 447 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 448 .memory_block_size = pnv_memory_block_size, 449 #endif 450 }; 451