1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * PowerNV setup code.
4  *
5  * Copyright 2011 IBM Corp.
6  */
7 
8 #undef DEBUG
9 
10 #include <linux/cpu.h>
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/tty.h>
15 #include <linux/reboot.h>
16 #include <linux/init.h>
17 #include <linux/console.h>
18 #include <linux/delay.h>
19 #include <linux/irq.h>
20 #include <linux/seq_file.h>
21 #include <linux/of.h>
22 #include <linux/of_fdt.h>
23 #include <linux/interrupt.h>
24 #include <linux/bug.h>
25 #include <linux/pci.h>
26 #include <linux/cpufreq.h>
27 #include <linux/memblock.h>
28 
29 #include <asm/machdep.h>
30 #include <asm/firmware.h>
31 #include <asm/xics.h>
32 #include <asm/xive.h>
33 #include <asm/opal.h>
34 #include <asm/kexec.h>
35 #include <asm/smp.h>
36 #include <asm/tm.h>
37 #include <asm/setup.h>
38 #include <asm/security_features.h>
39 
40 #include "powernv.h"
41 
42 
43 static bool fw_feature_is(const char *state, const char *name,
44 			  struct device_node *fw_features)
45 {
46 	struct device_node *np;
47 	bool rc = false;
48 
49 	np = of_get_child_by_name(fw_features, name);
50 	if (np) {
51 		rc = of_property_read_bool(np, state);
52 		of_node_put(np);
53 	}
54 
55 	return rc;
56 }
57 
58 static void init_fw_feat_flags(struct device_node *np)
59 {
60 	if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
61 		security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
62 
63 	if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
64 		security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
65 
66 	if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
67 		security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
68 
69 	if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
70 		security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
71 
72 	if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
73 		security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
74 
75 	if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
76 		security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
77 
78 	if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
79 		security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
80 
81 	if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
82 		security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
83 
84 	/*
85 	 * The features below are enabled by default, so we instead look to see
86 	 * if firmware has *disabled* them, and clear them if so.
87 	 */
88 	if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
89 		security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
90 
91 	if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
92 		security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
93 
94 	if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
95 		security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
96 
97 	if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
98 		security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
99 }
100 
101 static void pnv_setup_rfi_flush(void)
102 {
103 	struct device_node *np, *fw_features;
104 	enum l1d_flush_type type;
105 	bool enable;
106 
107 	/* Default to fallback in case fw-features are not available */
108 	type = L1D_FLUSH_FALLBACK;
109 
110 	np = of_find_node_by_name(NULL, "ibm,opal");
111 	fw_features = of_get_child_by_name(np, "fw-features");
112 	of_node_put(np);
113 
114 	if (fw_features) {
115 		init_fw_feat_flags(fw_features);
116 		of_node_put(fw_features);
117 
118 		if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
119 			type = L1D_FLUSH_MTTRIG;
120 
121 		if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
122 			type = L1D_FLUSH_ORI;
123 	}
124 
125 	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
126 		 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR)   || \
127 		  security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
128 
129 	setup_rfi_flush(type, enable);
130 	setup_count_cache_flush();
131 }
132 
133 static void __init pnv_check_guarded_cores(void)
134 {
135 	struct device_node *dn;
136 	int bad_count = 0;
137 
138 	for_each_node_by_type(dn, "cpu") {
139 		if (of_property_match_string(dn, "status", "bad") >= 0)
140 			bad_count++;
141 	};
142 
143 	if (bad_count) {
144 		printk("  _     _______________\n");
145 		pr_cont(" | |   /               \\\n");
146 		pr_cont(" | |   |    WARNING!   |\n");
147 		pr_cont(" | |   |               |\n");
148 		pr_cont(" | |   | It looks like |\n");
149 		pr_cont(" |_|   |  you have %*d |\n", 3, bad_count);
150 		pr_cont("  _    | guarded cores |\n");
151 		pr_cont(" (_)   \\_______________/\n");
152 	}
153 }
154 
155 static void __init pnv_setup_arch(void)
156 {
157 	set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
158 
159 	pnv_setup_rfi_flush();
160 	setup_stf_barrier();
161 
162 	/* Initialize SMP */
163 	pnv_smp_init();
164 
165 	/* Setup PCI */
166 	pnv_pci_init();
167 
168 	/* Setup RTC and NVRAM callbacks */
169 	if (firmware_has_feature(FW_FEATURE_OPAL))
170 		opal_nvram_init();
171 
172 	/* Enable NAP mode */
173 	powersave_nap = 1;
174 
175 	pnv_check_guarded_cores();
176 
177 	/* XXX PMCS */
178 }
179 
180 static void __init pnv_init(void)
181 {
182 	/*
183 	 * Initialize the LPC bus now so that legacy serial
184 	 * ports can be found on it
185 	 */
186 	opal_lpc_init();
187 
188 #ifdef CONFIG_HVC_OPAL
189 	if (firmware_has_feature(FW_FEATURE_OPAL))
190 		hvc_opal_init_early();
191 	else
192 #endif
193 		add_preferred_console("hvc", 0, NULL);
194 
195 	if (!radix_enabled()) {
196 		int i;
197 
198 		/* Allocate per cpu area to save old slb contents during MCE */
199 		for_each_possible_cpu(i)
200 			paca_ptrs[i]->mce_faulty_slbs = memblock_alloc_node(mmu_slb_size, __alignof__(*paca_ptrs[i]->mce_faulty_slbs), cpu_to_node(i));
201 	}
202 }
203 
204 static void __init pnv_init_IRQ(void)
205 {
206 	/* Try using a XIVE if available, otherwise use a XICS */
207 	if (!xive_native_init())
208 		xics_init();
209 
210 	WARN_ON(!ppc_md.get_irq);
211 }
212 
213 static void pnv_show_cpuinfo(struct seq_file *m)
214 {
215 	struct device_node *root;
216 	const char *model = "";
217 
218 	root = of_find_node_by_path("/");
219 	if (root)
220 		model = of_get_property(root, "model", NULL);
221 	seq_printf(m, "machine\t\t: PowerNV %s\n", model);
222 	if (firmware_has_feature(FW_FEATURE_OPAL))
223 		seq_printf(m, "firmware\t: OPAL\n");
224 	else
225 		seq_printf(m, "firmware\t: BML\n");
226 	of_node_put(root);
227 	if (radix_enabled())
228 		seq_printf(m, "MMU\t\t: Radix\n");
229 	else
230 		seq_printf(m, "MMU\t\t: Hash\n");
231 }
232 
233 static void pnv_prepare_going_down(void)
234 {
235 	/*
236 	 * Disable all notifiers from OPAL, we can't
237 	 * service interrupts anymore anyway
238 	 */
239 	opal_event_shutdown();
240 
241 	/* Print flash update message if one is scheduled. */
242 	opal_flash_update_print_message();
243 
244 	smp_send_stop();
245 
246 	hard_irq_disable();
247 }
248 
249 static void  __noreturn pnv_restart(char *cmd)
250 {
251 	long rc;
252 
253 	pnv_prepare_going_down();
254 
255 	do {
256 		if (!cmd || !strlen(cmd))
257 			rc = opal_cec_reboot();
258 		else if (strcmp(cmd, "full") == 0)
259 			rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL);
260 		else if (strcmp(cmd, "mpipl") == 0)
261 			rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL);
262 		else if (strcmp(cmd, "error") == 0)
263 			rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL);
264 		else if (strcmp(cmd, "fast") == 0)
265 			rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL);
266 		else
267 			rc = OPAL_UNSUPPORTED;
268 
269 		if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
270 			/* Opal is busy wait for some time and retry */
271 			opal_poll_events(NULL);
272 			mdelay(10);
273 
274 		} else	if (cmd && rc) {
275 			/* Unknown error while issuing reboot */
276 			if (rc == OPAL_UNSUPPORTED)
277 				pr_err("Unsupported '%s' reboot.\n", cmd);
278 			else
279 				pr_err("Unable to issue '%s' reboot. Err=%ld\n",
280 				       cmd, rc);
281 			pr_info("Forcing a cec-reboot\n");
282 			cmd = NULL;
283 			rc = OPAL_BUSY;
284 
285 		} else if (rc != OPAL_SUCCESS) {
286 			/* Unknown error while issuing cec-reboot */
287 			pr_err("Unable to reboot. Err=%ld\n", rc);
288 		}
289 
290 	} while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT);
291 
292 	for (;;)
293 		opal_poll_events(NULL);
294 }
295 
296 static void __noreturn pnv_power_off(void)
297 {
298 	long rc = OPAL_BUSY;
299 
300 	pnv_prepare_going_down();
301 
302 	while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
303 		rc = opal_cec_power_down(0);
304 		if (rc == OPAL_BUSY_EVENT)
305 			opal_poll_events(NULL);
306 		else
307 			mdelay(10);
308 	}
309 	for (;;)
310 		opal_poll_events(NULL);
311 }
312 
313 static void __noreturn pnv_halt(void)
314 {
315 	pnv_power_off();
316 }
317 
318 static void pnv_progress(char *s, unsigned short hex)
319 {
320 }
321 
322 static void pnv_shutdown(void)
323 {
324 	/* Let the PCI code clear up IODA tables */
325 	pnv_pci_shutdown();
326 
327 	/*
328 	 * Stop OPAL activity: Unregister all OPAL interrupts so they
329 	 * don't fire up while we kexec and make sure all potentially
330 	 * DMA'ing ops are complete (such as dump retrieval).
331 	 */
332 	opal_shutdown();
333 }
334 
335 #ifdef CONFIG_KEXEC_CORE
336 static void pnv_kexec_wait_secondaries_down(void)
337 {
338 	int my_cpu, i, notified = -1;
339 
340 	my_cpu = get_cpu();
341 
342 	for_each_online_cpu(i) {
343 		uint8_t status;
344 		int64_t rc, timeout = 1000;
345 
346 		if (i == my_cpu)
347 			continue;
348 
349 		for (;;) {
350 			rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
351 						   &status);
352 			if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
353 				break;
354 			barrier();
355 			if (i != notified) {
356 				printk(KERN_INFO "kexec: waiting for cpu %d "
357 				       "(physical %d) to enter OPAL\n",
358 				       i, paca_ptrs[i]->hw_cpu_id);
359 				notified = i;
360 			}
361 
362 			/*
363 			 * On crash secondaries might be unreachable or hung,
364 			 * so timeout if we've waited too long
365 			 * */
366 			mdelay(1);
367 			if (timeout-- == 0) {
368 				printk(KERN_ERR "kexec: timed out waiting for "
369 				       "cpu %d (physical %d) to enter OPAL\n",
370 				       i, paca_ptrs[i]->hw_cpu_id);
371 				break;
372 			}
373 		}
374 	}
375 }
376 
377 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
378 {
379 	u64 reinit_flags;
380 
381 	if (xive_enabled())
382 		xive_teardown_cpu();
383 	else
384 		xics_kexec_teardown_cpu(secondary);
385 
386 	/* On OPAL, we return all CPUs to firmware */
387 	if (!firmware_has_feature(FW_FEATURE_OPAL))
388 		return;
389 
390 	if (secondary) {
391 		/* Return secondary CPUs to firmware on OPAL v3 */
392 		mb();
393 		get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
394 		mb();
395 
396 		/* Return the CPU to OPAL */
397 		opal_return_cpu();
398 	} else {
399 		/* Primary waits for the secondaries to have reached OPAL */
400 		pnv_kexec_wait_secondaries_down();
401 
402 		/* Switch XIVE back to emulation mode */
403 		if (xive_enabled())
404 			xive_shutdown();
405 
406 		/*
407 		 * We might be running as little-endian - now that interrupts
408 		 * are disabled, reset the HILE bit to big-endian so we don't
409 		 * take interrupts in the wrong endian later
410 		 *
411 		 * We reinit to enable both radix and hash on P9 to ensure
412 		 * the mode used by the next kernel is always supported.
413 		 */
414 		reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
415 		if (cpu_has_feature(CPU_FTR_ARCH_300))
416 			reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
417 				OPAL_REINIT_CPUS_MMU_HASH;
418 		opal_reinit_cpus(reinit_flags);
419 	}
420 }
421 #endif /* CONFIG_KEXEC_CORE */
422 
423 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
424 static unsigned long pnv_memory_block_size(void)
425 {
426 	/*
427 	 * We map the kernel linear region with 1GB large pages on radix. For
428 	 * memory hot unplug to work our memory block size must be at least
429 	 * this size.
430 	 */
431 	if (radix_enabled())
432 		return radix_mem_block_size;
433 	else
434 		return 256UL * 1024 * 1024;
435 }
436 #endif
437 
438 static void __init pnv_setup_machdep_opal(void)
439 {
440 	ppc_md.get_boot_time = opal_get_boot_time;
441 	ppc_md.restart = pnv_restart;
442 	pm_power_off = pnv_power_off;
443 	ppc_md.halt = pnv_halt;
444 	/* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
445 	ppc_md.machine_check_exception = opal_machine_check;
446 	ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
447 	if (opal_check_token(OPAL_HANDLE_HMI2))
448 		ppc_md.hmi_exception_early = opal_hmi_exception_early2;
449 	else
450 		ppc_md.hmi_exception_early = opal_hmi_exception_early;
451 	ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
452 }
453 
454 static int __init pnv_probe(void)
455 {
456 	if (!of_machine_is_compatible("ibm,powernv"))
457 		return 0;
458 
459 	if (firmware_has_feature(FW_FEATURE_OPAL))
460 		pnv_setup_machdep_opal();
461 
462 	pr_debug("PowerNV detected !\n");
463 
464 	pnv_init();
465 
466 	return 1;
467 }
468 
469 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
470 void __init pnv_tm_init(void)
471 {
472 	if (!firmware_has_feature(FW_FEATURE_OPAL) ||
473 	    !pvr_version_is(PVR_POWER9) ||
474 	    early_cpu_has_feature(CPU_FTR_TM))
475 		return;
476 
477 	if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
478 		return;
479 
480 	pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
481 	cur_cpu_spec->cpu_features |= CPU_FTR_TM;
482 	/* Make sure "normal" HTM is off (it should be) */
483 	cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
484 	/* Turn on no suspend mode, and HTM no SC */
485 	cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
486 					    PPC_FEATURE2_HTM_NOSC;
487 	tm_suspend_disabled = true;
488 }
489 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
490 
491 /*
492  * Returns the cpu frequency for 'cpu' in Hz. This is used by
493  * /proc/cpuinfo
494  */
495 static unsigned long pnv_get_proc_freq(unsigned int cpu)
496 {
497 	unsigned long ret_freq;
498 
499 	ret_freq = cpufreq_get(cpu) * 1000ul;
500 
501 	/*
502 	 * If the backend cpufreq driver does not exist,
503          * then fallback to old way of reporting the clockrate.
504 	 */
505 	if (!ret_freq)
506 		ret_freq = ppc_proc_freq;
507 	return ret_freq;
508 }
509 
510 static long pnv_machine_check_early(struct pt_regs *regs)
511 {
512 	long handled = 0;
513 
514 	if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
515 		handled = cur_cpu_spec->machine_check_early(regs);
516 
517 	return handled;
518 }
519 
520 define_machine(powernv) {
521 	.name			= "PowerNV",
522 	.probe			= pnv_probe,
523 	.setup_arch		= pnv_setup_arch,
524 	.init_IRQ		= pnv_init_IRQ,
525 	.show_cpuinfo		= pnv_show_cpuinfo,
526 	.get_proc_freq          = pnv_get_proc_freq,
527 	.progress		= pnv_progress,
528 	.machine_shutdown	= pnv_shutdown,
529 	.power_save             = NULL,
530 	.calibrate_decr		= generic_calibrate_decr,
531 	.machine_check_early	= pnv_machine_check_early,
532 #ifdef CONFIG_KEXEC_CORE
533 	.kexec_cpu_down		= pnv_kexec_cpu_down,
534 #endif
535 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
536 	.memory_block_size	= pnv_memory_block_size,
537 #endif
538 };
539