1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV setup code. 4 * 5 * Copyright 2011 IBM Corp. 6 */ 7 8 #undef DEBUG 9 10 #include <linux/cpu.h> 11 #include <linux/errno.h> 12 #include <linux/sched.h> 13 #include <linux/kernel.h> 14 #include <linux/tty.h> 15 #include <linux/reboot.h> 16 #include <linux/init.h> 17 #include <linux/console.h> 18 #include <linux/delay.h> 19 #include <linux/irq.h> 20 #include <linux/seq_file.h> 21 #include <linux/of.h> 22 #include <linux/of_fdt.h> 23 #include <linux/interrupt.h> 24 #include <linux/bug.h> 25 #include <linux/pci.h> 26 #include <linux/cpufreq.h> 27 #include <linux/memblock.h> 28 29 #include <asm/machdep.h> 30 #include <asm/firmware.h> 31 #include <asm/xics.h> 32 #include <asm/xive.h> 33 #include <asm/opal.h> 34 #include <asm/kexec.h> 35 #include <asm/smp.h> 36 #include <asm/tm.h> 37 #include <asm/setup.h> 38 #include <asm/security_features.h> 39 40 #include "powernv.h" 41 42 43 static bool __init fw_feature_is(const char *state, const char *name, 44 struct device_node *fw_features) 45 { 46 struct device_node *np; 47 bool rc = false; 48 49 np = of_get_child_by_name(fw_features, name); 50 if (np) { 51 rc = of_property_read_bool(np, state); 52 of_node_put(np); 53 } 54 55 return rc; 56 } 57 58 static void __init init_fw_feat_flags(struct device_node *np) 59 { 60 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np)) 61 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31); 62 63 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np)) 64 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED); 65 66 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np)) 67 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30); 68 69 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np)) 70 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2); 71 72 if (fw_feature_is("enabled", "fw-l1d-thread-split", np)) 73 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV); 74 75 if (fw_feature_is("enabled", "fw-count-cache-disabled", np)) 76 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED); 77 78 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np)) 79 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST); 80 81 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np)) 82 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE); 83 84 /* 85 * The features below are enabled by default, so we instead look to see 86 * if firmware has *disabled* them, and clear them if so. 87 */ 88 if (fw_feature_is("disabled", "speculation-policy-favor-security", np)) 89 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); 90 91 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np)) 92 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); 93 94 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np)) 95 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV); 96 97 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np)) 98 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); 99 } 100 101 static void __init pnv_setup_security_mitigations(void) 102 { 103 struct device_node *np, *fw_features; 104 enum l1d_flush_type type; 105 bool enable; 106 107 /* Default to fallback in case fw-features are not available */ 108 type = L1D_FLUSH_FALLBACK; 109 110 np = of_find_node_by_name(NULL, "ibm,opal"); 111 fw_features = of_get_child_by_name(np, "fw-features"); 112 of_node_put(np); 113 114 if (fw_features) { 115 init_fw_feat_flags(fw_features); 116 of_node_put(fw_features); 117 118 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2)) 119 type = L1D_FLUSH_MTTRIG; 120 121 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30)) 122 type = L1D_FLUSH_ORI; 123 } 124 125 /* 126 * The issues addressed by the entry and uaccess flush don't affect P7 127 * or P8, so on bare metal disable them explicitly in case firmware does 128 * not include the features to disable them. POWER9 and newer processors 129 * should have the appropriate firmware flags. 130 */ 131 if (pvr_version_is(PVR_POWER7) || pvr_version_is(PVR_POWER7p) || 132 pvr_version_is(PVR_POWER8E) || pvr_version_is(PVR_POWER8NVL) || 133 pvr_version_is(PVR_POWER8)) { 134 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY); 135 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS); 136 } 137 138 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \ 139 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \ 140 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV)); 141 142 setup_rfi_flush(type, enable); 143 setup_count_cache_flush(); 144 145 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 146 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY); 147 setup_entry_flush(enable); 148 149 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 150 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS); 151 setup_uaccess_flush(enable); 152 153 setup_stf_barrier(); 154 } 155 156 static void __init pnv_check_guarded_cores(void) 157 { 158 struct device_node *dn; 159 int bad_count = 0; 160 161 for_each_node_by_type(dn, "cpu") { 162 if (of_property_match_string(dn, "status", "bad") >= 0) 163 bad_count++; 164 } 165 166 if (bad_count) { 167 printk(" _ _______________\n"); 168 pr_cont(" | | / \\\n"); 169 pr_cont(" | | | WARNING! |\n"); 170 pr_cont(" | | | |\n"); 171 pr_cont(" | | | It looks like |\n"); 172 pr_cont(" |_| | you have %*d |\n", 3, bad_count); 173 pr_cont(" _ | guarded cores |\n"); 174 pr_cont(" (_) \\_______________/\n"); 175 } 176 } 177 178 static void __init pnv_setup_arch(void) 179 { 180 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); 181 182 pnv_setup_security_mitigations(); 183 184 /* Initialize SMP */ 185 pnv_smp_init(); 186 187 /* Setup RTC and NVRAM callbacks */ 188 if (firmware_has_feature(FW_FEATURE_OPAL)) 189 opal_nvram_init(); 190 191 /* Enable NAP mode */ 192 powersave_nap = 1; 193 194 pnv_check_guarded_cores(); 195 196 /* XXX PMCS */ 197 } 198 199 static void __init pnv_init(void) 200 { 201 /* 202 * Initialize the LPC bus now so that legacy serial 203 * ports can be found on it 204 */ 205 opal_lpc_init(); 206 207 #ifdef CONFIG_HVC_OPAL 208 if (firmware_has_feature(FW_FEATURE_OPAL)) 209 hvc_opal_init_early(); 210 else 211 #endif 212 add_preferred_console("hvc", 0, NULL); 213 214 #ifdef CONFIG_PPC_64S_HASH_MMU 215 if (!radix_enabled()) { 216 size_t size = sizeof(struct slb_entry) * mmu_slb_size; 217 int i; 218 219 /* Allocate per cpu area to save old slb contents during MCE */ 220 for_each_possible_cpu(i) { 221 paca_ptrs[i]->mce_faulty_slbs = 222 memblock_alloc_node(size, 223 __alignof__(struct slb_entry), 224 cpu_to_node(i)); 225 } 226 } 227 #endif 228 } 229 230 static void __init pnv_init_IRQ(void) 231 { 232 /* Try using a XIVE if available, otherwise use a XICS */ 233 if (!xive_native_init()) 234 xics_init(); 235 236 WARN_ON(!ppc_md.get_irq); 237 } 238 239 static void pnv_show_cpuinfo(struct seq_file *m) 240 { 241 struct device_node *root; 242 const char *model = ""; 243 244 root = of_find_node_by_path("/"); 245 if (root) 246 model = of_get_property(root, "model", NULL); 247 seq_printf(m, "machine\t\t: PowerNV %s\n", model); 248 if (firmware_has_feature(FW_FEATURE_OPAL)) 249 seq_printf(m, "firmware\t: OPAL\n"); 250 else 251 seq_printf(m, "firmware\t: BML\n"); 252 of_node_put(root); 253 if (radix_enabled()) 254 seq_printf(m, "MMU\t\t: Radix\n"); 255 else 256 seq_printf(m, "MMU\t\t: Hash\n"); 257 } 258 259 static void pnv_prepare_going_down(void) 260 { 261 /* 262 * Disable all notifiers from OPAL, we can't 263 * service interrupts anymore anyway 264 */ 265 opal_event_shutdown(); 266 267 /* Print flash update message if one is scheduled. */ 268 opal_flash_update_print_message(); 269 270 smp_send_stop(); 271 272 hard_irq_disable(); 273 } 274 275 static void __noreturn pnv_restart(char *cmd) 276 { 277 long rc; 278 279 pnv_prepare_going_down(); 280 281 do { 282 if (!cmd || !strlen(cmd)) 283 rc = opal_cec_reboot(); 284 else if (strcmp(cmd, "full") == 0) 285 rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL); 286 else if (strcmp(cmd, "mpipl") == 0) 287 rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL); 288 else if (strcmp(cmd, "error") == 0) 289 rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL); 290 else if (strcmp(cmd, "fast") == 0) 291 rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL); 292 else 293 rc = OPAL_UNSUPPORTED; 294 295 if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 296 /* Opal is busy wait for some time and retry */ 297 opal_poll_events(NULL); 298 mdelay(10); 299 300 } else if (cmd && rc) { 301 /* Unknown error while issuing reboot */ 302 if (rc == OPAL_UNSUPPORTED) 303 pr_err("Unsupported '%s' reboot.\n", cmd); 304 else 305 pr_err("Unable to issue '%s' reboot. Err=%ld\n", 306 cmd, rc); 307 pr_info("Forcing a cec-reboot\n"); 308 cmd = NULL; 309 rc = OPAL_BUSY; 310 311 } else if (rc != OPAL_SUCCESS) { 312 /* Unknown error while issuing cec-reboot */ 313 pr_err("Unable to reboot. Err=%ld\n", rc); 314 } 315 316 } while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT); 317 318 for (;;) 319 opal_poll_events(NULL); 320 } 321 322 static void __noreturn pnv_power_off(void) 323 { 324 long rc = OPAL_BUSY; 325 326 pnv_prepare_going_down(); 327 328 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 329 rc = opal_cec_power_down(0); 330 if (rc == OPAL_BUSY_EVENT) 331 opal_poll_events(NULL); 332 else 333 mdelay(10); 334 } 335 for (;;) 336 opal_poll_events(NULL); 337 } 338 339 static void __noreturn pnv_halt(void) 340 { 341 pnv_power_off(); 342 } 343 344 static void pnv_progress(char *s, unsigned short hex) 345 { 346 } 347 348 static void pnv_shutdown(void) 349 { 350 /* Let the PCI code clear up IODA tables */ 351 pnv_pci_shutdown(); 352 353 /* 354 * Stop OPAL activity: Unregister all OPAL interrupts so they 355 * don't fire up while we kexec and make sure all potentially 356 * DMA'ing ops are complete (such as dump retrieval). 357 */ 358 opal_shutdown(); 359 } 360 361 #ifdef CONFIG_KEXEC_CORE 362 static void pnv_kexec_wait_secondaries_down(void) 363 { 364 int my_cpu, i, notified = -1; 365 366 my_cpu = get_cpu(); 367 368 for_each_online_cpu(i) { 369 uint8_t status; 370 int64_t rc, timeout = 1000; 371 372 if (i == my_cpu) 373 continue; 374 375 for (;;) { 376 rc = opal_query_cpu_status(get_hard_smp_processor_id(i), 377 &status); 378 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED) 379 break; 380 barrier(); 381 if (i != notified) { 382 printk(KERN_INFO "kexec: waiting for cpu %d " 383 "(physical %d) to enter OPAL\n", 384 i, paca_ptrs[i]->hw_cpu_id); 385 notified = i; 386 } 387 388 /* 389 * On crash secondaries might be unreachable or hung, 390 * so timeout if we've waited too long 391 * */ 392 mdelay(1); 393 if (timeout-- == 0) { 394 printk(KERN_ERR "kexec: timed out waiting for " 395 "cpu %d (physical %d) to enter OPAL\n", 396 i, paca_ptrs[i]->hw_cpu_id); 397 break; 398 } 399 } 400 } 401 } 402 403 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) 404 { 405 u64 reinit_flags; 406 407 if (xive_enabled()) 408 xive_teardown_cpu(); 409 else 410 xics_kexec_teardown_cpu(secondary); 411 412 /* On OPAL, we return all CPUs to firmware */ 413 if (!firmware_has_feature(FW_FEATURE_OPAL)) 414 return; 415 416 if (secondary) { 417 /* Return secondary CPUs to firmware on OPAL v3 */ 418 mb(); 419 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE; 420 mb(); 421 422 /* Return the CPU to OPAL */ 423 opal_return_cpu(); 424 } else { 425 /* Primary waits for the secondaries to have reached OPAL */ 426 pnv_kexec_wait_secondaries_down(); 427 428 /* Switch XIVE back to emulation mode */ 429 if (xive_enabled()) 430 xive_shutdown(); 431 432 /* 433 * We might be running as little-endian - now that interrupts 434 * are disabled, reset the HILE bit to big-endian so we don't 435 * take interrupts in the wrong endian later 436 * 437 * We reinit to enable both radix and hash on P9 to ensure 438 * the mode used by the next kernel is always supported. 439 */ 440 reinit_flags = OPAL_REINIT_CPUS_HILE_BE; 441 if (cpu_has_feature(CPU_FTR_ARCH_300)) 442 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX | 443 OPAL_REINIT_CPUS_MMU_HASH; 444 opal_reinit_cpus(reinit_flags); 445 } 446 } 447 #endif /* CONFIG_KEXEC_CORE */ 448 449 #ifdef CONFIG_MEMORY_HOTPLUG 450 static unsigned long pnv_memory_block_size(void) 451 { 452 /* 453 * We map the kernel linear region with 1GB large pages on radix. For 454 * memory hot unplug to work our memory block size must be at least 455 * this size. 456 */ 457 if (radix_enabled()) 458 return radix_mem_block_size; 459 else 460 return 256UL * 1024 * 1024; 461 } 462 #endif 463 464 static void __init pnv_setup_machdep_opal(void) 465 { 466 ppc_md.get_boot_time = opal_get_boot_time; 467 ppc_md.restart = pnv_restart; 468 pm_power_off = pnv_power_off; 469 ppc_md.halt = pnv_halt; 470 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */ 471 ppc_md.machine_check_exception = opal_machine_check; 472 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery; 473 if (opal_check_token(OPAL_HANDLE_HMI2)) 474 ppc_md.hmi_exception_early = opal_hmi_exception_early2; 475 else 476 ppc_md.hmi_exception_early = opal_hmi_exception_early; 477 ppc_md.handle_hmi_exception = opal_handle_hmi_exception; 478 } 479 480 static int __init pnv_probe(void) 481 { 482 if (!of_machine_is_compatible("ibm,powernv")) 483 return 0; 484 485 if (firmware_has_feature(FW_FEATURE_OPAL)) 486 pnv_setup_machdep_opal(); 487 488 pr_debug("PowerNV detected !\n"); 489 490 pnv_init(); 491 492 return 1; 493 } 494 495 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 496 void __init pnv_tm_init(void) 497 { 498 if (!firmware_has_feature(FW_FEATURE_OPAL) || 499 !pvr_version_is(PVR_POWER9) || 500 early_cpu_has_feature(CPU_FTR_TM)) 501 return; 502 503 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS) 504 return; 505 506 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n"); 507 cur_cpu_spec->cpu_features |= CPU_FTR_TM; 508 /* Make sure "normal" HTM is off (it should be) */ 509 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM; 510 /* Turn on no suspend mode, and HTM no SC */ 511 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \ 512 PPC_FEATURE2_HTM_NOSC; 513 tm_suspend_disabled = true; 514 } 515 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 516 517 /* 518 * Returns the cpu frequency for 'cpu' in Hz. This is used by 519 * /proc/cpuinfo 520 */ 521 static unsigned long pnv_get_proc_freq(unsigned int cpu) 522 { 523 unsigned long ret_freq; 524 525 ret_freq = cpufreq_get(cpu) * 1000ul; 526 527 /* 528 * If the backend cpufreq driver does not exist, 529 * then fallback to old way of reporting the clockrate. 530 */ 531 if (!ret_freq) 532 ret_freq = ppc_proc_freq; 533 return ret_freq; 534 } 535 536 static long pnv_machine_check_early(struct pt_regs *regs) 537 { 538 long handled = 0; 539 540 if (cur_cpu_spec && cur_cpu_spec->machine_check_early) 541 handled = cur_cpu_spec->machine_check_early(regs); 542 543 return handled; 544 } 545 546 define_machine(powernv) { 547 .name = "PowerNV", 548 .probe = pnv_probe, 549 .setup_arch = pnv_setup_arch, 550 .init_IRQ = pnv_init_IRQ, 551 .show_cpuinfo = pnv_show_cpuinfo, 552 .get_proc_freq = pnv_get_proc_freq, 553 .discover_phbs = pnv_pci_init, 554 .progress = pnv_progress, 555 .machine_shutdown = pnv_shutdown, 556 .power_save = NULL, 557 .calibrate_decr = generic_calibrate_decr, 558 .machine_check_early = pnv_machine_check_early, 559 #ifdef CONFIG_KEXEC_CORE 560 .kexec_cpu_down = pnv_kexec_cpu_down, 561 #endif 562 #ifdef CONFIG_MEMORY_HOTPLUG 563 .memory_block_size = pnv_memory_block_size, 564 #endif 565 }; 566