1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV setup code. 4 * 5 * Copyright 2011 IBM Corp. 6 */ 7 8 #undef DEBUG 9 10 #include <linux/cpu.h> 11 #include <linux/errno.h> 12 #include <linux/sched.h> 13 #include <linux/kernel.h> 14 #include <linux/tty.h> 15 #include <linux/reboot.h> 16 #include <linux/init.h> 17 #include <linux/console.h> 18 #include <linux/delay.h> 19 #include <linux/irq.h> 20 #include <linux/seq_file.h> 21 #include <linux/of.h> 22 #include <linux/of_fdt.h> 23 #include <linux/interrupt.h> 24 #include <linux/bug.h> 25 #include <linux/pci.h> 26 #include <linux/cpufreq.h> 27 #include <linux/memblock.h> 28 29 #include <asm/machdep.h> 30 #include <asm/firmware.h> 31 #include <asm/xics.h> 32 #include <asm/xive.h> 33 #include <asm/opal.h> 34 #include <asm/kexec.h> 35 #include <asm/smp.h> 36 #include <asm/tm.h> 37 #include <asm/setup.h> 38 #include <asm/security_features.h> 39 40 #include "powernv.h" 41 42 43 static bool fw_feature_is(const char *state, const char *name, 44 struct device_node *fw_features) 45 { 46 struct device_node *np; 47 bool rc = false; 48 49 np = of_get_child_by_name(fw_features, name); 50 if (np) { 51 rc = of_property_read_bool(np, state); 52 of_node_put(np); 53 } 54 55 return rc; 56 } 57 58 static void init_fw_feat_flags(struct device_node *np) 59 { 60 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np)) 61 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31); 62 63 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np)) 64 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED); 65 66 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np)) 67 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30); 68 69 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np)) 70 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2); 71 72 if (fw_feature_is("enabled", "fw-l1d-thread-split", np)) 73 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV); 74 75 if (fw_feature_is("enabled", "fw-count-cache-disabled", np)) 76 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED); 77 78 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np)) 79 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST); 80 81 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np)) 82 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE); 83 84 /* 85 * The features below are enabled by default, so we instead look to see 86 * if firmware has *disabled* them, and clear them if so. 87 */ 88 if (fw_feature_is("disabled", "speculation-policy-favor-security", np)) 89 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); 90 91 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np)) 92 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); 93 94 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np)) 95 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV); 96 97 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np)) 98 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); 99 } 100 101 static void pnv_setup_security_mitigations(void) 102 { 103 struct device_node *np, *fw_features; 104 enum l1d_flush_type type; 105 bool enable; 106 107 /* Default to fallback in case fw-features are not available */ 108 type = L1D_FLUSH_FALLBACK; 109 110 np = of_find_node_by_name(NULL, "ibm,opal"); 111 fw_features = of_get_child_by_name(np, "fw-features"); 112 of_node_put(np); 113 114 if (fw_features) { 115 init_fw_feat_flags(fw_features); 116 of_node_put(fw_features); 117 118 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2)) 119 type = L1D_FLUSH_MTTRIG; 120 121 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30)) 122 type = L1D_FLUSH_ORI; 123 } 124 125 /* 126 * If we are non-Power9 bare metal, we don't need to flush on kernel 127 * entry or after user access: they fix a P9 specific vulnerability. 128 */ 129 if (!pvr_version_is(PVR_POWER9)) { 130 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY); 131 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS); 132 } 133 134 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \ 135 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \ 136 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV)); 137 138 setup_rfi_flush(type, enable); 139 setup_count_cache_flush(); 140 141 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 142 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY); 143 setup_entry_flush(enable); 144 145 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && 146 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS); 147 setup_uaccess_flush(enable); 148 149 setup_stf_barrier(); 150 } 151 152 static void __init pnv_check_guarded_cores(void) 153 { 154 struct device_node *dn; 155 int bad_count = 0; 156 157 for_each_node_by_type(dn, "cpu") { 158 if (of_property_match_string(dn, "status", "bad") >= 0) 159 bad_count++; 160 }; 161 162 if (bad_count) { 163 printk(" _ _______________\n"); 164 pr_cont(" | | / \\\n"); 165 pr_cont(" | | | WARNING! |\n"); 166 pr_cont(" | | | |\n"); 167 pr_cont(" | | | It looks like |\n"); 168 pr_cont(" |_| | you have %*d |\n", 3, bad_count); 169 pr_cont(" _ | guarded cores |\n"); 170 pr_cont(" (_) \\_______________/\n"); 171 } 172 } 173 174 static void __init pnv_setup_arch(void) 175 { 176 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); 177 178 pnv_setup_security_mitigations(); 179 180 /* Initialize SMP */ 181 pnv_smp_init(); 182 183 /* Setup PCI */ 184 pnv_pci_init(); 185 186 /* Setup RTC and NVRAM callbacks */ 187 if (firmware_has_feature(FW_FEATURE_OPAL)) 188 opal_nvram_init(); 189 190 /* Enable NAP mode */ 191 powersave_nap = 1; 192 193 pnv_check_guarded_cores(); 194 195 /* XXX PMCS */ 196 } 197 198 static void __init pnv_init(void) 199 { 200 /* 201 * Initialize the LPC bus now so that legacy serial 202 * ports can be found on it 203 */ 204 opal_lpc_init(); 205 206 #ifdef CONFIG_HVC_OPAL 207 if (firmware_has_feature(FW_FEATURE_OPAL)) 208 hvc_opal_init_early(); 209 else 210 #endif 211 add_preferred_console("hvc", 0, NULL); 212 213 if (!radix_enabled()) { 214 int i; 215 216 /* Allocate per cpu area to save old slb contents during MCE */ 217 for_each_possible_cpu(i) 218 paca_ptrs[i]->mce_faulty_slbs = memblock_alloc_node(mmu_slb_size, __alignof__(*paca_ptrs[i]->mce_faulty_slbs), cpu_to_node(i)); 219 } 220 } 221 222 static void __init pnv_init_IRQ(void) 223 { 224 /* Try using a XIVE if available, otherwise use a XICS */ 225 if (!xive_native_init()) 226 xics_init(); 227 228 WARN_ON(!ppc_md.get_irq); 229 } 230 231 static void pnv_show_cpuinfo(struct seq_file *m) 232 { 233 struct device_node *root; 234 const char *model = ""; 235 236 root = of_find_node_by_path("/"); 237 if (root) 238 model = of_get_property(root, "model", NULL); 239 seq_printf(m, "machine\t\t: PowerNV %s\n", model); 240 if (firmware_has_feature(FW_FEATURE_OPAL)) 241 seq_printf(m, "firmware\t: OPAL\n"); 242 else 243 seq_printf(m, "firmware\t: BML\n"); 244 of_node_put(root); 245 if (radix_enabled()) 246 seq_printf(m, "MMU\t\t: Radix\n"); 247 else 248 seq_printf(m, "MMU\t\t: Hash\n"); 249 } 250 251 static void pnv_prepare_going_down(void) 252 { 253 /* 254 * Disable all notifiers from OPAL, we can't 255 * service interrupts anymore anyway 256 */ 257 opal_event_shutdown(); 258 259 /* Print flash update message if one is scheduled. */ 260 opal_flash_update_print_message(); 261 262 smp_send_stop(); 263 264 hard_irq_disable(); 265 } 266 267 static void __noreturn pnv_restart(char *cmd) 268 { 269 long rc; 270 271 pnv_prepare_going_down(); 272 273 do { 274 if (!cmd || !strlen(cmd)) 275 rc = opal_cec_reboot(); 276 else if (strcmp(cmd, "full") == 0) 277 rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL); 278 else if (strcmp(cmd, "mpipl") == 0) 279 rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL); 280 else if (strcmp(cmd, "error") == 0) 281 rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL); 282 else if (strcmp(cmd, "fast") == 0) 283 rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL); 284 else 285 rc = OPAL_UNSUPPORTED; 286 287 if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 288 /* Opal is busy wait for some time and retry */ 289 opal_poll_events(NULL); 290 mdelay(10); 291 292 } else if (cmd && rc) { 293 /* Unknown error while issuing reboot */ 294 if (rc == OPAL_UNSUPPORTED) 295 pr_err("Unsupported '%s' reboot.\n", cmd); 296 else 297 pr_err("Unable to issue '%s' reboot. Err=%ld\n", 298 cmd, rc); 299 pr_info("Forcing a cec-reboot\n"); 300 cmd = NULL; 301 rc = OPAL_BUSY; 302 303 } else if (rc != OPAL_SUCCESS) { 304 /* Unknown error while issuing cec-reboot */ 305 pr_err("Unable to reboot. Err=%ld\n", rc); 306 } 307 308 } while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT); 309 310 for (;;) 311 opal_poll_events(NULL); 312 } 313 314 static void __noreturn pnv_power_off(void) 315 { 316 long rc = OPAL_BUSY; 317 318 pnv_prepare_going_down(); 319 320 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 321 rc = opal_cec_power_down(0); 322 if (rc == OPAL_BUSY_EVENT) 323 opal_poll_events(NULL); 324 else 325 mdelay(10); 326 } 327 for (;;) 328 opal_poll_events(NULL); 329 } 330 331 static void __noreturn pnv_halt(void) 332 { 333 pnv_power_off(); 334 } 335 336 static void pnv_progress(char *s, unsigned short hex) 337 { 338 } 339 340 static void pnv_shutdown(void) 341 { 342 /* Let the PCI code clear up IODA tables */ 343 pnv_pci_shutdown(); 344 345 /* 346 * Stop OPAL activity: Unregister all OPAL interrupts so they 347 * don't fire up while we kexec and make sure all potentially 348 * DMA'ing ops are complete (such as dump retrieval). 349 */ 350 opal_shutdown(); 351 } 352 353 #ifdef CONFIG_KEXEC_CORE 354 static void pnv_kexec_wait_secondaries_down(void) 355 { 356 int my_cpu, i, notified = -1; 357 358 my_cpu = get_cpu(); 359 360 for_each_online_cpu(i) { 361 uint8_t status; 362 int64_t rc, timeout = 1000; 363 364 if (i == my_cpu) 365 continue; 366 367 for (;;) { 368 rc = opal_query_cpu_status(get_hard_smp_processor_id(i), 369 &status); 370 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED) 371 break; 372 barrier(); 373 if (i != notified) { 374 printk(KERN_INFO "kexec: waiting for cpu %d " 375 "(physical %d) to enter OPAL\n", 376 i, paca_ptrs[i]->hw_cpu_id); 377 notified = i; 378 } 379 380 /* 381 * On crash secondaries might be unreachable or hung, 382 * so timeout if we've waited too long 383 * */ 384 mdelay(1); 385 if (timeout-- == 0) { 386 printk(KERN_ERR "kexec: timed out waiting for " 387 "cpu %d (physical %d) to enter OPAL\n", 388 i, paca_ptrs[i]->hw_cpu_id); 389 break; 390 } 391 } 392 } 393 } 394 395 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) 396 { 397 u64 reinit_flags; 398 399 if (xive_enabled()) 400 xive_teardown_cpu(); 401 else 402 xics_kexec_teardown_cpu(secondary); 403 404 /* On OPAL, we return all CPUs to firmware */ 405 if (!firmware_has_feature(FW_FEATURE_OPAL)) 406 return; 407 408 if (secondary) { 409 /* Return secondary CPUs to firmware on OPAL v3 */ 410 mb(); 411 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE; 412 mb(); 413 414 /* Return the CPU to OPAL */ 415 opal_return_cpu(); 416 } else { 417 /* Primary waits for the secondaries to have reached OPAL */ 418 pnv_kexec_wait_secondaries_down(); 419 420 /* Switch XIVE back to emulation mode */ 421 if (xive_enabled()) 422 xive_shutdown(); 423 424 /* 425 * We might be running as little-endian - now that interrupts 426 * are disabled, reset the HILE bit to big-endian so we don't 427 * take interrupts in the wrong endian later 428 * 429 * We reinit to enable both radix and hash on P9 to ensure 430 * the mode used by the next kernel is always supported. 431 */ 432 reinit_flags = OPAL_REINIT_CPUS_HILE_BE; 433 if (cpu_has_feature(CPU_FTR_ARCH_300)) 434 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX | 435 OPAL_REINIT_CPUS_MMU_HASH; 436 opal_reinit_cpus(reinit_flags); 437 } 438 } 439 #endif /* CONFIG_KEXEC_CORE */ 440 441 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 442 static unsigned long pnv_memory_block_size(void) 443 { 444 /* 445 * We map the kernel linear region with 1GB large pages on radix. For 446 * memory hot unplug to work our memory block size must be at least 447 * this size. 448 */ 449 if (radix_enabled()) 450 return radix_mem_block_size; 451 else 452 return 256UL * 1024 * 1024; 453 } 454 #endif 455 456 static void __init pnv_setup_machdep_opal(void) 457 { 458 ppc_md.get_boot_time = opal_get_boot_time; 459 ppc_md.restart = pnv_restart; 460 pm_power_off = pnv_power_off; 461 ppc_md.halt = pnv_halt; 462 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */ 463 ppc_md.machine_check_exception = opal_machine_check; 464 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery; 465 if (opal_check_token(OPAL_HANDLE_HMI2)) 466 ppc_md.hmi_exception_early = opal_hmi_exception_early2; 467 else 468 ppc_md.hmi_exception_early = opal_hmi_exception_early; 469 ppc_md.handle_hmi_exception = opal_handle_hmi_exception; 470 } 471 472 static int __init pnv_probe(void) 473 { 474 if (!of_machine_is_compatible("ibm,powernv")) 475 return 0; 476 477 if (firmware_has_feature(FW_FEATURE_OPAL)) 478 pnv_setup_machdep_opal(); 479 480 pr_debug("PowerNV detected !\n"); 481 482 pnv_init(); 483 484 return 1; 485 } 486 487 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 488 void __init pnv_tm_init(void) 489 { 490 if (!firmware_has_feature(FW_FEATURE_OPAL) || 491 !pvr_version_is(PVR_POWER9) || 492 early_cpu_has_feature(CPU_FTR_TM)) 493 return; 494 495 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS) 496 return; 497 498 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n"); 499 cur_cpu_spec->cpu_features |= CPU_FTR_TM; 500 /* Make sure "normal" HTM is off (it should be) */ 501 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM; 502 /* Turn on no suspend mode, and HTM no SC */ 503 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \ 504 PPC_FEATURE2_HTM_NOSC; 505 tm_suspend_disabled = true; 506 } 507 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 508 509 /* 510 * Returns the cpu frequency for 'cpu' in Hz. This is used by 511 * /proc/cpuinfo 512 */ 513 static unsigned long pnv_get_proc_freq(unsigned int cpu) 514 { 515 unsigned long ret_freq; 516 517 ret_freq = cpufreq_get(cpu) * 1000ul; 518 519 /* 520 * If the backend cpufreq driver does not exist, 521 * then fallback to old way of reporting the clockrate. 522 */ 523 if (!ret_freq) 524 ret_freq = ppc_proc_freq; 525 return ret_freq; 526 } 527 528 static long pnv_machine_check_early(struct pt_regs *regs) 529 { 530 long handled = 0; 531 532 if (cur_cpu_spec && cur_cpu_spec->machine_check_early) 533 handled = cur_cpu_spec->machine_check_early(regs); 534 535 return handled; 536 } 537 538 define_machine(powernv) { 539 .name = "PowerNV", 540 .probe = pnv_probe, 541 .setup_arch = pnv_setup_arch, 542 .init_IRQ = pnv_init_IRQ, 543 .show_cpuinfo = pnv_show_cpuinfo, 544 .get_proc_freq = pnv_get_proc_freq, 545 .progress = pnv_progress, 546 .machine_shutdown = pnv_shutdown, 547 .power_save = NULL, 548 .calibrate_decr = generic_calibrate_decr, 549 .machine_check_early = pnv_machine_check_early, 550 #ifdef CONFIG_KEXEC_CORE 551 .kexec_cpu_down = pnv_kexec_cpu_down, 552 #endif 553 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE 554 .memory_block_size = pnv_memory_block_size, 555 #endif 556 }; 557