1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 struct pci_dn; 5 6 enum pnv_phb_type { 7 PNV_PHB_P5IOC2 = 0, 8 PNV_PHB_IODA1 = 1, 9 PNV_PHB_IODA2 = 2, 10 }; 11 12 /* Precise PHB model for error management */ 13 enum pnv_phb_model { 14 PNV_PHB_MODEL_UNKNOWN, 15 PNV_PHB_MODEL_P5IOC2, 16 PNV_PHB_MODEL_P7IOC, 17 PNV_PHB_MODEL_PHB3, 18 }; 19 20 #define PNV_PCI_DIAG_BUF_SIZE 4096 21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24 25 /* Data associated with a PE, including IOMMU tracking etc.. */ 26 struct pnv_phb; 27 struct pnv_ioda_pe { 28 unsigned long flags; 29 struct pnv_phb *phb; 30 31 /* A PE can be associated with a single device or an 32 * entire bus (& children). In the former case, pdev 33 * is populated, in the later case, pbus is. 34 */ 35 struct pci_dev *pdev; 36 struct pci_bus *pbus; 37 38 /* Effective RID (device RID for a device PE and base bus 39 * RID with devfn 0 for a bus PE) 40 */ 41 unsigned int rid; 42 43 /* PE number */ 44 unsigned int pe_number; 45 46 /* "Weight" assigned to the PE for the sake of DMA resource 47 * allocations 48 */ 49 unsigned int dma_weight; 50 51 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 52 int tce32_seg; 53 int tce32_segcount; 54 struct iommu_table tce32_table; 55 56 /* XXX TODO: Add support for additional 64-bit iommus */ 57 58 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 59 * and -1 if not supported. (It's actually identical to the 60 * PE number) 61 */ 62 int mve_number; 63 64 /* Link in list of PE#s */ 65 struct list_head dma_link; 66 struct list_head list; 67 }; 68 69 /* IOC dependent EEH operations */ 70 #ifdef CONFIG_EEH 71 struct pnv_eeh_ops { 72 int (*post_init)(struct pci_controller *hose); 73 int (*set_option)(struct eeh_pe *pe, int option); 74 int (*get_state)(struct eeh_pe *pe); 75 int (*reset)(struct eeh_pe *pe, int option); 76 int (*get_log)(struct eeh_pe *pe, int severity, 77 char *drv_log, unsigned long len); 78 int (*configure_bridge)(struct eeh_pe *pe); 79 int (*next_error)(struct eeh_pe **pe); 80 }; 81 82 #define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */ 83 #define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */ 84 85 #endif /* CONFIG_EEH */ 86 87 struct pnv_phb { 88 struct pci_controller *hose; 89 enum pnv_phb_type type; 90 enum pnv_phb_model model; 91 u64 hub_id; 92 u64 opal_id; 93 void __iomem *regs; 94 int initialized; 95 spinlock_t lock; 96 97 #ifdef CONFIG_EEH 98 struct pnv_eeh_ops *eeh_ops; 99 int eeh_state; 100 #endif 101 102 #ifdef CONFIG_DEBUG_FS 103 struct dentry *dbgfs; 104 #endif 105 106 #ifdef CONFIG_PCI_MSI 107 unsigned int msi_base; 108 unsigned int msi32_support; 109 struct msi_bitmap msi_bmp; 110 #endif 111 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 112 unsigned int hwirq, unsigned int virq, 113 unsigned int is_64, struct msi_msg *msg); 114 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 115 void (*fixup_phb)(struct pci_controller *hose); 116 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 117 void (*shutdown)(struct pnv_phb *phb); 118 119 union { 120 struct { 121 struct iommu_table iommu_table; 122 } p5ioc2; 123 124 struct { 125 /* Global bridge info */ 126 unsigned int total_pe; 127 unsigned int m32_size; 128 unsigned int m32_segsize; 129 unsigned int m32_pci_base; 130 unsigned int io_size; 131 unsigned int io_segsize; 132 unsigned int io_pci_base; 133 134 /* PE allocation bitmap */ 135 unsigned long *pe_alloc; 136 137 /* M32 & IO segment maps */ 138 unsigned int *m32_segmap; 139 unsigned int *io_segmap; 140 struct pnv_ioda_pe *pe_array; 141 142 /* IRQ chip */ 143 int irq_chip_init; 144 struct irq_chip irq_chip; 145 146 /* Sorted list of used PE's based 147 * on the sequence of creation 148 */ 149 struct list_head pe_list; 150 151 /* Reverse map of PEs, will have to extend if 152 * we are to support more than 256 PEs, indexed 153 * bus { bus, devfn } 154 */ 155 unsigned char pe_rmap[0x10000]; 156 157 /* 32-bit TCE tables allocation */ 158 unsigned long tce32_count; 159 160 /* Total "weight" for the sake of DMA resources 161 * allocation 162 */ 163 unsigned int dma_weight; 164 unsigned int dma_pe_count; 165 166 /* Sorted list of used PE's, sorted at 167 * boot for resource allocation purposes 168 */ 169 struct list_head pe_dma_list; 170 } ioda; 171 }; 172 173 /* PHB status structure */ 174 union { 175 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 176 struct OpalIoP7IOCPhbErrorData p7ioc; 177 } diag; 178 }; 179 180 extern struct pci_ops pnv_pci_ops; 181 #ifdef CONFIG_EEH 182 extern struct pnv_eeh_ops ioda_eeh_ops; 183 #endif 184 185 int pnv_pci_cfg_read(struct device_node *dn, 186 int where, int size, u32 *val); 187 int pnv_pci_cfg_write(struct device_node *dn, 188 int where, int size, u32 val); 189 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 190 void *tce_mem, u64 tce_size, 191 u64 dma_offset); 192 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 193 extern void pnv_pci_init_ioda_hub(struct device_node *np); 194 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 195 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 196 u64 *startp, u64 *endp); 197 198 #endif /* __POWERNV_PCI_H */ 199