1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __POWERNV_PCI_H 3 #define __POWERNV_PCI_H 4 5 #include <linux/iommu.h> 6 #include <asm/iommu.h> 7 #include <asm/msi_bitmap.h> 8 9 struct pci_dn; 10 11 enum pnv_phb_type { 12 PNV_PHB_IODA1 = 0, 13 PNV_PHB_IODA2 = 1, 14 PNV_PHB_NPU_NVLINK = 2, 15 PNV_PHB_NPU_OCAPI = 3, 16 }; 17 18 /* Precise PHB model for error management */ 19 enum pnv_phb_model { 20 PNV_PHB_MODEL_UNKNOWN, 21 PNV_PHB_MODEL_P7IOC, 22 PNV_PHB_MODEL_PHB3, 23 PNV_PHB_MODEL_NPU, 24 PNV_PHB_MODEL_NPU2, 25 }; 26 27 #define PNV_PCI_DIAG_BUF_SIZE 8192 28 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 29 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 30 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 31 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 32 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 33 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 34 35 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 36 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 37 38 /* Data associated with a PE, including IOMMU tracking etc.. */ 39 struct pnv_phb; 40 struct pnv_ioda_pe { 41 unsigned long flags; 42 struct pnv_phb *phb; 43 int device_count; 44 45 /* A PE can be associated with a single device or an 46 * entire bus (& children). In the former case, pdev 47 * is populated, in the later case, pbus is. 48 */ 49 #ifdef CONFIG_PCI_IOV 50 struct pci_dev *parent_dev; 51 #endif 52 struct pci_dev *pdev; 53 struct pci_bus *pbus; 54 55 /* Effective RID (device RID for a device PE and base bus 56 * RID with devfn 0 for a bus PE) 57 */ 58 unsigned int rid; 59 60 /* PE number */ 61 unsigned int pe_number; 62 63 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 64 struct iommu_table_group table_group; 65 struct npu_comp *npucomp; 66 67 /* 64-bit TCE bypass region */ 68 bool tce_bypass_enabled; 69 uint64_t tce_bypass_base; 70 71 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 72 * and -1 if not supported. (It's actually identical to the 73 * PE number) 74 */ 75 int mve_number; 76 77 /* PEs in compound case */ 78 struct pnv_ioda_pe *master; 79 struct list_head slaves; 80 81 /* PCI peer-to-peer*/ 82 int p2p_initiator_count; 83 84 /* Link in list of PE#s */ 85 struct list_head list; 86 }; 87 88 #define PNV_PHB_FLAG_EEH (1 << 0) 89 90 struct pnv_phb { 91 struct pci_controller *hose; 92 enum pnv_phb_type type; 93 enum pnv_phb_model model; 94 u64 hub_id; 95 u64 opal_id; 96 int flags; 97 void __iomem *regs; 98 u64 regs_phys; 99 int initialized; 100 spinlock_t lock; 101 102 #ifdef CONFIG_DEBUG_FS 103 int has_dbgfs; 104 struct dentry *dbgfs; 105 #endif 106 107 unsigned int msi_base; 108 unsigned int msi32_support; 109 struct msi_bitmap msi_bmp; 110 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 111 unsigned int hwirq, unsigned int virq, 112 unsigned int is_64, struct msi_msg *msg); 113 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 114 int (*init_m64)(struct pnv_phb *phb); 115 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 116 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 117 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 118 119 struct { 120 /* Global bridge info */ 121 unsigned int total_pe_num; 122 unsigned int reserved_pe_idx; 123 unsigned int root_pe_idx; 124 bool root_pe_populated; 125 126 /* 32-bit MMIO window */ 127 unsigned int m32_size; 128 unsigned int m32_segsize; 129 unsigned int m32_pci_base; 130 131 /* 64-bit MMIO window */ 132 unsigned int m64_bar_idx; 133 unsigned long m64_size; 134 unsigned long m64_segsize; 135 unsigned long m64_base; 136 unsigned long m64_bar_alloc; 137 138 /* IO ports */ 139 unsigned int io_size; 140 unsigned int io_segsize; 141 unsigned int io_pci_base; 142 143 /* PE allocation */ 144 struct mutex pe_alloc_mutex; 145 unsigned long *pe_alloc; 146 struct pnv_ioda_pe *pe_array; 147 148 /* M32 & IO segment maps */ 149 unsigned int *m64_segmap; 150 unsigned int *m32_segmap; 151 unsigned int *io_segmap; 152 153 /* DMA32 segment maps - IODA1 only */ 154 unsigned int dma32_count; 155 unsigned int *dma32_segmap; 156 157 /* IRQ chip */ 158 int irq_chip_init; 159 struct irq_chip irq_chip; 160 161 /* Sorted list of used PE's based 162 * on the sequence of creation 163 */ 164 struct list_head pe_list; 165 struct mutex pe_list_mutex; 166 167 /* Reverse map of PEs, indexed by {bus, devfn} */ 168 unsigned int pe_rmap[0x10000]; 169 } ioda; 170 171 /* PHB and hub diagnostics */ 172 unsigned int diag_data_size; 173 u8 *diag_data; 174 175 int p2p_target_count; 176 }; 177 178 extern struct pci_ops pnv_pci_ops; 179 180 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 181 unsigned char *log_buff); 182 int pnv_pci_cfg_read(struct pci_dn *pdn, 183 int where, int size, u32 *val); 184 int pnv_pci_cfg_write(struct pci_dn *pdn, 185 int where, int size, u32 val); 186 extern struct iommu_table *pnv_pci_table_alloc(int nid); 187 188 extern void pnv_pci_init_ioda_hub(struct device_node *np); 189 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 190 extern void pnv_pci_init_npu_phb(struct device_node *np); 191 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 192 extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr); 193 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 194 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 195 196 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 197 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 198 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 199 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 200 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 201 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 202 extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 203 extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 204 __u64 window_size, __u32 levels); 205 extern int pnv_eeh_post_init(void); 206 207 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 208 const char *fmt, ...); 209 #define pe_err(pe, fmt, ...) \ 210 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 211 #define pe_warn(pe, fmt, ...) \ 212 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 213 #define pe_info(pe, fmt, ...) \ 214 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 215 216 /* Nvlink functions */ 217 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 218 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 219 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 220 extern struct iommu_table_group *pnv_try_setup_npu_table_group( 221 struct pnv_ioda_pe *pe); 222 extern struct iommu_table_group *pnv_npu_compound_attach( 223 struct pnv_ioda_pe *pe); 224 225 /* pci-ioda-tce.c */ 226 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 227 #define POWERNV_IOMMU_MAX_LEVELS 5 228 229 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 230 unsigned long uaddr, enum dma_data_direction direction, 231 unsigned long attrs); 232 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 233 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 234 unsigned long *hpa, enum dma_data_direction *direction, 235 bool alloc); 236 extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 237 bool alloc); 238 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 239 240 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 241 __u32 page_shift, __u64 window_size, __u32 levels, 242 bool alloc_userspace_copy, struct iommu_table *tbl); 243 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 244 245 extern long pnv_pci_link_table_and_group(int node, int num, 246 struct iommu_table *tbl, 247 struct iommu_table_group *table_group); 248 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 249 struct iommu_table_group *table_group); 250 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 251 void *tce_mem, u64 tce_size, 252 u64 dma_offset, unsigned int page_shift); 253 254 #endif /* __POWERNV_PCI_H */ 255