1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 struct pci_dn; 5 6 enum pnv_phb_type { 7 PNV_PHB_P5IOC2, 8 PNV_PHB_IODA1, 9 PNV_PHB_IODA2, 10 }; 11 12 /* Precise PHB model for error management */ 13 enum pnv_phb_model { 14 PNV_PHB_MODEL_UNKNOWN, 15 PNV_PHB_MODEL_P5IOC2, 16 PNV_PHB_MODEL_P7IOC, 17 }; 18 19 #define PNV_PCI_DIAG_BUF_SIZE 4096 20 21 /* Data associated with a PE, including IOMMU tracking etc.. */ 22 struct pnv_ioda_pe { 23 /* A PE can be associated with a single device or an 24 * entire bus (& children). In the former case, pdev 25 * is populated, in the later case, pbus is. 26 */ 27 struct pci_dev *pdev; 28 struct pci_bus *pbus; 29 30 /* Effective RID (device RID for a device PE and base bus 31 * RID with devfn 0 for a bus PE) 32 */ 33 unsigned int rid; 34 35 /* PE number */ 36 unsigned int pe_number; 37 38 /* "Weight" assigned to the PE for the sake of DMA resource 39 * allocations 40 */ 41 unsigned int dma_weight; 42 43 /* This is a PCI-E -> PCI-X bridge, this points to the 44 * corresponding bus PE 45 */ 46 struct pnv_ioda_pe *bus_pe; 47 48 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 49 int tce32_seg; 50 int tce32_segcount; 51 struct iommu_table tce32_table; 52 53 /* XXX TODO: Add support for additional 64-bit iommus */ 54 55 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 56 * and -1 if not supported. (It's actually identical to the 57 * PE number) 58 */ 59 int mve_number; 60 61 /* Link in list of PE#s */ 62 struct list_head link; 63 }; 64 65 struct pnv_phb { 66 struct pci_controller *hose; 67 enum pnv_phb_type type; 68 enum pnv_phb_model model; 69 u64 opal_id; 70 void __iomem *regs; 71 spinlock_t lock; 72 73 #ifdef CONFIG_PCI_MSI 74 unsigned long *msi_map; 75 unsigned int msi_base; 76 unsigned int msi_count; 77 unsigned int msi_next; 78 unsigned int msi32_support; 79 #endif 80 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 81 unsigned int hwirq, unsigned int is_64, 82 struct msi_msg *msg); 83 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 84 void (*fixup_phb)(struct pci_controller *hose); 85 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 86 87 union { 88 struct { 89 struct iommu_table iommu_table; 90 } p5ioc2; 91 92 struct { 93 /* Global bridge info */ 94 unsigned int total_pe; 95 unsigned int m32_size; 96 unsigned int m32_segsize; 97 unsigned int m32_pci_base; 98 unsigned int io_size; 99 unsigned int io_segsize; 100 unsigned int io_pci_base; 101 102 /* PE allocation bitmap */ 103 unsigned long *pe_alloc; 104 105 /* M32 & IO segment maps */ 106 unsigned int *m32_segmap; 107 unsigned int *io_segmap; 108 struct pnv_ioda_pe *pe_array; 109 110 /* Reverse map of PEs, will have to extend if 111 * we are to support more than 256 PEs, indexed 112 * bus { bus, devfn } 113 */ 114 unsigned char pe_rmap[0x10000]; 115 116 /* 32-bit TCE tables allocation */ 117 unsigned long tce32_count; 118 119 /* Total "weight" for the sake of DMA resources 120 * allocation 121 */ 122 unsigned int dma_weight; 123 unsigned int dma_pe_count; 124 125 /* Sorted list of used PE's, sorted at 126 * boot for resource allocation purposes 127 */ 128 struct list_head pe_list; 129 } ioda; 130 }; 131 132 /* PHB status structure */ 133 union { 134 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 135 struct OpalIoP7IOCPhbErrorData p7ioc; 136 } diag; 137 }; 138 139 extern struct pci_ops pnv_pci_ops; 140 141 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 142 void *tce_mem, u64 tce_size, 143 u64 dma_offset); 144 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 145 extern void pnv_pci_init_ioda_hub(struct device_node *np); 146 147 148 #endif /* __POWERNV_PCI_H */ 149