1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __POWERNV_PCI_H 3 #define __POWERNV_PCI_H 4 5 #include <linux/iommu.h> 6 #include <asm/iommu.h> 7 #include <asm/msi_bitmap.h> 8 9 struct pci_dn; 10 11 /* Maximum possible number of ATSD MMIO registers per NPU */ 12 #define NV_NMMU_ATSD_REGS 8 13 14 enum pnv_phb_type { 15 PNV_PHB_IODA1 = 0, 16 PNV_PHB_IODA2 = 1, 17 PNV_PHB_NPU = 2, 18 }; 19 20 /* Precise PHB model for error management */ 21 enum pnv_phb_model { 22 PNV_PHB_MODEL_UNKNOWN, 23 PNV_PHB_MODEL_P7IOC, 24 PNV_PHB_MODEL_PHB3, 25 PNV_PHB_MODEL_NPU, 26 PNV_PHB_MODEL_NPU2, 27 }; 28 29 #define PNV_PCI_DIAG_BUF_SIZE 8192 30 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 31 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 32 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 33 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 34 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 35 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 36 37 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 38 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 39 40 /* Data associated with a PE, including IOMMU tracking etc.. */ 41 struct pnv_phb; 42 struct pnv_ioda_pe { 43 unsigned long flags; 44 struct pnv_phb *phb; 45 int device_count; 46 47 /* A PE can be associated with a single device or an 48 * entire bus (& children). In the former case, pdev 49 * is populated, in the later case, pbus is. 50 */ 51 #ifdef CONFIG_PCI_IOV 52 struct pci_dev *parent_dev; 53 #endif 54 struct pci_dev *pdev; 55 struct pci_bus *pbus; 56 57 /* Effective RID (device RID for a device PE and base bus 58 * RID with devfn 0 for a bus PE) 59 */ 60 unsigned int rid; 61 62 /* PE number */ 63 unsigned int pe_number; 64 65 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 66 struct iommu_table_group table_group; 67 68 /* 64-bit TCE bypass region */ 69 bool tce_bypass_enabled; 70 uint64_t tce_bypass_base; 71 72 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 73 * and -1 if not supported. (It's actually identical to the 74 * PE number) 75 */ 76 int mve_number; 77 78 /* PEs in compound case */ 79 struct pnv_ioda_pe *master; 80 struct list_head slaves; 81 82 /* PCI peer-to-peer*/ 83 int p2p_initiator_count; 84 85 /* Link in list of PE#s */ 86 struct list_head list; 87 }; 88 89 #define PNV_PHB_FLAG_EEH (1 << 0) 90 #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */ 91 92 struct pnv_phb { 93 struct pci_controller *hose; 94 enum pnv_phb_type type; 95 enum pnv_phb_model model; 96 u64 hub_id; 97 u64 opal_id; 98 int flags; 99 void __iomem *regs; 100 u64 regs_phys; 101 int initialized; 102 spinlock_t lock; 103 104 #ifdef CONFIG_DEBUG_FS 105 int has_dbgfs; 106 struct dentry *dbgfs; 107 #endif 108 109 #ifdef CONFIG_PCI_MSI 110 unsigned int msi_base; 111 unsigned int msi32_support; 112 struct msi_bitmap msi_bmp; 113 #endif 114 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 115 unsigned int hwirq, unsigned int virq, 116 unsigned int is_64, struct msi_msg *msg); 117 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 118 void (*fixup_phb)(struct pci_controller *hose); 119 int (*init_m64)(struct pnv_phb *phb); 120 void (*reserve_m64_pe)(struct pci_bus *bus, 121 unsigned long *pe_bitmap, bool all); 122 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all); 123 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 124 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 125 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 126 127 struct { 128 /* Global bridge info */ 129 unsigned int total_pe_num; 130 unsigned int reserved_pe_idx; 131 unsigned int root_pe_idx; 132 bool root_pe_populated; 133 134 /* 32-bit MMIO window */ 135 unsigned int m32_size; 136 unsigned int m32_segsize; 137 unsigned int m32_pci_base; 138 139 /* 64-bit MMIO window */ 140 unsigned int m64_bar_idx; 141 unsigned long m64_size; 142 unsigned long m64_segsize; 143 unsigned long m64_base; 144 unsigned long m64_bar_alloc; 145 146 /* IO ports */ 147 unsigned int io_size; 148 unsigned int io_segsize; 149 unsigned int io_pci_base; 150 151 /* PE allocation */ 152 struct mutex pe_alloc_mutex; 153 unsigned long *pe_alloc; 154 struct pnv_ioda_pe *pe_array; 155 156 /* M32 & IO segment maps */ 157 unsigned int *m64_segmap; 158 unsigned int *m32_segmap; 159 unsigned int *io_segmap; 160 161 /* DMA32 segment maps - IODA1 only */ 162 unsigned int dma32_count; 163 unsigned int *dma32_segmap; 164 165 /* IRQ chip */ 166 int irq_chip_init; 167 struct irq_chip irq_chip; 168 169 /* Sorted list of used PE's based 170 * on the sequence of creation 171 */ 172 struct list_head pe_list; 173 struct mutex pe_list_mutex; 174 175 /* Reverse map of PEs, indexed by {bus, devfn} */ 176 unsigned int pe_rmap[0x10000]; 177 } ioda; 178 179 /* PHB and hub diagnostics */ 180 unsigned int diag_data_size; 181 u8 *diag_data; 182 183 /* Nvlink2 data */ 184 struct npu { 185 int index; 186 __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS]; 187 unsigned int mmio_atsd_count; 188 189 /* Bitmask for MMIO register usage */ 190 unsigned long mmio_atsd_usage; 191 192 /* Do we need to explicitly flush the nest mmu? */ 193 bool nmmu_flush; 194 } npu; 195 196 #ifdef CONFIG_CXL_BASE 197 struct cxl_afu *cxl_afu; 198 #endif 199 int p2p_target_count; 200 }; 201 202 extern struct pci_ops pnv_pci_ops; 203 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 204 unsigned long uaddr, enum dma_data_direction direction, 205 unsigned long attrs); 206 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 207 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 208 unsigned long *hpa, enum dma_data_direction *direction); 209 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 210 211 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 212 unsigned char *log_buff); 213 int pnv_pci_cfg_read(struct pci_dn *pdn, 214 int where, int size, u32 *val); 215 int pnv_pci_cfg_write(struct pci_dn *pdn, 216 int where, int size, u32 val); 217 extern struct iommu_table *pnv_pci_table_alloc(int nid); 218 219 extern long pnv_pci_link_table_and_group(int node, int num, 220 struct iommu_table *tbl, 221 struct iommu_table_group *table_group); 222 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 223 struct iommu_table_group *table_group); 224 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 225 void *tce_mem, u64 tce_size, 226 u64 dma_offset, unsigned page_shift); 227 extern void pnv_pci_init_ioda_hub(struct device_node *np); 228 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 229 extern void pnv_pci_init_npu_phb(struct device_node *np); 230 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 231 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 232 233 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 234 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 235 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 236 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 237 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 238 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 239 extern bool pnv_pci_enable_device_hook(struct pci_dev *dev); 240 extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 241 extern int pnv_eeh_post_init(void); 242 243 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 244 const char *fmt, ...); 245 #define pe_err(pe, fmt, ...) \ 246 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 247 #define pe_warn(pe, fmt, ...) \ 248 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 249 #define pe_info(pe, fmt, ...) \ 250 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 251 252 /* Nvlink functions */ 253 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 254 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 255 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 256 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, 257 struct iommu_table *tbl); 258 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num); 259 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe); 260 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe); 261 extern int pnv_npu2_init(struct pnv_phb *phb); 262 263 /* cxl functions */ 264 extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev); 265 extern void pnv_cxl_disable_device(struct pci_dev *dev); 266 extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 267 extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev); 268 269 270 /* phb ops (cxl switches these when enabling the kernel api on the phb) */ 271 extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops; 272 273 #endif /* __POWERNV_PCI_H */ 274