1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __POWERNV_PCI_H 3 #define __POWERNV_PCI_H 4 5 #include <linux/compiler.h> /* for __printf */ 6 #include <linux/iommu.h> 7 #include <asm/iommu.h> 8 #include <asm/msi_bitmap.h> 9 10 struct pci_dn; 11 12 enum pnv_phb_type { 13 PNV_PHB_IODA1, 14 PNV_PHB_IODA2, 15 PNV_PHB_NPU_OCAPI, 16 }; 17 18 /* Precise PHB model for error management */ 19 enum pnv_phb_model { 20 PNV_PHB_MODEL_UNKNOWN, 21 PNV_PHB_MODEL_P7IOC, 22 PNV_PHB_MODEL_PHB3, 23 }; 24 25 #define PNV_PCI_DIAG_BUF_SIZE 8192 26 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 27 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 28 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 29 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 30 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 31 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 32 33 /* 34 * A brief note on PNV_IODA_PE_BUS_ALL 35 * 36 * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses 37 * the Requester ID field of the PCIe request header to determine the device 38 * (and PE) that initiated a DMA. In legacy PCI individual memory read/write 39 * requests aren't tagged with the RID. To work around this the PCIe-to-PCI 40 * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side. 41 * 42 * PCIe-to-X bridges have a similar issue even though PCI-X requests also have 43 * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take 44 * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe 45 * side of the bridge. 46 * 47 * To work around these problems we use the BUS_ALL flag since every subordinate 48 * bus of the bridge should go into the same PE. 49 */ 50 51 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 52 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 53 54 /* Data associated with a PE, including IOMMU tracking etc.. */ 55 struct pnv_phb; 56 struct pnv_ioda_pe { 57 unsigned long flags; 58 struct pnv_phb *phb; 59 int device_count; 60 61 /* A PE can be associated with a single device or an 62 * entire bus (& children). In the former case, pdev 63 * is populated, in the later case, pbus is. 64 */ 65 #ifdef CONFIG_PCI_IOV 66 struct pci_dev *parent_dev; 67 #endif 68 struct pci_dev *pdev; 69 struct pci_bus *pbus; 70 71 /* Effective RID (device RID for a device PE and base bus 72 * RID with devfn 0 for a bus PE) 73 */ 74 unsigned int rid; 75 76 /* PE number */ 77 unsigned int pe_number; 78 79 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 80 struct iommu_table_group table_group; 81 82 /* 64-bit TCE bypass region */ 83 bool tce_bypass_enabled; 84 uint64_t tce_bypass_base; 85 86 /* 87 * Used to track whether we've done DMA setup for this PE or not. We 88 * want to defer allocating TCE tables, etc until we've added a 89 * non-bridge device to the PE. 90 */ 91 bool dma_setup_done; 92 93 /* MSIs. MVE index is identical for 32 and 64 bit MSI 94 * and -1 if not supported. (It's actually identical to the 95 * PE number) 96 */ 97 int mve_number; 98 99 /* PEs in compound case */ 100 struct pnv_ioda_pe *master; 101 struct list_head slaves; 102 103 /* Link in list of PE#s */ 104 struct list_head list; 105 }; 106 107 #define PNV_PHB_FLAG_EEH (1 << 0) 108 109 struct pnv_phb { 110 struct pci_controller *hose; 111 enum pnv_phb_type type; 112 enum pnv_phb_model model; 113 u64 hub_id; 114 u64 opal_id; 115 int flags; 116 void __iomem *regs; 117 u64 regs_phys; 118 spinlock_t lock; 119 120 #ifdef CONFIG_DEBUG_FS 121 int has_dbgfs; 122 struct dentry *dbgfs; 123 #endif 124 125 unsigned int msi_base; 126 unsigned int msi32_support; 127 struct msi_bitmap msi_bmp; 128 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 129 unsigned int hwirq, unsigned int virq, 130 unsigned int is_64, struct msi_msg *msg); 131 int (*init_m64)(struct pnv_phb *phb); 132 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 133 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 134 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 135 136 struct { 137 /* Global bridge info */ 138 unsigned int total_pe_num; 139 unsigned int reserved_pe_idx; 140 unsigned int root_pe_idx; 141 142 /* 32-bit MMIO window */ 143 unsigned int m32_size; 144 unsigned int m32_segsize; 145 unsigned int m32_pci_base; 146 147 /* 64-bit MMIO window */ 148 unsigned int m64_bar_idx; 149 unsigned long m64_size; 150 unsigned long m64_segsize; 151 unsigned long m64_base; 152 #define MAX_M64_BARS 64 153 unsigned long m64_bar_alloc; 154 155 /* IO ports */ 156 unsigned int io_size; 157 unsigned int io_segsize; 158 unsigned int io_pci_base; 159 160 /* PE allocation */ 161 struct mutex pe_alloc_mutex; 162 unsigned long *pe_alloc; 163 struct pnv_ioda_pe *pe_array; 164 165 /* M32 & IO segment maps */ 166 unsigned int *m64_segmap; 167 unsigned int *m32_segmap; 168 unsigned int *io_segmap; 169 170 /* DMA32 segment maps - IODA1 only */ 171 unsigned int dma32_count; 172 unsigned int *dma32_segmap; 173 174 /* IRQ chip */ 175 int irq_chip_init; 176 struct irq_chip irq_chip; 177 178 /* Sorted list of used PE's based 179 * on the sequence of creation 180 */ 181 struct list_head pe_list; 182 struct mutex pe_list_mutex; 183 184 /* Reverse map of PEs, indexed by {bus, devfn} */ 185 unsigned int pe_rmap[0x10000]; 186 } ioda; 187 188 /* PHB and hub diagnostics */ 189 unsigned int diag_data_size; 190 u8 *diag_data; 191 }; 192 193 194 /* IODA PE management */ 195 196 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 197 { 198 /* 199 * WARNING: We cannot rely on the resource flags. The Linux PCI 200 * allocation code sometimes decides to put a 64-bit prefetchable 201 * BAR in the 32-bit window, so we have to compare the addresses. 202 * 203 * For simplicity we only test resource start. 204 */ 205 return (r->start >= phb->ioda.m64_base && 206 r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 207 } 208 209 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 210 { 211 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 212 213 return (resource_flags & flags) == flags; 214 } 215 216 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 217 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 218 219 void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 220 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe); 221 222 struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count); 223 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe); 224 225 #ifdef CONFIG_PCI_IOV 226 /* 227 * For SR-IOV we want to put each VF's MMIO resource in to a separate PE. 228 * This requires a bit of acrobatics with the MMIO -> PE configuration 229 * and this structure is used to keep track of it all. 230 */ 231 struct pnv_iov_data { 232 /* number of VFs enabled */ 233 u16 num_vfs; 234 235 /* pointer to the array of VF PEs. num_vfs long*/ 236 struct pnv_ioda_pe *vf_pe_arr; 237 238 /* Did we map the VF BAR with single-PE IODA BARs? */ 239 bool m64_single_mode[PCI_SRIOV_NUM_BARS]; 240 241 /* 242 * True if we're using any segmented windows. In that case we need 243 * shift the start of the IOV resource the segment corresponding to 244 * the allocated PE. 245 */ 246 bool need_shift; 247 248 /* 249 * Bit mask used to track which m64 windows are used to map the 250 * SR-IOV BARs for this device. 251 */ 252 DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS); 253 254 /* 255 * If we map the SR-IOV BARs with a segmented window then 256 * parts of that window will be "claimed" by other PEs. 257 * 258 * "holes" here is used to reserve the leading portion 259 * of the window that is used by other (non VF) PEs. 260 */ 261 struct resource holes[PCI_SRIOV_NUM_BARS]; 262 }; 263 264 static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev) 265 { 266 return pdev->dev.archdata.iov_data; 267 } 268 269 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev); 270 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno); 271 272 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 273 int pnv_pcibios_sriov_disable(struct pci_dev *pdev); 274 #endif /* CONFIG_PCI_IOV */ 275 276 extern struct pci_ops pnv_pci_ops; 277 278 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 279 unsigned char *log_buff); 280 int pnv_pci_cfg_read(struct pci_dn *pdn, 281 int where, int size, u32 *val); 282 int pnv_pci_cfg_write(struct pci_dn *pdn, 283 int where, int size, u32 val); 284 extern struct iommu_table *pnv_pci_table_alloc(int nid); 285 286 extern void pnv_pci_init_ioda_hub(struct device_node *np); 287 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 288 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 289 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 290 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 291 292 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 293 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 294 extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn); 295 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 296 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 297 extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 298 __u64 window_size, __u32 levels); 299 extern int pnv_eeh_post_init(void); 300 301 __printf(3, 4) 302 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 303 const char *fmt, ...); 304 #define pe_err(pe, fmt, ...) \ 305 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 306 #define pe_warn(pe, fmt, ...) \ 307 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 308 #define pe_info(pe, fmt, ...) \ 309 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 310 311 /* pci-ioda-tce.c */ 312 #define POWERNV_IOMMU_DEFAULT_LEVELS 2 313 #define POWERNV_IOMMU_MAX_LEVELS 5 314 315 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 316 unsigned long uaddr, enum dma_data_direction direction, 317 unsigned long attrs); 318 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 319 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 320 unsigned long *hpa, enum dma_data_direction *direction, 321 bool alloc); 322 extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 323 bool alloc); 324 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 325 326 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 327 __u32 page_shift, __u64 window_size, __u32 levels, 328 bool alloc_userspace_copy, struct iommu_table *tbl); 329 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 330 331 extern long pnv_pci_link_table_and_group(int node, int num, 332 struct iommu_table *tbl, 333 struct iommu_table_group *table_group); 334 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 335 struct iommu_table_group *table_group); 336 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 337 void *tce_mem, u64 tce_size, 338 u64 dma_offset, unsigned int page_shift); 339 340 extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 341 342 static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus) 343 { 344 struct pci_controller *hose = bus->sysdata; 345 346 if (hose) 347 return hose->private_data; 348 349 return NULL; 350 } 351 352 #endif /* __POWERNV_PCI_H */ 353