1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __POWERNV_PCI_H 3 #define __POWERNV_PCI_H 4 5 #include <linux/compiler.h> /* for __printf */ 6 #include <linux/iommu.h> 7 #include <asm/iommu.h> 8 #include <asm/msi_bitmap.h> 9 10 struct pci_dn; 11 12 enum pnv_phb_type { 13 PNV_PHB_IODA1 = 0, 14 PNV_PHB_IODA2 = 1, 15 PNV_PHB_NPU_NVLINK = 2, 16 PNV_PHB_NPU_OCAPI = 3, 17 }; 18 19 /* Precise PHB model for error management */ 20 enum pnv_phb_model { 21 PNV_PHB_MODEL_UNKNOWN, 22 PNV_PHB_MODEL_P7IOC, 23 PNV_PHB_MODEL_PHB3, 24 PNV_PHB_MODEL_NPU, 25 PNV_PHB_MODEL_NPU2, 26 }; 27 28 #define PNV_PCI_DIAG_BUF_SIZE 8192 29 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 30 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 31 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35 36 /* 37 * A brief note on PNV_IODA_PE_BUS_ALL 38 * 39 * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses 40 * the Requester ID field of the PCIe request header to determine the device 41 * (and PE) that initiated a DMA. In legacy PCI individual memory read/write 42 * requests aren't tagged with the RID. To work around this the PCIe-to-PCI 43 * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side. 44 * 45 * PCIe-to-X bridges have a similar issue even though PCI-X requests also have 46 * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take 47 * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe 48 * side of the bridge. 49 * 50 * To work around these problems we use the BUS_ALL flag since every subordinate 51 * bus of the bridge should go into the same PE. 52 */ 53 54 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 55 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 56 57 /* Data associated with a PE, including IOMMU tracking etc.. */ 58 struct pnv_phb; 59 struct pnv_ioda_pe { 60 unsigned long flags; 61 struct pnv_phb *phb; 62 int device_count; 63 64 /* A PE can be associated with a single device or an 65 * entire bus (& children). In the former case, pdev 66 * is populated, in the later case, pbus is. 67 */ 68 #ifdef CONFIG_PCI_IOV 69 struct pci_dev *parent_dev; 70 #endif 71 struct pci_dev *pdev; 72 struct pci_bus *pbus; 73 74 /* Effective RID (device RID for a device PE and base bus 75 * RID with devfn 0 for a bus PE) 76 */ 77 unsigned int rid; 78 79 /* PE number */ 80 unsigned int pe_number; 81 82 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 83 struct iommu_table_group table_group; 84 struct npu_comp *npucomp; 85 86 /* 64-bit TCE bypass region */ 87 bool tce_bypass_enabled; 88 uint64_t tce_bypass_base; 89 90 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 91 * and -1 if not supported. (It's actually identical to the 92 * PE number) 93 */ 94 int mve_number; 95 96 /* PEs in compound case */ 97 struct pnv_ioda_pe *master; 98 struct list_head slaves; 99 100 /* Link in list of PE#s */ 101 struct list_head list; 102 }; 103 104 #define PNV_PHB_FLAG_EEH (1 << 0) 105 106 struct pnv_phb { 107 struct pci_controller *hose; 108 enum pnv_phb_type type; 109 enum pnv_phb_model model; 110 u64 hub_id; 111 u64 opal_id; 112 int flags; 113 void __iomem *regs; 114 u64 regs_phys; 115 int initialized; 116 spinlock_t lock; 117 118 #ifdef CONFIG_DEBUG_FS 119 int has_dbgfs; 120 struct dentry *dbgfs; 121 #endif 122 123 unsigned int msi_base; 124 unsigned int msi32_support; 125 struct msi_bitmap msi_bmp; 126 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 127 unsigned int hwirq, unsigned int virq, 128 unsigned int is_64, struct msi_msg *msg); 129 int (*init_m64)(struct pnv_phb *phb); 130 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 131 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 132 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 133 134 struct { 135 /* Global bridge info */ 136 unsigned int total_pe_num; 137 unsigned int reserved_pe_idx; 138 unsigned int root_pe_idx; 139 140 /* 32-bit MMIO window */ 141 unsigned int m32_size; 142 unsigned int m32_segsize; 143 unsigned int m32_pci_base; 144 145 /* 64-bit MMIO window */ 146 unsigned int m64_bar_idx; 147 unsigned long m64_size; 148 unsigned long m64_segsize; 149 unsigned long m64_base; 150 unsigned long m64_bar_alloc; 151 152 /* IO ports */ 153 unsigned int io_size; 154 unsigned int io_segsize; 155 unsigned int io_pci_base; 156 157 /* PE allocation */ 158 struct mutex pe_alloc_mutex; 159 unsigned long *pe_alloc; 160 struct pnv_ioda_pe *pe_array; 161 162 /* M32 & IO segment maps */ 163 unsigned int *m64_segmap; 164 unsigned int *m32_segmap; 165 unsigned int *io_segmap; 166 167 /* DMA32 segment maps - IODA1 only */ 168 unsigned int dma32_count; 169 unsigned int *dma32_segmap; 170 171 /* IRQ chip */ 172 int irq_chip_init; 173 struct irq_chip irq_chip; 174 175 /* Sorted list of used PE's based 176 * on the sequence of creation 177 */ 178 struct list_head pe_list; 179 struct mutex pe_list_mutex; 180 181 /* Reverse map of PEs, indexed by {bus, devfn} */ 182 unsigned int pe_rmap[0x10000]; 183 } ioda; 184 185 /* PHB and hub diagnostics */ 186 unsigned int diag_data_size; 187 u8 *diag_data; 188 }; 189 190 extern struct pci_ops pnv_pci_ops; 191 192 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 193 unsigned char *log_buff); 194 int pnv_pci_cfg_read(struct pci_dn *pdn, 195 int where, int size, u32 *val); 196 int pnv_pci_cfg_write(struct pci_dn *pdn, 197 int where, int size, u32 val); 198 extern struct iommu_table *pnv_pci_table_alloc(int nid); 199 200 extern void pnv_pci_init_ioda_hub(struct device_node *np); 201 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 202 extern void pnv_pci_init_npu_phb(struct device_node *np); 203 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 204 extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr); 205 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 206 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 207 208 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 209 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 210 extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn); 211 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 212 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 213 extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 214 __u64 window_size, __u32 levels); 215 extern int pnv_eeh_post_init(void); 216 217 __printf(3, 4) 218 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 219 const char *fmt, ...); 220 #define pe_err(pe, fmt, ...) \ 221 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 222 #define pe_warn(pe, fmt, ...) \ 223 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 224 #define pe_info(pe, fmt, ...) \ 225 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 226 227 /* Nvlink functions */ 228 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 229 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 230 extern void pnv_pci_npu_setup_iommu_groups(void); 231 232 /* pci-ioda-tce.c */ 233 #define POWERNV_IOMMU_DEFAULT_LEVELS 2 234 #define POWERNV_IOMMU_MAX_LEVELS 5 235 236 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 237 unsigned long uaddr, enum dma_data_direction direction, 238 unsigned long attrs); 239 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 240 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 241 unsigned long *hpa, enum dma_data_direction *direction, 242 bool alloc); 243 extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 244 bool alloc); 245 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 246 247 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 248 __u32 page_shift, __u64 window_size, __u32 levels, 249 bool alloc_userspace_copy, struct iommu_table *tbl); 250 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 251 252 extern long pnv_pci_link_table_and_group(int node, int num, 253 struct iommu_table *tbl, 254 struct iommu_table_group *table_group); 255 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 256 struct iommu_table_group *table_group); 257 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 258 void *tce_mem, u64 tce_size, 259 u64 dma_offset, unsigned int page_shift); 260 261 extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 262 263 static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus) 264 { 265 struct pci_controller *hose = bus->sysdata; 266 267 if (hose) 268 return hose->private_data; 269 270 return NULL; 271 } 272 273 #endif /* __POWERNV_PCI_H */ 274