1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 struct pci_dn; 5 6 enum pnv_phb_type { 7 PNV_PHB_P5IOC2 = 0, 8 PNV_PHB_IODA1 = 1, 9 PNV_PHB_IODA2 = 2, 10 }; 11 12 /* Precise PHB model for error management */ 13 enum pnv_phb_model { 14 PNV_PHB_MODEL_UNKNOWN, 15 PNV_PHB_MODEL_P5IOC2, 16 PNV_PHB_MODEL_P7IOC, 17 PNV_PHB_MODEL_PHB3, 18 }; 19 20 #define PNV_PCI_DIAG_BUF_SIZE 8192 21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24 25 /* Data associated with a PE, including IOMMU tracking etc.. */ 26 struct pnv_phb; 27 struct pnv_ioda_pe { 28 unsigned long flags; 29 struct pnv_phb *phb; 30 31 /* A PE can be associated with a single device or an 32 * entire bus (& children). In the former case, pdev 33 * is populated, in the later case, pbus is. 34 */ 35 struct pci_dev *pdev; 36 struct pci_bus *pbus; 37 38 /* Effective RID (device RID for a device PE and base bus 39 * RID with devfn 0 for a bus PE) 40 */ 41 unsigned int rid; 42 43 /* PE number */ 44 unsigned int pe_number; 45 46 /* "Weight" assigned to the PE for the sake of DMA resource 47 * allocations 48 */ 49 unsigned int dma_weight; 50 51 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 52 int tce32_seg; 53 int tce32_segcount; 54 struct iommu_table tce32_table; 55 phys_addr_t tce_inval_reg_phys; 56 57 /* XXX TODO: Add support for additional 64-bit iommus */ 58 59 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 60 * and -1 if not supported. (It's actually identical to the 61 * PE number) 62 */ 63 int mve_number; 64 65 /* Link in list of PE#s */ 66 struct list_head dma_link; 67 struct list_head list; 68 }; 69 70 /* IOC dependent EEH operations */ 71 #ifdef CONFIG_EEH 72 struct pnv_eeh_ops { 73 int (*post_init)(struct pci_controller *hose); 74 int (*set_option)(struct eeh_pe *pe, int option); 75 int (*get_state)(struct eeh_pe *pe); 76 int (*reset)(struct eeh_pe *pe, int option); 77 int (*get_log)(struct eeh_pe *pe, int severity, 78 char *drv_log, unsigned long len); 79 int (*configure_bridge)(struct eeh_pe *pe); 80 int (*next_error)(struct eeh_pe **pe); 81 }; 82 83 #define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */ 84 #define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */ 85 86 #endif /* CONFIG_EEH */ 87 88 struct pnv_phb { 89 struct pci_controller *hose; 90 enum pnv_phb_type type; 91 enum pnv_phb_model model; 92 u64 hub_id; 93 u64 opal_id; 94 void __iomem *regs; 95 int initialized; 96 spinlock_t lock; 97 98 #ifdef CONFIG_EEH 99 struct pnv_eeh_ops *eeh_ops; 100 int eeh_state; 101 #endif 102 103 #ifdef CONFIG_DEBUG_FS 104 struct dentry *dbgfs; 105 #endif 106 107 #ifdef CONFIG_PCI_MSI 108 unsigned int msi_base; 109 unsigned int msi32_support; 110 struct msi_bitmap msi_bmp; 111 #endif 112 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 113 unsigned int hwirq, unsigned int virq, 114 unsigned int is_64, struct msi_msg *msg); 115 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 116 void (*fixup_phb)(struct pci_controller *hose); 117 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 118 void (*shutdown)(struct pnv_phb *phb); 119 120 union { 121 struct { 122 struct iommu_table iommu_table; 123 } p5ioc2; 124 125 struct { 126 /* Global bridge info */ 127 unsigned int total_pe; 128 unsigned int reserved_pe; 129 unsigned int m32_size; 130 unsigned int m32_segsize; 131 unsigned int m32_pci_base; 132 unsigned int io_size; 133 unsigned int io_segsize; 134 unsigned int io_pci_base; 135 136 /* PE allocation bitmap */ 137 unsigned long *pe_alloc; 138 139 /* M32 & IO segment maps */ 140 unsigned int *m32_segmap; 141 unsigned int *io_segmap; 142 struct pnv_ioda_pe *pe_array; 143 144 /* IRQ chip */ 145 int irq_chip_init; 146 struct irq_chip irq_chip; 147 148 /* Sorted list of used PE's based 149 * on the sequence of creation 150 */ 151 struct list_head pe_list; 152 153 /* Reverse map of PEs, will have to extend if 154 * we are to support more than 256 PEs, indexed 155 * bus { bus, devfn } 156 */ 157 unsigned char pe_rmap[0x10000]; 158 159 /* 32-bit TCE tables allocation */ 160 unsigned long tce32_count; 161 162 /* Total "weight" for the sake of DMA resources 163 * allocation 164 */ 165 unsigned int dma_weight; 166 unsigned int dma_pe_count; 167 168 /* Sorted list of used PE's, sorted at 169 * boot for resource allocation purposes 170 */ 171 struct list_head pe_dma_list; 172 } ioda; 173 }; 174 175 /* PHB status structure */ 176 union { 177 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 178 struct OpalIoP7IOCPhbErrorData p7ioc; 179 } diag; 180 }; 181 182 extern struct pci_ops pnv_pci_ops; 183 #ifdef CONFIG_EEH 184 extern struct pnv_eeh_ops ioda_eeh_ops; 185 #endif 186 187 int pnv_pci_cfg_read(struct device_node *dn, 188 int where, int size, u32 *val); 189 int pnv_pci_cfg_write(struct device_node *dn, 190 int where, int size, u32 val); 191 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 192 void *tce_mem, u64 tce_size, 193 u64 dma_offset); 194 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 195 extern void pnv_pci_init_ioda_hub(struct device_node *np); 196 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 197 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 198 __be64 *startp, __be64 *endp, bool rm); 199 200 #endif /* __POWERNV_PCI_H */ 201