1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 #include <linux/iommu.h> 5 #include <asm/iommu.h> 6 #include <asm/msi_bitmap.h> 7 8 struct pci_dn; 9 10 /* Maximum possible number of ATSD MMIO registers per NPU */ 11 #define NV_NMMU_ATSD_REGS 8 12 13 enum pnv_phb_type { 14 PNV_PHB_IODA1 = 0, 15 PNV_PHB_IODA2 = 1, 16 PNV_PHB_NPU = 2, 17 }; 18 19 /* Precise PHB model for error management */ 20 enum pnv_phb_model { 21 PNV_PHB_MODEL_UNKNOWN, 22 PNV_PHB_MODEL_P7IOC, 23 PNV_PHB_MODEL_PHB3, 24 PNV_PHB_MODEL_NPU, 25 PNV_PHB_MODEL_NPU2, 26 }; 27 28 #define PNV_PCI_DIAG_BUF_SIZE 8192 29 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 30 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 31 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35 36 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 37 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 38 39 /* Data associated with a PE, including IOMMU tracking etc.. */ 40 struct pnv_phb; 41 struct pnv_ioda_pe { 42 unsigned long flags; 43 struct pnv_phb *phb; 44 int device_count; 45 46 /* A PE can be associated with a single device or an 47 * entire bus (& children). In the former case, pdev 48 * is populated, in the later case, pbus is. 49 */ 50 #ifdef CONFIG_PCI_IOV 51 struct pci_dev *parent_dev; 52 #endif 53 struct pci_dev *pdev; 54 struct pci_bus *pbus; 55 56 /* Effective RID (device RID for a device PE and base bus 57 * RID with devfn 0 for a bus PE) 58 */ 59 unsigned int rid; 60 61 /* PE number */ 62 unsigned int pe_number; 63 64 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 65 struct iommu_table_group table_group; 66 67 /* 64-bit TCE bypass region */ 68 bool tce_bypass_enabled; 69 uint64_t tce_bypass_base; 70 71 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 72 * and -1 if not supported. (It's actually identical to the 73 * PE number) 74 */ 75 int mve_number; 76 77 /* PEs in compound case */ 78 struct pnv_ioda_pe *master; 79 struct list_head slaves; 80 81 /* Link in list of PE#s */ 82 struct list_head list; 83 }; 84 85 #define PNV_PHB_FLAG_EEH (1 << 0) 86 #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */ 87 88 struct pnv_phb { 89 struct pci_controller *hose; 90 enum pnv_phb_type type; 91 enum pnv_phb_model model; 92 u64 hub_id; 93 u64 opal_id; 94 int flags; 95 void __iomem *regs; 96 u64 regs_phys; 97 int initialized; 98 spinlock_t lock; 99 100 #ifdef CONFIG_DEBUG_FS 101 int has_dbgfs; 102 struct dentry *dbgfs; 103 #endif 104 105 #ifdef CONFIG_PCI_MSI 106 unsigned int msi_base; 107 unsigned int msi32_support; 108 struct msi_bitmap msi_bmp; 109 #endif 110 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 111 unsigned int hwirq, unsigned int virq, 112 unsigned int is_64, struct msi_msg *msg); 113 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 114 void (*fixup_phb)(struct pci_controller *hose); 115 int (*init_m64)(struct pnv_phb *phb); 116 void (*reserve_m64_pe)(struct pci_bus *bus, 117 unsigned long *pe_bitmap, bool all); 118 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all); 119 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 120 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 121 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 122 123 struct { 124 /* Global bridge info */ 125 unsigned int total_pe_num; 126 unsigned int reserved_pe_idx; 127 unsigned int root_pe_idx; 128 bool root_pe_populated; 129 130 /* 32-bit MMIO window */ 131 unsigned int m32_size; 132 unsigned int m32_segsize; 133 unsigned int m32_pci_base; 134 135 /* 64-bit MMIO window */ 136 unsigned int m64_bar_idx; 137 unsigned long m64_size; 138 unsigned long m64_segsize; 139 unsigned long m64_base; 140 unsigned long m64_bar_alloc; 141 142 /* IO ports */ 143 unsigned int io_size; 144 unsigned int io_segsize; 145 unsigned int io_pci_base; 146 147 /* PE allocation */ 148 struct mutex pe_alloc_mutex; 149 unsigned long *pe_alloc; 150 struct pnv_ioda_pe *pe_array; 151 152 /* M32 & IO segment maps */ 153 unsigned int *m64_segmap; 154 unsigned int *m32_segmap; 155 unsigned int *io_segmap; 156 157 /* DMA32 segment maps - IODA1 only */ 158 unsigned int dma32_count; 159 unsigned int *dma32_segmap; 160 161 /* IRQ chip */ 162 int irq_chip_init; 163 struct irq_chip irq_chip; 164 165 /* Sorted list of used PE's based 166 * on the sequence of creation 167 */ 168 struct list_head pe_list; 169 struct mutex pe_list_mutex; 170 171 /* Reverse map of PEs, indexed by {bus, devfn} */ 172 unsigned int pe_rmap[0x10000]; 173 } ioda; 174 175 /* PHB and hub status structure */ 176 union { 177 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 178 struct OpalIoP7IOCPhbErrorData p7ioc; 179 struct OpalIoPhb3ErrorData phb3; 180 struct OpalIoP7IOCErrorData hub_diag; 181 } diag; 182 183 /* Nvlink2 data */ 184 struct npu { 185 int index; 186 __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS]; 187 unsigned int mmio_atsd_count; 188 189 /* Bitmask for MMIO register usage */ 190 unsigned long mmio_atsd_usage; 191 } npu; 192 193 #ifdef CONFIG_CXL_BASE 194 struct cxl_afu *cxl_afu; 195 #endif 196 }; 197 198 extern struct pci_ops pnv_pci_ops; 199 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 200 unsigned long uaddr, enum dma_data_direction direction, 201 unsigned long attrs); 202 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 203 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 204 unsigned long *hpa, enum dma_data_direction *direction); 205 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 206 207 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 208 unsigned char *log_buff); 209 int pnv_pci_cfg_read(struct pci_dn *pdn, 210 int where, int size, u32 *val); 211 int pnv_pci_cfg_write(struct pci_dn *pdn, 212 int where, int size, u32 val); 213 extern struct iommu_table *pnv_pci_table_alloc(int nid); 214 215 extern long pnv_pci_link_table_and_group(int node, int num, 216 struct iommu_table *tbl, 217 struct iommu_table_group *table_group); 218 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 219 struct iommu_table_group *table_group); 220 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 221 void *tce_mem, u64 tce_size, 222 u64 dma_offset, unsigned page_shift); 223 extern void pnv_pci_init_ioda_hub(struct device_node *np); 224 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 225 extern void pnv_pci_init_npu_phb(struct device_node *np); 226 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 227 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 228 229 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 230 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 231 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 232 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 233 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 234 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 235 extern bool pnv_pci_enable_device_hook(struct pci_dev *dev); 236 237 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 238 const char *fmt, ...); 239 #define pe_err(pe, fmt, ...) \ 240 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 241 #define pe_warn(pe, fmt, ...) \ 242 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 243 #define pe_info(pe, fmt, ...) \ 244 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 245 246 /* Nvlink functions */ 247 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 248 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 249 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 250 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, 251 struct iommu_table *tbl); 252 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num); 253 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe); 254 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe); 255 extern int pnv_npu2_init(struct pnv_phb *phb); 256 257 /* cxl functions */ 258 extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev); 259 extern void pnv_cxl_disable_device(struct pci_dev *dev); 260 extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 261 extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev); 262 263 264 /* phb ops (cxl switches these when enabling the kernel api on the phb) */ 265 extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops; 266 267 #endif /* __POWERNV_PCI_H */ 268