1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __POWERNV_PCI_H 3 #define __POWERNV_PCI_H 4 5 #include <linux/compiler.h> /* for __printf */ 6 #include <linux/iommu.h> 7 #include <asm/iommu.h> 8 #include <asm/msi_bitmap.h> 9 10 struct pci_dn; 11 12 enum pnv_phb_type { 13 PNV_PHB_IODA1 = 0, 14 PNV_PHB_IODA2 = 1, 15 PNV_PHB_NPU_NVLINK = 2, 16 PNV_PHB_NPU_OCAPI = 3, 17 }; 18 19 /* Precise PHB model for error management */ 20 enum pnv_phb_model { 21 PNV_PHB_MODEL_UNKNOWN, 22 PNV_PHB_MODEL_P7IOC, 23 PNV_PHB_MODEL_PHB3, 24 PNV_PHB_MODEL_NPU, 25 PNV_PHB_MODEL_NPU2, 26 }; 27 28 #define PNV_PCI_DIAG_BUF_SIZE 8192 29 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 30 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 31 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35 36 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 37 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 38 39 /* Data associated with a PE, including IOMMU tracking etc.. */ 40 struct pnv_phb; 41 struct pnv_ioda_pe { 42 unsigned long flags; 43 struct pnv_phb *phb; 44 int device_count; 45 46 /* A PE can be associated with a single device or an 47 * entire bus (& children). In the former case, pdev 48 * is populated, in the later case, pbus is. 49 */ 50 #ifdef CONFIG_PCI_IOV 51 struct pci_dev *parent_dev; 52 #endif 53 struct pci_dev *pdev; 54 struct pci_bus *pbus; 55 56 /* Effective RID (device RID for a device PE and base bus 57 * RID with devfn 0 for a bus PE) 58 */ 59 unsigned int rid; 60 61 /* PE number */ 62 unsigned int pe_number; 63 64 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 65 struct iommu_table_group table_group; 66 struct npu_comp *npucomp; 67 68 /* 64-bit TCE bypass region */ 69 bool tce_bypass_enabled; 70 uint64_t tce_bypass_base; 71 72 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 73 * and -1 if not supported. (It's actually identical to the 74 * PE number) 75 */ 76 int mve_number; 77 78 /* PEs in compound case */ 79 struct pnv_ioda_pe *master; 80 struct list_head slaves; 81 82 /* PCI peer-to-peer*/ 83 int p2p_initiator_count; 84 85 /* Link in list of PE#s */ 86 struct list_head list; 87 }; 88 89 #define PNV_PHB_FLAG_EEH (1 << 0) 90 91 struct pnv_phb { 92 struct pci_controller *hose; 93 enum pnv_phb_type type; 94 enum pnv_phb_model model; 95 u64 hub_id; 96 u64 opal_id; 97 int flags; 98 void __iomem *regs; 99 u64 regs_phys; 100 int initialized; 101 spinlock_t lock; 102 103 #ifdef CONFIG_DEBUG_FS 104 int has_dbgfs; 105 struct dentry *dbgfs; 106 #endif 107 108 unsigned int msi_base; 109 unsigned int msi32_support; 110 struct msi_bitmap msi_bmp; 111 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 112 unsigned int hwirq, unsigned int virq, 113 unsigned int is_64, struct msi_msg *msg); 114 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 115 int (*init_m64)(struct pnv_phb *phb); 116 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 117 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 118 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 119 120 struct { 121 /* Global bridge info */ 122 unsigned int total_pe_num; 123 unsigned int reserved_pe_idx; 124 unsigned int root_pe_idx; 125 bool root_pe_populated; 126 127 /* 32-bit MMIO window */ 128 unsigned int m32_size; 129 unsigned int m32_segsize; 130 unsigned int m32_pci_base; 131 132 /* 64-bit MMIO window */ 133 unsigned int m64_bar_idx; 134 unsigned long m64_size; 135 unsigned long m64_segsize; 136 unsigned long m64_base; 137 unsigned long m64_bar_alloc; 138 139 /* IO ports */ 140 unsigned int io_size; 141 unsigned int io_segsize; 142 unsigned int io_pci_base; 143 144 /* PE allocation */ 145 struct mutex pe_alloc_mutex; 146 unsigned long *pe_alloc; 147 struct pnv_ioda_pe *pe_array; 148 149 /* M32 & IO segment maps */ 150 unsigned int *m64_segmap; 151 unsigned int *m32_segmap; 152 unsigned int *io_segmap; 153 154 /* DMA32 segment maps - IODA1 only */ 155 unsigned int dma32_count; 156 unsigned int *dma32_segmap; 157 158 /* IRQ chip */ 159 int irq_chip_init; 160 struct irq_chip irq_chip; 161 162 /* Sorted list of used PE's based 163 * on the sequence of creation 164 */ 165 struct list_head pe_list; 166 struct mutex pe_list_mutex; 167 168 /* Reverse map of PEs, indexed by {bus, devfn} */ 169 unsigned int pe_rmap[0x10000]; 170 } ioda; 171 172 /* PHB and hub diagnostics */ 173 unsigned int diag_data_size; 174 u8 *diag_data; 175 176 int p2p_target_count; 177 }; 178 179 extern struct pci_ops pnv_pci_ops; 180 181 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 182 unsigned char *log_buff); 183 int pnv_pci_cfg_read(struct pci_dn *pdn, 184 int where, int size, u32 *val); 185 int pnv_pci_cfg_write(struct pci_dn *pdn, 186 int where, int size, u32 val); 187 extern struct iommu_table *pnv_pci_table_alloc(int nid); 188 189 extern void pnv_pci_init_ioda_hub(struct device_node *np); 190 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 191 extern void pnv_pci_init_npu_phb(struct device_node *np); 192 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 193 extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr); 194 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 195 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 196 197 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 198 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 199 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 200 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 201 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 202 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 203 extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 204 extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 205 __u64 window_size, __u32 levels); 206 extern int pnv_eeh_post_init(void); 207 208 __printf(3, 4) 209 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 210 const char *fmt, ...); 211 #define pe_err(pe, fmt, ...) \ 212 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 213 #define pe_warn(pe, fmt, ...) \ 214 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 215 #define pe_info(pe, fmt, ...) \ 216 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 217 218 /* Nvlink functions */ 219 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 220 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 221 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 222 extern struct iommu_table_group *pnv_try_setup_npu_table_group( 223 struct pnv_ioda_pe *pe); 224 extern struct iommu_table_group *pnv_npu_compound_attach( 225 struct pnv_ioda_pe *pe); 226 227 /* pci-ioda-tce.c */ 228 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 229 #define POWERNV_IOMMU_MAX_LEVELS 5 230 231 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 232 unsigned long uaddr, enum dma_data_direction direction, 233 unsigned long attrs); 234 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 235 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 236 unsigned long *hpa, enum dma_data_direction *direction, 237 bool alloc); 238 extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 239 bool alloc); 240 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 241 242 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 243 __u32 page_shift, __u64 window_size, __u32 levels, 244 bool alloc_userspace_copy, struct iommu_table *tbl); 245 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 246 247 extern long pnv_pci_link_table_and_group(int node, int num, 248 struct iommu_table *tbl, 249 struct iommu_table_group *table_group); 250 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 251 struct iommu_table_group *table_group); 252 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 253 void *tce_mem, u64 tce_size, 254 u64 dma_offset, unsigned int page_shift); 255 256 #endif /* __POWERNV_PCI_H */ 257