1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 struct pci_dn; 5 6 enum pnv_phb_type { 7 PNV_PHB_P5IOC2 = 0, 8 PNV_PHB_IODA1 = 1, 9 PNV_PHB_IODA2 = 2, 10 }; 11 12 /* Precise PHB model for error management */ 13 enum pnv_phb_model { 14 PNV_PHB_MODEL_UNKNOWN, 15 PNV_PHB_MODEL_P5IOC2, 16 PNV_PHB_MODEL_P7IOC, 17 PNV_PHB_MODEL_PHB3, 18 }; 19 20 #define PNV_PCI_DIAG_BUF_SIZE 8192 21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 26 27 /* Data associated with a PE, including IOMMU tracking etc.. */ 28 struct pnv_phb; 29 struct pnv_ioda_pe { 30 unsigned long flags; 31 struct pnv_phb *phb; 32 33 /* A PE can be associated with a single device or an 34 * entire bus (& children). In the former case, pdev 35 * is populated, in the later case, pbus is. 36 */ 37 struct pci_dev *pdev; 38 struct pci_bus *pbus; 39 40 /* Effective RID (device RID for a device PE and base bus 41 * RID with devfn 0 for a bus PE) 42 */ 43 unsigned int rid; 44 45 /* PE number */ 46 unsigned int pe_number; 47 48 /* "Weight" assigned to the PE for the sake of DMA resource 49 * allocations 50 */ 51 unsigned int dma_weight; 52 53 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 54 int tce32_seg; 55 int tce32_segcount; 56 struct iommu_table tce32_table; 57 phys_addr_t tce_inval_reg_phys; 58 59 /* 64-bit TCE bypass region */ 60 bool tce_bypass_enabled; 61 uint64_t tce_bypass_base; 62 63 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 64 * and -1 if not supported. (It's actually identical to the 65 * PE number) 66 */ 67 int mve_number; 68 69 /* PEs in compound case */ 70 struct pnv_ioda_pe *master; 71 struct list_head slaves; 72 73 /* Link in list of PE#s */ 74 struct list_head dma_link; 75 struct list_head list; 76 }; 77 78 /* IOC dependent EEH operations */ 79 #ifdef CONFIG_EEH 80 struct pnv_eeh_ops { 81 int (*post_init)(struct pci_controller *hose); 82 int (*set_option)(struct eeh_pe *pe, int option); 83 int (*get_state)(struct eeh_pe *pe); 84 int (*reset)(struct eeh_pe *pe, int option); 85 int (*get_log)(struct eeh_pe *pe, int severity, 86 char *drv_log, unsigned long len); 87 int (*configure_bridge)(struct eeh_pe *pe); 88 int (*next_error)(struct eeh_pe **pe); 89 }; 90 #endif /* CONFIG_EEH */ 91 92 #define PNV_PHB_FLAG_EEH (1 << 0) 93 94 struct pnv_phb { 95 struct pci_controller *hose; 96 enum pnv_phb_type type; 97 enum pnv_phb_model model; 98 u64 hub_id; 99 u64 opal_id; 100 int flags; 101 void __iomem *regs; 102 int initialized; 103 spinlock_t lock; 104 105 #ifdef CONFIG_EEH 106 struct pnv_eeh_ops *eeh_ops; 107 #endif 108 109 #ifdef CONFIG_DEBUG_FS 110 int has_dbgfs; 111 struct dentry *dbgfs; 112 #endif 113 114 #ifdef CONFIG_PCI_MSI 115 unsigned int msi_base; 116 unsigned int msi32_support; 117 struct msi_bitmap msi_bmp; 118 #endif 119 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 120 unsigned int hwirq, unsigned int virq, 121 unsigned int is_64, struct msi_msg *msg); 122 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 123 int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev, 124 u64 dma_mask); 125 void (*fixup_phb)(struct pci_controller *hose); 126 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 127 void (*shutdown)(struct pnv_phb *phb); 128 int (*init_m64)(struct pnv_phb *phb); 129 void (*alloc_m64_pe)(struct pnv_phb *phb); 130 int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all); 131 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 132 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 133 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 134 135 union { 136 struct { 137 struct iommu_table iommu_table; 138 } p5ioc2; 139 140 struct { 141 /* Global bridge info */ 142 unsigned int total_pe; 143 unsigned int reserved_pe; 144 145 /* 32-bit MMIO window */ 146 unsigned int m32_size; 147 unsigned int m32_segsize; 148 unsigned int m32_pci_base; 149 150 /* 64-bit MMIO window */ 151 unsigned int m64_bar_idx; 152 unsigned long m64_size; 153 unsigned long m64_segsize; 154 unsigned long m64_base; 155 unsigned long m64_bar_alloc; 156 157 /* IO ports */ 158 unsigned int io_size; 159 unsigned int io_segsize; 160 unsigned int io_pci_base; 161 162 /* PE allocation bitmap */ 163 unsigned long *pe_alloc; 164 165 /* M32 & IO segment maps */ 166 unsigned int *m32_segmap; 167 unsigned int *io_segmap; 168 struct pnv_ioda_pe *pe_array; 169 170 /* IRQ chip */ 171 int irq_chip_init; 172 struct irq_chip irq_chip; 173 174 /* Sorted list of used PE's based 175 * on the sequence of creation 176 */ 177 struct list_head pe_list; 178 179 /* Reverse map of PEs, will have to extend if 180 * we are to support more than 256 PEs, indexed 181 * bus { bus, devfn } 182 */ 183 unsigned char pe_rmap[0x10000]; 184 185 /* 32-bit TCE tables allocation */ 186 unsigned long tce32_count; 187 188 /* Total "weight" for the sake of DMA resources 189 * allocation 190 */ 191 unsigned int dma_weight; 192 unsigned int dma_pe_count; 193 194 /* Sorted list of used PE's, sorted at 195 * boot for resource allocation purposes 196 */ 197 struct list_head pe_dma_list; 198 } ioda; 199 }; 200 201 /* PHB and hub status structure */ 202 union { 203 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 204 struct OpalIoP7IOCPhbErrorData p7ioc; 205 struct OpalIoPhb3ErrorData phb3; 206 struct OpalIoP7IOCErrorData hub_diag; 207 } diag; 208 209 }; 210 211 extern struct pci_ops pnv_pci_ops; 212 #ifdef CONFIG_EEH 213 extern struct pnv_eeh_ops ioda_eeh_ops; 214 #endif 215 216 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 217 unsigned char *log_buff); 218 int pnv_pci_cfg_read(struct device_node *dn, 219 int where, int size, u32 *val); 220 int pnv_pci_cfg_write(struct device_node *dn, 221 int where, int size, u32 val); 222 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 223 void *tce_mem, u64 tce_size, 224 u64 dma_offset, unsigned page_shift); 225 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 226 extern void pnv_pci_init_ioda_hub(struct device_node *np); 227 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 228 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 229 __be64 *startp, __be64 *endp, bool rm); 230 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 231 extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option); 232 233 #endif /* __POWERNV_PCI_H */ 234