1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __POWERNV_PCI_H 3 #define __POWERNV_PCI_H 4 5 #include <linux/compiler.h> /* for __printf */ 6 #include <linux/iommu.h> 7 #include <asm/iommu.h> 8 #include <asm/msi_bitmap.h> 9 10 struct pci_dn; 11 12 enum pnv_phb_type { 13 PNV_PHB_IODA1 = 0, 14 PNV_PHB_IODA2 = 1, 15 PNV_PHB_NPU_NVLINK = 2, 16 PNV_PHB_NPU_OCAPI = 3, 17 }; 18 19 /* Precise PHB model for error management */ 20 enum pnv_phb_model { 21 PNV_PHB_MODEL_UNKNOWN, 22 PNV_PHB_MODEL_P7IOC, 23 PNV_PHB_MODEL_PHB3, 24 PNV_PHB_MODEL_NPU, 25 PNV_PHB_MODEL_NPU2, 26 }; 27 28 #define PNV_PCI_DIAG_BUF_SIZE 8192 29 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 30 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 31 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35 36 /* 37 * A brief note on PNV_IODA_PE_BUS_ALL 38 * 39 * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses 40 * the Requester ID field of the PCIe request header to determine the device 41 * (and PE) that initiated a DMA. In legacy PCI individual memory read/write 42 * requests aren't tagged with the RID. To work around this the PCIe-to-PCI 43 * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side. 44 * 45 * PCIe-to-X bridges have a similar issue even though PCI-X requests also have 46 * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take 47 * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe 48 * side of the bridge. 49 * 50 * To work around these problems we use the BUS_ALL flag since every subordinate 51 * bus of the bridge should go into the same PE. 52 */ 53 54 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 55 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 56 57 /* Data associated with a PE, including IOMMU tracking etc.. */ 58 struct pnv_phb; 59 struct pnv_ioda_pe { 60 unsigned long flags; 61 struct pnv_phb *phb; 62 int device_count; 63 64 /* A PE can be associated with a single device or an 65 * entire bus (& children). In the former case, pdev 66 * is populated, in the later case, pbus is. 67 */ 68 #ifdef CONFIG_PCI_IOV 69 struct pci_dev *parent_dev; 70 #endif 71 struct pci_dev *pdev; 72 struct pci_bus *pbus; 73 74 /* Effective RID (device RID for a device PE and base bus 75 * RID with devfn 0 for a bus PE) 76 */ 77 unsigned int rid; 78 79 /* PE number */ 80 unsigned int pe_number; 81 82 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 83 struct iommu_table_group table_group; 84 struct npu_comp *npucomp; 85 86 /* 64-bit TCE bypass region */ 87 bool tce_bypass_enabled; 88 uint64_t tce_bypass_base; 89 90 /* 91 * Used to track whether we've done DMA setup for this PE or not. We 92 * want to defer allocating TCE tables, etc until we've added a 93 * non-bridge device to the PE. 94 */ 95 bool dma_setup_done; 96 97 /* MSIs. MVE index is identical for 32 and 64 bit MSI 98 * and -1 if not supported. (It's actually identical to the 99 * PE number) 100 */ 101 int mve_number; 102 103 /* PEs in compound case */ 104 struct pnv_ioda_pe *master; 105 struct list_head slaves; 106 107 /* Link in list of PE#s */ 108 struct list_head list; 109 }; 110 111 #define PNV_PHB_FLAG_EEH (1 << 0) 112 113 struct pnv_phb { 114 struct pci_controller *hose; 115 enum pnv_phb_type type; 116 enum pnv_phb_model model; 117 u64 hub_id; 118 u64 opal_id; 119 int flags; 120 void __iomem *regs; 121 u64 regs_phys; 122 spinlock_t lock; 123 124 #ifdef CONFIG_DEBUG_FS 125 int has_dbgfs; 126 struct dentry *dbgfs; 127 #endif 128 129 unsigned int msi_base; 130 unsigned int msi32_support; 131 struct msi_bitmap msi_bmp; 132 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 133 unsigned int hwirq, unsigned int virq, 134 unsigned int is_64, struct msi_msg *msg); 135 int (*init_m64)(struct pnv_phb *phb); 136 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 137 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 138 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 139 140 struct { 141 /* Global bridge info */ 142 unsigned int total_pe_num; 143 unsigned int reserved_pe_idx; 144 unsigned int root_pe_idx; 145 146 /* 32-bit MMIO window */ 147 unsigned int m32_size; 148 unsigned int m32_segsize; 149 unsigned int m32_pci_base; 150 151 /* 64-bit MMIO window */ 152 unsigned int m64_bar_idx; 153 unsigned long m64_size; 154 unsigned long m64_segsize; 155 unsigned long m64_base; 156 #define MAX_M64_BARS 64 157 unsigned long m64_bar_alloc; 158 159 /* IO ports */ 160 unsigned int io_size; 161 unsigned int io_segsize; 162 unsigned int io_pci_base; 163 164 /* PE allocation */ 165 struct mutex pe_alloc_mutex; 166 unsigned long *pe_alloc; 167 struct pnv_ioda_pe *pe_array; 168 169 /* M32 & IO segment maps */ 170 unsigned int *m64_segmap; 171 unsigned int *m32_segmap; 172 unsigned int *io_segmap; 173 174 /* DMA32 segment maps - IODA1 only */ 175 unsigned int dma32_count; 176 unsigned int *dma32_segmap; 177 178 /* IRQ chip */ 179 int irq_chip_init; 180 struct irq_chip irq_chip; 181 182 /* Sorted list of used PE's based 183 * on the sequence of creation 184 */ 185 struct list_head pe_list; 186 struct mutex pe_list_mutex; 187 188 /* Reverse map of PEs, indexed by {bus, devfn} */ 189 unsigned int pe_rmap[0x10000]; 190 } ioda; 191 192 /* PHB and hub diagnostics */ 193 unsigned int diag_data_size; 194 u8 *diag_data; 195 }; 196 197 198 /* IODA PE management */ 199 200 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 201 { 202 /* 203 * WARNING: We cannot rely on the resource flags. The Linux PCI 204 * allocation code sometimes decides to put a 64-bit prefetchable 205 * BAR in the 32-bit window, so we have to compare the addresses. 206 * 207 * For simplicity we only test resource start. 208 */ 209 return (r->start >= phb->ioda.m64_base && 210 r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 211 } 212 213 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 214 { 215 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 216 217 return (resource_flags & flags) == flags; 218 } 219 220 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 221 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 222 223 void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 224 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe); 225 226 struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count); 227 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe); 228 229 #ifdef CONFIG_PCI_IOV 230 /* 231 * For SR-IOV we want to put each VF's MMIO resource in to a separate PE. 232 * This requires a bit of acrobatics with the MMIO -> PE configuration 233 * and this structure is used to keep track of it all. 234 */ 235 struct pnv_iov_data { 236 /* number of VFs enabled */ 237 u16 num_vfs; 238 239 /* pointer to the array of VF PEs. num_vfs long*/ 240 struct pnv_ioda_pe *vf_pe_arr; 241 242 /* Did we map the VF BAR with single-PE IODA BARs? */ 243 bool m64_single_mode[PCI_SRIOV_NUM_BARS]; 244 245 /* 246 * True if we're using any segmented windows. In that case we need 247 * shift the start of the IOV resource the segment corresponding to 248 * the allocated PE. 249 */ 250 bool need_shift; 251 252 /* 253 * Bit mask used to track which m64 windows are used to map the 254 * SR-IOV BARs for this device. 255 */ 256 DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS); 257 258 /* 259 * If we map the SR-IOV BARs with a segmented window then 260 * parts of that window will be "claimed" by other PEs. 261 * 262 * "holes" here is used to reserve the leading portion 263 * of the window that is used by other (non VF) PEs. 264 */ 265 struct resource holes[PCI_SRIOV_NUM_BARS]; 266 }; 267 268 static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev) 269 { 270 return pdev->dev.archdata.iov_data; 271 } 272 273 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev); 274 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno); 275 276 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 277 int pnv_pcibios_sriov_disable(struct pci_dev *pdev); 278 #endif /* CONFIG_PCI_IOV */ 279 280 extern struct pci_ops pnv_pci_ops; 281 282 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 283 unsigned char *log_buff); 284 int pnv_pci_cfg_read(struct pci_dn *pdn, 285 int where, int size, u32 *val); 286 int pnv_pci_cfg_write(struct pci_dn *pdn, 287 int where, int size, u32 val); 288 extern struct iommu_table *pnv_pci_table_alloc(int nid); 289 290 extern void pnv_pci_init_ioda_hub(struct device_node *np); 291 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 292 extern void pnv_pci_init_npu_phb(struct device_node *np); 293 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 294 extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr); 295 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 296 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 297 298 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 299 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 300 extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn); 301 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 302 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 303 extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 304 __u64 window_size, __u32 levels); 305 extern int pnv_eeh_post_init(void); 306 307 __printf(3, 4) 308 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 309 const char *fmt, ...); 310 #define pe_err(pe, fmt, ...) \ 311 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 312 #define pe_warn(pe, fmt, ...) \ 313 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 314 #define pe_info(pe, fmt, ...) \ 315 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 316 317 /* Nvlink functions */ 318 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 319 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 320 extern void pnv_pci_npu_setup_iommu_groups(void); 321 322 /* pci-ioda-tce.c */ 323 #define POWERNV_IOMMU_DEFAULT_LEVELS 2 324 #define POWERNV_IOMMU_MAX_LEVELS 5 325 326 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 327 unsigned long uaddr, enum dma_data_direction direction, 328 unsigned long attrs); 329 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 330 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 331 unsigned long *hpa, enum dma_data_direction *direction, 332 bool alloc); 333 extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 334 bool alloc); 335 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 336 337 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 338 __u32 page_shift, __u64 window_size, __u32 levels, 339 bool alloc_userspace_copy, struct iommu_table *tbl); 340 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 341 342 extern long pnv_pci_link_table_and_group(int node, int num, 343 struct iommu_table *tbl, 344 struct iommu_table_group *table_group); 345 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 346 struct iommu_table_group *table_group); 347 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 348 void *tce_mem, u64 tce_size, 349 u64 dma_offset, unsigned int page_shift); 350 351 extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 352 353 static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus) 354 { 355 struct pci_controller *hose = bus->sysdata; 356 357 if (hose) 358 return hose->private_data; 359 360 return NULL; 361 } 362 363 #endif /* __POWERNV_PCI_H */ 364