1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 #include <linux/iommu.h> 5 #include <asm/iommu.h> 6 #include <asm/msi_bitmap.h> 7 8 struct pci_dn; 9 10 /* Maximum possible number of ATSD MMIO registers per NPU */ 11 #define NV_NMMU_ATSD_REGS 8 12 13 enum pnv_phb_type { 14 PNV_PHB_IODA1 = 0, 15 PNV_PHB_IODA2 = 1, 16 PNV_PHB_NPU = 2, 17 }; 18 19 /* Precise PHB model for error management */ 20 enum pnv_phb_model { 21 PNV_PHB_MODEL_UNKNOWN, 22 PNV_PHB_MODEL_P7IOC, 23 PNV_PHB_MODEL_PHB3, 24 PNV_PHB_MODEL_NPU, 25 PNV_PHB_MODEL_NPU2, 26 }; 27 28 #define PNV_PCI_DIAG_BUF_SIZE 8192 29 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 30 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 31 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35 36 /* Data associated with a PE, including IOMMU tracking etc.. */ 37 struct pnv_phb; 38 struct pnv_ioda_pe { 39 unsigned long flags; 40 struct pnv_phb *phb; 41 int device_count; 42 43 /* A PE can be associated with a single device or an 44 * entire bus (& children). In the former case, pdev 45 * is populated, in the later case, pbus is. 46 */ 47 #ifdef CONFIG_PCI_IOV 48 struct pci_dev *parent_dev; 49 #endif 50 struct pci_dev *pdev; 51 struct pci_bus *pbus; 52 53 /* Effective RID (device RID for a device PE and base bus 54 * RID with devfn 0 for a bus PE) 55 */ 56 unsigned int rid; 57 58 /* PE number */ 59 unsigned int pe_number; 60 61 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 62 struct iommu_table_group table_group; 63 64 /* 64-bit TCE bypass region */ 65 bool tce_bypass_enabled; 66 uint64_t tce_bypass_base; 67 68 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 69 * and -1 if not supported. (It's actually identical to the 70 * PE number) 71 */ 72 int mve_number; 73 74 /* PEs in compound case */ 75 struct pnv_ioda_pe *master; 76 struct list_head slaves; 77 78 /* Link in list of PE#s */ 79 struct list_head list; 80 }; 81 82 #define PNV_PHB_FLAG_EEH (1 << 0) 83 #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */ 84 85 struct pnv_phb { 86 struct pci_controller *hose; 87 enum pnv_phb_type type; 88 enum pnv_phb_model model; 89 u64 hub_id; 90 u64 opal_id; 91 int flags; 92 void __iomem *regs; 93 u64 regs_phys; 94 int initialized; 95 spinlock_t lock; 96 97 #ifdef CONFIG_DEBUG_FS 98 int has_dbgfs; 99 struct dentry *dbgfs; 100 #endif 101 102 #ifdef CONFIG_PCI_MSI 103 unsigned int msi_base; 104 unsigned int msi32_support; 105 struct msi_bitmap msi_bmp; 106 #endif 107 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 108 unsigned int hwirq, unsigned int virq, 109 unsigned int is_64, struct msi_msg *msg); 110 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 111 void (*fixup_phb)(struct pci_controller *hose); 112 int (*init_m64)(struct pnv_phb *phb); 113 void (*reserve_m64_pe)(struct pci_bus *bus, 114 unsigned long *pe_bitmap, bool all); 115 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all); 116 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 117 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 118 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 119 120 struct { 121 /* Global bridge info */ 122 unsigned int total_pe_num; 123 unsigned int reserved_pe_idx; 124 unsigned int root_pe_idx; 125 bool root_pe_populated; 126 127 /* 32-bit MMIO window */ 128 unsigned int m32_size; 129 unsigned int m32_segsize; 130 unsigned int m32_pci_base; 131 132 /* 64-bit MMIO window */ 133 unsigned int m64_bar_idx; 134 unsigned long m64_size; 135 unsigned long m64_segsize; 136 unsigned long m64_base; 137 unsigned long m64_bar_alloc; 138 139 /* IO ports */ 140 unsigned int io_size; 141 unsigned int io_segsize; 142 unsigned int io_pci_base; 143 144 /* PE allocation */ 145 struct mutex pe_alloc_mutex; 146 unsigned long *pe_alloc; 147 struct pnv_ioda_pe *pe_array; 148 149 /* M32 & IO segment maps */ 150 unsigned int *m64_segmap; 151 unsigned int *m32_segmap; 152 unsigned int *io_segmap; 153 154 /* DMA32 segment maps - IODA1 only */ 155 unsigned int dma32_count; 156 unsigned int *dma32_segmap; 157 158 /* IRQ chip */ 159 int irq_chip_init; 160 struct irq_chip irq_chip; 161 162 /* Sorted list of used PE's based 163 * on the sequence of creation 164 */ 165 struct list_head pe_list; 166 struct mutex pe_list_mutex; 167 168 /* Reverse map of PEs, indexed by {bus, devfn} */ 169 unsigned int pe_rmap[0x10000]; 170 } ioda; 171 172 /* PHB and hub status structure */ 173 union { 174 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 175 struct OpalIoP7IOCPhbErrorData p7ioc; 176 struct OpalIoPhb3ErrorData phb3; 177 struct OpalIoP7IOCErrorData hub_diag; 178 } diag; 179 180 /* Nvlink2 data */ 181 struct npu { 182 int index; 183 __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS]; 184 unsigned int mmio_atsd_count; 185 186 /* Bitmask for MMIO register usage */ 187 unsigned long mmio_atsd_usage; 188 } npu; 189 190 #ifdef CONFIG_CXL_BASE 191 struct cxl_afu *cxl_afu; 192 #endif 193 }; 194 195 extern struct pci_ops pnv_pci_ops; 196 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 197 unsigned long uaddr, enum dma_data_direction direction, 198 unsigned long attrs); 199 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 200 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 201 unsigned long *hpa, enum dma_data_direction *direction); 202 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 203 204 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 205 unsigned char *log_buff); 206 int pnv_pci_cfg_read(struct pci_dn *pdn, 207 int where, int size, u32 *val); 208 int pnv_pci_cfg_write(struct pci_dn *pdn, 209 int where, int size, u32 val); 210 extern struct iommu_table *pnv_pci_table_alloc(int nid); 211 212 extern long pnv_pci_link_table_and_group(int node, int num, 213 struct iommu_table *tbl, 214 struct iommu_table_group *table_group); 215 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 216 struct iommu_table_group *table_group); 217 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 218 void *tce_mem, u64 tce_size, 219 u64 dma_offset, unsigned page_shift); 220 extern void pnv_pci_init_ioda_hub(struct device_node *np); 221 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 222 extern void pnv_pci_init_npu_phb(struct device_node *np); 223 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 224 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 225 226 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 227 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 228 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 229 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 230 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 231 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 232 extern bool pnv_pci_enable_device_hook(struct pci_dev *dev); 233 234 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 235 const char *fmt, ...); 236 #define pe_err(pe, fmt, ...) \ 237 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 238 #define pe_warn(pe, fmt, ...) \ 239 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 240 #define pe_info(pe, fmt, ...) \ 241 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 242 243 /* Nvlink functions */ 244 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 245 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 246 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 247 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, 248 struct iommu_table *tbl); 249 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num); 250 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe); 251 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe); 252 extern int pnv_npu2_init(struct pnv_phb *phb); 253 254 /* cxl functions */ 255 extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev); 256 extern void pnv_cxl_disable_device(struct pci_dev *dev); 257 extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 258 extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev); 259 260 261 /* phb ops (cxl switches these when enabling the kernel api on the phb) */ 262 extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops; 263 264 #endif /* __POWERNV_PCI_H */ 265