1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __POWERNV_PCI_H 3 #define __POWERNV_PCI_H 4 5 #include <linux/iommu.h> 6 #include <asm/iommu.h> 7 #include <asm/msi_bitmap.h> 8 9 struct pci_dn; 10 11 /* Maximum possible number of ATSD MMIO registers per NPU */ 12 #define NV_NMMU_ATSD_REGS 8 13 14 enum pnv_phb_type { 15 PNV_PHB_IODA1 = 0, 16 PNV_PHB_IODA2 = 1, 17 PNV_PHB_NPU_NVLINK = 2, 18 PNV_PHB_NPU_OCAPI = 3, 19 }; 20 21 /* Precise PHB model for error management */ 22 enum pnv_phb_model { 23 PNV_PHB_MODEL_UNKNOWN, 24 PNV_PHB_MODEL_P7IOC, 25 PNV_PHB_MODEL_PHB3, 26 PNV_PHB_MODEL_NPU, 27 PNV_PHB_MODEL_NPU2, 28 }; 29 30 #define PNV_PCI_DIAG_BUF_SIZE 8192 31 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 32 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 33 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 34 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 35 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 36 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 37 38 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 39 #define PNV_IODA_STOPPED_STATE 0x8000000000000000 40 41 /* Data associated with a PE, including IOMMU tracking etc.. */ 42 struct pnv_phb; 43 struct pnv_ioda_pe { 44 unsigned long flags; 45 struct pnv_phb *phb; 46 int device_count; 47 48 /* A PE can be associated with a single device or an 49 * entire bus (& children). In the former case, pdev 50 * is populated, in the later case, pbus is. 51 */ 52 #ifdef CONFIG_PCI_IOV 53 struct pci_dev *parent_dev; 54 #endif 55 struct pci_dev *pdev; 56 struct pci_bus *pbus; 57 58 /* Effective RID (device RID for a device PE and base bus 59 * RID with devfn 0 for a bus PE) 60 */ 61 unsigned int rid; 62 63 /* PE number */ 64 unsigned int pe_number; 65 66 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 67 struct iommu_table_group table_group; 68 69 /* 64-bit TCE bypass region */ 70 bool tce_bypass_enabled; 71 uint64_t tce_bypass_base; 72 73 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 74 * and -1 if not supported. (It's actually identical to the 75 * PE number) 76 */ 77 int mve_number; 78 79 /* PEs in compound case */ 80 struct pnv_ioda_pe *master; 81 struct list_head slaves; 82 83 /* PCI peer-to-peer*/ 84 int p2p_initiator_count; 85 86 /* Link in list of PE#s */ 87 struct list_head list; 88 }; 89 90 #define PNV_PHB_FLAG_EEH (1 << 0) 91 #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */ 92 93 struct pnv_phb { 94 struct pci_controller *hose; 95 enum pnv_phb_type type; 96 enum pnv_phb_model model; 97 u64 hub_id; 98 u64 opal_id; 99 int flags; 100 void __iomem *regs; 101 u64 regs_phys; 102 int initialized; 103 spinlock_t lock; 104 105 #ifdef CONFIG_DEBUG_FS 106 int has_dbgfs; 107 struct dentry *dbgfs; 108 #endif 109 110 #ifdef CONFIG_PCI_MSI 111 unsigned int msi_base; 112 unsigned int msi32_support; 113 struct msi_bitmap msi_bmp; 114 #endif 115 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 116 unsigned int hwirq, unsigned int virq, 117 unsigned int is_64, struct msi_msg *msg); 118 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 119 void (*fixup_phb)(struct pci_controller *hose); 120 int (*init_m64)(struct pnv_phb *phb); 121 void (*reserve_m64_pe)(struct pci_bus *bus, 122 unsigned long *pe_bitmap, bool all); 123 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all); 124 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 125 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 126 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 127 128 struct { 129 /* Global bridge info */ 130 unsigned int total_pe_num; 131 unsigned int reserved_pe_idx; 132 unsigned int root_pe_idx; 133 bool root_pe_populated; 134 135 /* 32-bit MMIO window */ 136 unsigned int m32_size; 137 unsigned int m32_segsize; 138 unsigned int m32_pci_base; 139 140 /* 64-bit MMIO window */ 141 unsigned int m64_bar_idx; 142 unsigned long m64_size; 143 unsigned long m64_segsize; 144 unsigned long m64_base; 145 unsigned long m64_bar_alloc; 146 147 /* IO ports */ 148 unsigned int io_size; 149 unsigned int io_segsize; 150 unsigned int io_pci_base; 151 152 /* PE allocation */ 153 struct mutex pe_alloc_mutex; 154 unsigned long *pe_alloc; 155 struct pnv_ioda_pe *pe_array; 156 157 /* M32 & IO segment maps */ 158 unsigned int *m64_segmap; 159 unsigned int *m32_segmap; 160 unsigned int *io_segmap; 161 162 /* DMA32 segment maps - IODA1 only */ 163 unsigned int dma32_count; 164 unsigned int *dma32_segmap; 165 166 /* IRQ chip */ 167 int irq_chip_init; 168 struct irq_chip irq_chip; 169 170 /* Sorted list of used PE's based 171 * on the sequence of creation 172 */ 173 struct list_head pe_list; 174 struct mutex pe_list_mutex; 175 176 /* Reverse map of PEs, indexed by {bus, devfn} */ 177 unsigned int pe_rmap[0x10000]; 178 } ioda; 179 180 /* PHB and hub diagnostics */ 181 unsigned int diag_data_size; 182 u8 *diag_data; 183 184 /* Nvlink2 data */ 185 struct npu { 186 int index; 187 __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS]; 188 unsigned int mmio_atsd_count; 189 190 /* Bitmask for MMIO register usage */ 191 unsigned long mmio_atsd_usage; 192 193 /* Do we need to explicitly flush the nest mmu? */ 194 bool nmmu_flush; 195 } npu; 196 197 #ifdef CONFIG_CXL_BASE 198 struct cxl_afu *cxl_afu; 199 #endif 200 int p2p_target_count; 201 }; 202 203 extern struct pci_ops pnv_pci_ops; 204 205 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 206 unsigned char *log_buff); 207 int pnv_pci_cfg_read(struct pci_dn *pdn, 208 int where, int size, u32 *val); 209 int pnv_pci_cfg_write(struct pci_dn *pdn, 210 int where, int size, u32 val); 211 extern struct iommu_table *pnv_pci_table_alloc(int nid); 212 213 extern void pnv_pci_init_ioda_hub(struct device_node *np); 214 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 215 extern void pnv_pci_init_npu_phb(struct device_node *np); 216 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 217 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 218 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 219 220 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 221 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 222 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 223 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 224 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 225 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 226 extern bool pnv_pci_enable_device_hook(struct pci_dev *dev); 227 extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 228 extern int pnv_eeh_post_init(void); 229 230 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 231 const char *fmt, ...); 232 #define pe_err(pe, fmt, ...) \ 233 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 234 #define pe_warn(pe, fmt, ...) \ 235 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 236 #define pe_info(pe, fmt, ...) \ 237 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 238 239 /* Nvlink functions */ 240 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 241 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 242 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 243 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, 244 struct iommu_table *tbl); 245 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num); 246 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe); 247 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe); 248 extern int pnv_npu2_init(struct pnv_phb *phb); 249 250 /* cxl functions */ 251 extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev); 252 extern void pnv_cxl_disable_device(struct pci_dev *dev); 253 extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 254 extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev); 255 256 257 /* phb ops (cxl switches these when enabling the kernel api on the phb) */ 258 extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops; 259 260 /* pci-ioda-tce.c */ 261 #define POWERNV_IOMMU_DEFAULT_LEVELS 1 262 #define POWERNV_IOMMU_MAX_LEVELS 5 263 264 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 265 unsigned long uaddr, enum dma_data_direction direction, 266 unsigned long attrs); 267 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 268 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 269 unsigned long *hpa, enum dma_data_direction *direction); 270 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 271 272 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 273 __u32 page_shift, __u64 window_size, __u32 levels, 274 struct iommu_table *tbl); 275 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 276 277 extern long pnv_pci_link_table_and_group(int node, int num, 278 struct iommu_table *tbl, 279 struct iommu_table_group *table_group); 280 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 281 struct iommu_table_group *table_group); 282 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 283 void *tce_mem, u64 tce_size, 284 u64 dma_offset, unsigned int page_shift); 285 286 #endif /* __POWERNV_PCI_H */ 287