1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 261305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 461305a96SBenjamin Herrenschmidt 51e496391SJoe Perches #include <linux/compiler.h> /* for __printf */ 6f456834aSIan Munsie #include <linux/iommu.h> 7f456834aSIan Munsie #include <asm/iommu.h> 8f456834aSIan Munsie #include <asm/msi_bitmap.h> 9f456834aSIan Munsie 1061305a96SBenjamin Herrenschmidt struct pci_dn; 1161305a96SBenjamin Herrenschmidt 1261305a96SBenjamin Herrenschmidt enum pnv_phb_type { 13562d1e20SChristoph Hellwig PNV_PHB_IODA1, 14562d1e20SChristoph Hellwig PNV_PHB_IODA2, 15562d1e20SChristoph Hellwig PNV_PHB_NPU_OCAPI, 1661305a96SBenjamin Herrenschmidt }; 1761305a96SBenjamin Herrenschmidt 18cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 19cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 20cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 21cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 22aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 23cee72d5bSBenjamin Herrenschmidt }; 24cee72d5bSBenjamin Herrenschmidt 255c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 267ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 277ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 287ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 29262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 30262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 31781a868fSWei Yang #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 32cee72d5bSBenjamin Herrenschmidt 339d0879a2SOliver O'Halloran /* 349d0879a2SOliver O'Halloran * A brief note on PNV_IODA_PE_BUS_ALL 359d0879a2SOliver O'Halloran * 369d0879a2SOliver O'Halloran * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses 379d0879a2SOliver O'Halloran * the Requester ID field of the PCIe request header to determine the device 389d0879a2SOliver O'Halloran * (and PE) that initiated a DMA. In legacy PCI individual memory read/write 399d0879a2SOliver O'Halloran * requests aren't tagged with the RID. To work around this the PCIe-to-PCI 409d0879a2SOliver O'Halloran * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side. 419d0879a2SOliver O'Halloran * 429d0879a2SOliver O'Halloran * PCIe-to-X bridges have a similar issue even though PCI-X requests also have 439d0879a2SOliver O'Halloran * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take 449d0879a2SOliver O'Halloran * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe 459d0879a2SOliver O'Halloran * side of the bridge. 469d0879a2SOliver O'Halloran * 479d0879a2SOliver O'Halloran * To work around these problems we use the BUS_ALL flag since every subordinate 489d0879a2SOliver O'Halloran * bus of the bridge should go into the same PE. 499d0879a2SOliver O'Halloran */ 509d0879a2SOliver O'Halloran 5131bbd45aSRussell Currey /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 5231bbd45aSRussell Currey #define PNV_IODA_STOPPED_STATE 0x8000000000000000 5331bbd45aSRussell Currey 54184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 554cce9550SGavin Shan struct pnv_phb; 56184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 577ebdf956SGavin Shan unsigned long flags; 584cce9550SGavin Shan struct pnv_phb *phb; 59c5f7700bSGavin Shan int device_count; 607ebdf956SGavin Shan 61184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 62184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 63184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 64184cd4a3SBenjamin Herrenschmidt */ 65781a868fSWei Yang #ifdef CONFIG_PCI_IOV 66781a868fSWei Yang struct pci_dev *parent_dev; 67781a868fSWei Yang #endif 68184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 69184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 70184cd4a3SBenjamin Herrenschmidt 71184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 72184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 73184cd4a3SBenjamin Herrenschmidt */ 74184cd4a3SBenjamin Herrenschmidt unsigned int rid; 75184cd4a3SBenjamin Herrenschmidt 76184cd4a3SBenjamin Herrenschmidt /* PE number */ 77184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 78184cd4a3SBenjamin Herrenschmidt 79184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 80b348aa65SAlexey Kardashevskiy struct iommu_table_group table_group; 81184cd4a3SBenjamin Herrenschmidt 82cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 83cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 84cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 85184cd4a3SBenjamin Herrenschmidt 8601e12629SOliver O'Halloran /* 8701e12629SOliver O'Halloran * Used to track whether we've done DMA setup for this PE or not. We 8801e12629SOliver O'Halloran * want to defer allocating TCE tables, etc until we've added a 8901e12629SOliver O'Halloran * non-bridge device to the PE. 9001e12629SOliver O'Halloran */ 9101e12629SOliver O'Halloran bool dma_setup_done; 9201e12629SOliver O'Halloran 9386052e40SRandy Dunlap /* MSIs. MVE index is identical for 32 and 64 bit MSI 94184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 95184cd4a3SBenjamin Herrenschmidt * PE number) 96184cd4a3SBenjamin Herrenschmidt */ 97184cd4a3SBenjamin Herrenschmidt int mve_number; 98184cd4a3SBenjamin Herrenschmidt 99262af557SGuo Chao /* PEs in compound case */ 100262af557SGuo Chao struct pnv_ioda_pe *master; 101262af557SGuo Chao struct list_head slaves; 102262af557SGuo Chao 103184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 1047ebdf956SGavin Shan struct list_head list; 105184cd4a3SBenjamin Herrenschmidt }; 106184cd4a3SBenjamin Herrenschmidt 107f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 108f5bc6b70SGavin Shan 10961305a96SBenjamin Herrenschmidt struct pnv_phb { 11061305a96SBenjamin Herrenschmidt struct pci_controller *hose; 11161305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 112cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 1138747f363SGavin Shan u64 hub_id; 11461305a96SBenjamin Herrenschmidt u64 opal_id; 115f5bc6b70SGavin Shan int flags; 11661305a96SBenjamin Herrenschmidt void __iomem *regs; 117fd141d1aSBenjamin Herrenschmidt u64 regs_phys; 11861305a96SBenjamin Herrenschmidt spinlock_t lock; 11961305a96SBenjamin Herrenschmidt 12037c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 1217f52a526SGavin Shan int has_dbgfs; 12237c367f2SGavin Shan struct dentry *dbgfs; 12337c367f2SGavin Shan #endif 12437c367f2SGavin Shan 125c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 126fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 127262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 12849dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 12949dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 13049dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 13161305a96SBenjamin Herrenschmidt 132184cd4a3SBenjamin Herrenschmidt struct { 133184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 13492b8f137SGavin Shan unsigned int total_pe_num; 13592b8f137SGavin Shan unsigned int reserved_pe_idx; 13663803c39SGavin Shan unsigned int root_pe_idx; 137262af557SGuo Chao 138262af557SGuo Chao /* 32-bit MMIO window */ 139184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 140184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 141184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 142262af557SGuo Chao 143262af557SGuo Chao /* 64-bit MMIO window */ 144262af557SGuo Chao unsigned int m64_bar_idx; 145262af557SGuo Chao unsigned long m64_size; 146262af557SGuo Chao unsigned long m64_segsize; 147262af557SGuo Chao unsigned long m64_base; 148ad9add52SOliver O'Halloran #define MAX_M64_BARS 64 149262af557SGuo Chao unsigned long m64_bar_alloc; 150262af557SGuo Chao 151262af557SGuo Chao /* IO ports */ 152184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 153184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 154184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 155184cd4a3SBenjamin Herrenschmidt 15613ce7598SGavin Shan /* PE allocation */ 157781a868fSWei Yang struct mutex pe_alloc_mutex; 15813ce7598SGavin Shan unsigned long *pe_alloc; 15913ce7598SGavin Shan struct pnv_ioda_pe *pe_array; 160184cd4a3SBenjamin Herrenschmidt 161184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 16293289d8cSGavin Shan unsigned int *m64_segmap; 163184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 164184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 165184cd4a3SBenjamin Herrenschmidt 1662b923ed1SGavin Shan /* DMA32 segment maps - IODA1 only */ 1672b923ed1SGavin Shan unsigned int dma32_count; 1682b923ed1SGavin Shan unsigned int *dma32_segmap; 1692b923ed1SGavin Shan 170137436c9SGavin Shan /* IRQ chip */ 171137436c9SGavin Shan int irq_chip_init; 172137436c9SGavin Shan struct irq_chip irq_chip; 173137436c9SGavin Shan 1747ebdf956SGavin Shan /* Sorted list of used PE's based 1757ebdf956SGavin Shan * on the sequence of creation 1767ebdf956SGavin Shan */ 1777ebdf956SGavin Shan struct list_head pe_list; 178781a868fSWei Yang struct mutex pe_list_mutex; 1797ebdf956SGavin Shan 180c127562aSGavin Shan /* Reverse map of PEs, indexed by {bus, devfn} */ 181c127562aSGavin Shan unsigned int pe_rmap[0x10000]; 182184cd4a3SBenjamin Herrenschmidt } ioda; 183cee72d5bSBenjamin Herrenschmidt 1845cb1f8fdSRussell Currey /* PHB and hub diagnostics */ 1855cb1f8fdSRussell Currey unsigned int diag_data_size; 1865cb1f8fdSRussell Currey u8 *diag_data; 18761305a96SBenjamin Herrenschmidt }; 18861305a96SBenjamin Herrenschmidt 18937b59ef0SOliver O'Halloran 19037b59ef0SOliver O'Halloran /* IODA PE management */ 19137b59ef0SOliver O'Halloran 19237b59ef0SOliver O'Halloran static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 19337b59ef0SOliver O'Halloran { 19437b59ef0SOliver O'Halloran /* 19537b59ef0SOliver O'Halloran * WARNING: We cannot rely on the resource flags. The Linux PCI 19637b59ef0SOliver O'Halloran * allocation code sometimes decides to put a 64-bit prefetchable 19737b59ef0SOliver O'Halloran * BAR in the 32-bit window, so we have to compare the addresses. 19837b59ef0SOliver O'Halloran * 19937b59ef0SOliver O'Halloran * For simplicity we only test resource start. 20037b59ef0SOliver O'Halloran */ 20137b59ef0SOliver O'Halloran return (r->start >= phb->ioda.m64_base && 20237b59ef0SOliver O'Halloran r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 20337b59ef0SOliver O'Halloran } 20437b59ef0SOliver O'Halloran 20537b59ef0SOliver O'Halloran static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 20637b59ef0SOliver O'Halloran { 20737b59ef0SOliver O'Halloran unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 20837b59ef0SOliver O'Halloran 20937b59ef0SOliver O'Halloran return (resource_flags & flags) == flags; 21037b59ef0SOliver O'Halloran } 21137b59ef0SOliver O'Halloran 21237b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 21337b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 21437b59ef0SOliver O'Halloran 21537b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 21637b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe); 21737b59ef0SOliver O'Halloran 218a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count); 21937b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe); 22037b59ef0SOliver O'Halloran 22137b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV 22237b59ef0SOliver O'Halloran /* 22337b59ef0SOliver O'Halloran * For SR-IOV we want to put each VF's MMIO resource in to a separate PE. 22437b59ef0SOliver O'Halloran * This requires a bit of acrobatics with the MMIO -> PE configuration 22537b59ef0SOliver O'Halloran * and this structure is used to keep track of it all. 22637b59ef0SOliver O'Halloran */ 22737b59ef0SOliver O'Halloran struct pnv_iov_data { 22837b59ef0SOliver O'Halloran /* number of VFs enabled */ 22937b59ef0SOliver O'Halloran u16 num_vfs; 230d29a2488SOliver O'Halloran 231052da31dSOliver O'Halloran /* pointer to the array of VF PEs. num_vfs long*/ 232d29a2488SOliver O'Halloran struct pnv_ioda_pe *vf_pe_arr; 23337b59ef0SOliver O'Halloran 2344c51f3e1SOliver O'Halloran /* Did we map the VF BAR with single-PE IODA BARs? */ 2354c51f3e1SOliver O'Halloran bool m64_single_mode[PCI_SRIOV_NUM_BARS]; 2364c51f3e1SOliver O'Halloran 2374c51f3e1SOliver O'Halloran /* 2384c51f3e1SOliver O'Halloran * True if we're using any segmented windows. In that case we need 2394c51f3e1SOliver O'Halloran * shift the start of the IOV resource the segment corresponding to 2404c51f3e1SOliver O'Halloran * the allocated PE. 2414c51f3e1SOliver O'Halloran */ 2424c51f3e1SOliver O'Halloran bool need_shift; 24337b59ef0SOliver O'Halloran 244ad9add52SOliver O'Halloran /* 245ad9add52SOliver O'Halloran * Bit mask used to track which m64 windows are used to map the 246ad9add52SOliver O'Halloran * SR-IOV BARs for this device. 247ad9add52SOliver O'Halloran */ 248ad9add52SOliver O'Halloran DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS); 24937b59ef0SOliver O'Halloran 25037b59ef0SOliver O'Halloran /* 25137b59ef0SOliver O'Halloran * If we map the SR-IOV BARs with a segmented window then 25237b59ef0SOliver O'Halloran * parts of that window will be "claimed" by other PEs. 25337b59ef0SOliver O'Halloran * 25437b59ef0SOliver O'Halloran * "holes" here is used to reserve the leading portion 25537b59ef0SOliver O'Halloran * of the window that is used by other (non VF) PEs. 25637b59ef0SOliver O'Halloran */ 25737b59ef0SOliver O'Halloran struct resource holes[PCI_SRIOV_NUM_BARS]; 25837b59ef0SOliver O'Halloran }; 25937b59ef0SOliver O'Halloran 26037b59ef0SOliver O'Halloran static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev) 26137b59ef0SOliver O'Halloran { 26237b59ef0SOliver O'Halloran return pdev->dev.archdata.iov_data; 26337b59ef0SOliver O'Halloran } 26437b59ef0SOliver O'Halloran 26537b59ef0SOliver O'Halloran void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev); 26637b59ef0SOliver O'Halloran resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno); 26737b59ef0SOliver O'Halloran 26837b59ef0SOliver O'Halloran int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 26937b59ef0SOliver O'Halloran int pnv_pcibios_sriov_disable(struct pci_dev *pdev); 27037b59ef0SOliver O'Halloran #endif /* CONFIG_PCI_IOV */ 27137b59ef0SOliver O'Halloran 27261305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 27361305a96SBenjamin Herrenschmidt 27493aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 27593aef2a7SGavin Shan unsigned char *log_buff); 2763532a741SGavin Shan int pnv_pci_cfg_read(struct pci_dn *pdn, 2779bf41be6SGavin Shan int where, int size, u32 *val); 2783532a741SGavin Shan int pnv_pci_cfg_write(struct pci_dn *pdn, 2799bf41be6SGavin Shan int where, int size, u32 val); 2800eaf4defSAlexey Kardashevskiy extern struct iommu_table *pnv_pci_table_alloc(int nid); 2810eaf4defSAlexey Kardashevskiy 282184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 283aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2847f2c39e9SFrederic Barrat extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 285d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 286cadf364dSGavin Shan extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 28773ed148aSBenjamin Herrenschmidt 288a8d7d5fcSOliver O'Halloran extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn); 289f456834aSIan Munsie extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 290f456834aSIan Munsie extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 2910bd97167SAlexey Kardashevskiy extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2920bd97167SAlexey Kardashevskiy __u64 window_size, __u32 levels); 293b9fde58dSBenjamin Herrenschmidt extern int pnv_eeh_post_init(void); 29492ae0353SDaniel Axtens 2951e496391SJoe Perches __printf(3, 4) 2967d623e42SAlexey Kardashevskiy extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 2977d623e42SAlexey Kardashevskiy const char *fmt, ...); 2987d623e42SAlexey Kardashevskiy #define pe_err(pe, fmt, ...) \ 2997d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 3007d623e42SAlexey Kardashevskiy #define pe_warn(pe, fmt, ...) \ 3017d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 3027d623e42SAlexey Kardashevskiy #define pe_info(pe, fmt, ...) \ 3037d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 3047d623e42SAlexey Kardashevskiy 305191c2287SAlexey Kardashevskiy /* pci-ioda-tce.c */ 306c37c792dSAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 2 307191c2287SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 308191c2287SAlexey Kardashevskiy 309191c2287SAlexey Kardashevskiy extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 310191c2287SAlexey Kardashevskiy unsigned long uaddr, enum dma_data_direction direction, 311191c2287SAlexey Kardashevskiy unsigned long attrs); 312191c2287SAlexey Kardashevskiy extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 313191c2287SAlexey Kardashevskiy extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 314*cad32d9dSAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction); 315a68bd126SAlexey Kardashevskiy extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 316a68bd126SAlexey Kardashevskiy bool alloc); 317191c2287SAlexey Kardashevskiy extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 318191c2287SAlexey Kardashevskiy 319191c2287SAlexey Kardashevskiy extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 320191c2287SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 321090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table *tbl); 322191c2287SAlexey Kardashevskiy extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 323191c2287SAlexey Kardashevskiy 324191c2287SAlexey Kardashevskiy extern long pnv_pci_link_table_and_group(int node, int num, 325191c2287SAlexey Kardashevskiy struct iommu_table *tbl, 326191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group); 327191c2287SAlexey Kardashevskiy extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 328191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group); 329191c2287SAlexey Kardashevskiy extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 330191c2287SAlexey Kardashevskiy void *tce_mem, u64 tce_size, 331191c2287SAlexey Kardashevskiy u64 dma_offset, unsigned int page_shift); 332191c2287SAlexey Kardashevskiy 33396e2006aSOliver O'Halloran extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 33496e2006aSOliver O'Halloran 3355609ffddSOliver O'Halloran static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus) 3365609ffddSOliver O'Halloran { 3375609ffddSOliver O'Halloran struct pci_controller *hose = bus->sysdata; 3385609ffddSOliver O'Halloran 3395609ffddSOliver O'Halloran if (hose) 3405609ffddSOliver O'Halloran return hose->private_data; 3415609ffddSOliver O'Halloran 3425609ffddSOliver O'Halloran return NULL; 3435609ffddSOliver O'Halloran } 3445609ffddSOliver O'Halloran 34561305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 346