161305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 261305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt 4f456834aSIan Munsie #include <linux/iommu.h> 5f456834aSIan Munsie #include <asm/iommu.h> 6f456834aSIan Munsie #include <asm/msi_bitmap.h> 7f456834aSIan Munsie 861305a96SBenjamin Herrenschmidt struct pci_dn; 961305a96SBenjamin Herrenschmidt 101ab66d1fSAlistair Popple /* Maximum possible number of ATSD MMIO registers per NPU */ 111ab66d1fSAlistair Popple #define NV_NMMU_ATSD_REGS 8 121ab66d1fSAlistair Popple 1361305a96SBenjamin Herrenschmidt enum pnv_phb_type { 142de50e96SRussell Currey PNV_PHB_IODA1 = 0, 152de50e96SRussell Currey PNV_PHB_IODA2 = 1, 162de50e96SRussell Currey PNV_PHB_NPU = 2, 1761305a96SBenjamin Herrenschmidt }; 1861305a96SBenjamin Herrenschmidt 19cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 20cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 21cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 22cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 23aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 245d2aa710SAlistair Popple PNV_PHB_MODEL_NPU, 25616badd2SAlistair Popple PNV_PHB_MODEL_NPU2, 26cee72d5bSBenjamin Herrenschmidt }; 27cee72d5bSBenjamin Herrenschmidt 285c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 297ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 307ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 317ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34781a868fSWei Yang #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35cee72d5bSBenjamin Herrenschmidt 3631bbd45aSRussell Currey /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 3731bbd45aSRussell Currey #define PNV_IODA_STOPPED_STATE 0x8000000000000000 3831bbd45aSRussell Currey 39184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 404cce9550SGavin Shan struct pnv_phb; 41184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 427ebdf956SGavin Shan unsigned long flags; 434cce9550SGavin Shan struct pnv_phb *phb; 44c5f7700bSGavin Shan int device_count; 457ebdf956SGavin Shan 46184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 47184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 48184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 49184cd4a3SBenjamin Herrenschmidt */ 50781a868fSWei Yang #ifdef CONFIG_PCI_IOV 51781a868fSWei Yang struct pci_dev *parent_dev; 52781a868fSWei Yang #endif 53184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 54184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 55184cd4a3SBenjamin Herrenschmidt 56184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 57184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 58184cd4a3SBenjamin Herrenschmidt */ 59184cd4a3SBenjamin Herrenschmidt unsigned int rid; 60184cd4a3SBenjamin Herrenschmidt 61184cd4a3SBenjamin Herrenschmidt /* PE number */ 62184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 63184cd4a3SBenjamin Herrenschmidt 64184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 65b348aa65SAlexey Kardashevskiy struct iommu_table_group table_group; 66184cd4a3SBenjamin Herrenschmidt 67cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 68cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 69cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 70184cd4a3SBenjamin Herrenschmidt 71184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 72184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 73184cd4a3SBenjamin Herrenschmidt * PE number) 74184cd4a3SBenjamin Herrenschmidt */ 75184cd4a3SBenjamin Herrenschmidt int mve_number; 76184cd4a3SBenjamin Herrenschmidt 77262af557SGuo Chao /* PEs in compound case */ 78262af557SGuo Chao struct pnv_ioda_pe *master; 79262af557SGuo Chao struct list_head slaves; 80262af557SGuo Chao 8125529100SFrederic Barrat /* PCI peer-to-peer*/ 8225529100SFrederic Barrat int p2p_initiator_count; 8325529100SFrederic Barrat 84184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 857ebdf956SGavin Shan struct list_head list; 86184cd4a3SBenjamin Herrenschmidt }; 87184cd4a3SBenjamin Herrenschmidt 88f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 894361b034SIan Munsie #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */ 90f5bc6b70SGavin Shan 9161305a96SBenjamin Herrenschmidt struct pnv_phb { 9261305a96SBenjamin Herrenschmidt struct pci_controller *hose; 9361305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 94cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 958747f363SGavin Shan u64 hub_id; 9661305a96SBenjamin Herrenschmidt u64 opal_id; 97f5bc6b70SGavin Shan int flags; 9861305a96SBenjamin Herrenschmidt void __iomem *regs; 99fd141d1aSBenjamin Herrenschmidt u64 regs_phys; 100db1266c8SGavin Shan int initialized; 10161305a96SBenjamin Herrenschmidt spinlock_t lock; 10261305a96SBenjamin Herrenschmidt 10337c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 1047f52a526SGavin Shan int has_dbgfs; 10537c367f2SGavin Shan struct dentry *dbgfs; 10637c367f2SGavin Shan #endif 10737c367f2SGavin Shan 108c1a2562aSBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 109c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 110c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 111fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 112c1a2562aSBenjamin Herrenschmidt #endif 113c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 114137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 115137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 11661305a96SBenjamin Herrenschmidt void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 11761305a96SBenjamin Herrenschmidt void (*fixup_phb)(struct pci_controller *hose); 118262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 11996a2f92bSGavin Shan void (*reserve_m64_pe)(struct pci_bus *bus, 12096a2f92bSGavin Shan unsigned long *pe_bitmap, bool all); 1211e916772SGavin Shan struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all); 12249dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 12349dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 12449dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 12561305a96SBenjamin Herrenschmidt 126184cd4a3SBenjamin Herrenschmidt struct { 127184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 12892b8f137SGavin Shan unsigned int total_pe_num; 12992b8f137SGavin Shan unsigned int reserved_pe_idx; 13063803c39SGavin Shan unsigned int root_pe_idx; 13163803c39SGavin Shan bool root_pe_populated; 132262af557SGuo Chao 133262af557SGuo Chao /* 32-bit MMIO window */ 134184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 135184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 136184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 137262af557SGuo Chao 138262af557SGuo Chao /* 64-bit MMIO window */ 139262af557SGuo Chao unsigned int m64_bar_idx; 140262af557SGuo Chao unsigned long m64_size; 141262af557SGuo Chao unsigned long m64_segsize; 142262af557SGuo Chao unsigned long m64_base; 143262af557SGuo Chao unsigned long m64_bar_alloc; 144262af557SGuo Chao 145262af557SGuo Chao /* IO ports */ 146184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 147184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 148184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 149184cd4a3SBenjamin Herrenschmidt 15013ce7598SGavin Shan /* PE allocation */ 151781a868fSWei Yang struct mutex pe_alloc_mutex; 15213ce7598SGavin Shan unsigned long *pe_alloc; 15313ce7598SGavin Shan struct pnv_ioda_pe *pe_array; 154184cd4a3SBenjamin Herrenschmidt 155184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 15693289d8cSGavin Shan unsigned int *m64_segmap; 157184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 158184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 159184cd4a3SBenjamin Herrenschmidt 1602b923ed1SGavin Shan /* DMA32 segment maps - IODA1 only */ 1612b923ed1SGavin Shan unsigned int dma32_count; 1622b923ed1SGavin Shan unsigned int *dma32_segmap; 1632b923ed1SGavin Shan 164137436c9SGavin Shan /* IRQ chip */ 165137436c9SGavin Shan int irq_chip_init; 166137436c9SGavin Shan struct irq_chip irq_chip; 167137436c9SGavin Shan 1687ebdf956SGavin Shan /* Sorted list of used PE's based 1697ebdf956SGavin Shan * on the sequence of creation 1707ebdf956SGavin Shan */ 1717ebdf956SGavin Shan struct list_head pe_list; 172781a868fSWei Yang struct mutex pe_list_mutex; 1737ebdf956SGavin Shan 174c127562aSGavin Shan /* Reverse map of PEs, indexed by {bus, devfn} */ 175c127562aSGavin Shan unsigned int pe_rmap[0x10000]; 176184cd4a3SBenjamin Herrenschmidt } ioda; 177cee72d5bSBenjamin Herrenschmidt 1785cb1f8fdSRussell Currey /* PHB and hub diagnostics */ 1795cb1f8fdSRussell Currey unsigned int diag_data_size; 1805cb1f8fdSRussell Currey u8 *diag_data; 181ca1de5deSBrian W Hart 1821ab66d1fSAlistair Popple /* Nvlink2 data */ 1831ab66d1fSAlistair Popple struct npu { 1841ab66d1fSAlistair Popple int index; 1851ab66d1fSAlistair Popple __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS]; 1861ab66d1fSAlistair Popple unsigned int mmio_atsd_count; 1871ab66d1fSAlistair Popple 1881ab66d1fSAlistair Popple /* Bitmask for MMIO register usage */ 1891ab66d1fSAlistair Popple unsigned long mmio_atsd_usage; 1901ab66d1fSAlistair Popple } npu; 1911ab66d1fSAlistair Popple 1924361b034SIan Munsie #ifdef CONFIG_CXL_BASE 1934361b034SIan Munsie struct cxl_afu *cxl_afu; 1944361b034SIan Munsie #endif 19525529100SFrederic Barrat int p2p_target_count; 19661305a96SBenjamin Herrenschmidt }; 19761305a96SBenjamin Herrenschmidt 19861305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 199da004c36SAlexey Kardashevskiy extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 200da004c36SAlexey Kardashevskiy unsigned long uaddr, enum dma_data_direction direction, 20100085f1eSKrzysztof Kozlowski unsigned long attrs); 202da004c36SAlexey Kardashevskiy extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 20305c6cfb9SAlexey Kardashevskiy extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 20405c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction); 205da004c36SAlexey Kardashevskiy extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 20661305a96SBenjamin Herrenschmidt 20793aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 20893aef2a7SGavin Shan unsigned char *log_buff); 2093532a741SGavin Shan int pnv_pci_cfg_read(struct pci_dn *pdn, 2109bf41be6SGavin Shan int where, int size, u32 *val); 2113532a741SGavin Shan int pnv_pci_cfg_write(struct pci_dn *pdn, 2129bf41be6SGavin Shan int where, int size, u32 val); 2130eaf4defSAlexey Kardashevskiy extern struct iommu_table *pnv_pci_table_alloc(int nid); 2140eaf4defSAlexey Kardashevskiy 2150eaf4defSAlexey Kardashevskiy extern long pnv_pci_link_table_and_group(int node, int num, 2160eaf4defSAlexey Kardashevskiy struct iommu_table *tbl, 2170eaf4defSAlexey Kardashevskiy struct iommu_table_group *table_group); 2180eaf4defSAlexey Kardashevskiy extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 2190eaf4defSAlexey Kardashevskiy struct iommu_table_group *table_group); 22061305a96SBenjamin Herrenschmidt extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 22161305a96SBenjamin Herrenschmidt void *tce_mem, u64 tce_size, 2228fa5d454SAlexey Kardashevskiy u64 dma_offset, unsigned page_shift); 223184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 224aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2255d2aa710SAlistair Popple extern void pnv_pci_init_npu_phb(struct device_node *np); 226d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 227cadf364dSGavin Shan extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 22873ed148aSBenjamin Herrenschmidt 22992ae0353SDaniel Axtens extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 2301bc74f1cSGavin Shan extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 23192ae0353SDaniel Axtens extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 23292ae0353SDaniel Axtens extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 233f456834aSIan Munsie extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 234f456834aSIan Munsie extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 2354361b034SIan Munsie extern bool pnv_pci_enable_device_hook(struct pci_dev *dev); 23625529100SFrederic Barrat extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 237b9fde58dSBenjamin Herrenschmidt extern int pnv_eeh_post_init(void); 23892ae0353SDaniel Axtens 2397d623e42SAlexey Kardashevskiy extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 2407d623e42SAlexey Kardashevskiy const char *fmt, ...); 2417d623e42SAlexey Kardashevskiy #define pe_err(pe, fmt, ...) \ 2427d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 2437d623e42SAlexey Kardashevskiy #define pe_warn(pe, fmt, ...) \ 2447d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 2457d623e42SAlexey Kardashevskiy #define pe_info(pe, fmt, ...) \ 2467d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 2477d623e42SAlexey Kardashevskiy 2485d2aa710SAlistair Popple /* Nvlink functions */ 249f9f83456SAlexey Kardashevskiy extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 2506b3d12a9SAlistair Popple extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 251b5cb9ab1SAlexey Kardashevskiy extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 252b5cb9ab1SAlexey Kardashevskiy extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, 253b5cb9ab1SAlexey Kardashevskiy struct iommu_table *tbl); 254b5cb9ab1SAlexey Kardashevskiy extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num); 255b5cb9ab1SAlexey Kardashevskiy extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe); 256b5cb9ab1SAlexey Kardashevskiy extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe); 2571ab66d1fSAlistair Popple extern int pnv_npu2_init(struct pnv_phb *phb); 2584361b034SIan Munsie 2594361b034SIan Munsie /* cxl functions */ 2604361b034SIan Munsie extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev); 2614361b034SIan Munsie extern void pnv_cxl_disable_device(struct pci_dev *dev); 262a2f67d5eSIan Munsie extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 263a2f67d5eSIan Munsie extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev); 2644361b034SIan Munsie 2654361b034SIan Munsie 2664361b034SIan Munsie /* phb ops (cxl switches these when enabling the kernel api on the phb) */ 2674361b034SIan Munsie extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops; 2684361b034SIan Munsie 26961305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 270