1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
261305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H
361305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H
461305a96SBenjamin Herrenschmidt
51e496391SJoe Perches #include <linux/compiler.h> /* for __printf */
6f456834aSIan Munsie #include <linux/iommu.h>
7f456834aSIan Munsie #include <asm/iommu.h>
8f456834aSIan Munsie #include <asm/msi_bitmap.h>
9f456834aSIan Munsie
1061305a96SBenjamin Herrenschmidt struct pci_dn;
1161305a96SBenjamin Herrenschmidt
1261305a96SBenjamin Herrenschmidt enum pnv_phb_type {
13562d1e20SChristoph Hellwig PNV_PHB_IODA2,
14562d1e20SChristoph Hellwig PNV_PHB_NPU_OCAPI,
1561305a96SBenjamin Herrenschmidt };
1661305a96SBenjamin Herrenschmidt
17cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */
18cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model {
19cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN,
20cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC,
21aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3,
22cee72d5bSBenjamin Herrenschmidt };
23cee72d5bSBenjamin Herrenschmidt
245c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192
257ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
267ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
277ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
28262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
29262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
30781a868fSWei Yang #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
31cee72d5bSBenjamin Herrenschmidt
329d0879a2SOliver O'Halloran /*
339d0879a2SOliver O'Halloran * A brief note on PNV_IODA_PE_BUS_ALL
349d0879a2SOliver O'Halloran *
359d0879a2SOliver O'Halloran * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses
369d0879a2SOliver O'Halloran * the Requester ID field of the PCIe request header to determine the device
379d0879a2SOliver O'Halloran * (and PE) that initiated a DMA. In legacy PCI individual memory read/write
389d0879a2SOliver O'Halloran * requests aren't tagged with the RID. To work around this the PCIe-to-PCI
399d0879a2SOliver O'Halloran * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side.
409d0879a2SOliver O'Halloran *
419d0879a2SOliver O'Halloran * PCIe-to-X bridges have a similar issue even though PCI-X requests also have
429d0879a2SOliver O'Halloran * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take
439d0879a2SOliver O'Halloran * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe
449d0879a2SOliver O'Halloran * side of the bridge.
459d0879a2SOliver O'Halloran *
469d0879a2SOliver O'Halloran * To work around these problems we use the BUS_ALL flag since every subordinate
479d0879a2SOliver O'Halloran * bus of the bridge should go into the same PE.
489d0879a2SOliver O'Halloran */
499d0879a2SOliver O'Halloran
5031bbd45aSRussell Currey /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
5131bbd45aSRussell Currey #define PNV_IODA_STOPPED_STATE 0x8000000000000000
5231bbd45aSRussell Currey
53184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */
544cce9550SGavin Shan struct pnv_phb;
55184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe {
567ebdf956SGavin Shan unsigned long flags;
574cce9550SGavin Shan struct pnv_phb *phb;
58c5f7700bSGavin Shan int device_count;
597ebdf956SGavin Shan
60184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an
61184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev
62184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is.
63184cd4a3SBenjamin Herrenschmidt */
64781a868fSWei Yang #ifdef CONFIG_PCI_IOV
65781a868fSWei Yang struct pci_dev *parent_dev;
66781a868fSWei Yang #endif
67184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev;
68184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus;
69184cd4a3SBenjamin Herrenschmidt
70184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus
71184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE)
72184cd4a3SBenjamin Herrenschmidt */
73184cd4a3SBenjamin Herrenschmidt unsigned int rid;
74184cd4a3SBenjamin Herrenschmidt
75184cd4a3SBenjamin Herrenschmidt /* PE number */
76184cd4a3SBenjamin Herrenschmidt unsigned int pe_number;
77184cd4a3SBenjamin Herrenschmidt
78184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
79b348aa65SAlexey Kardashevskiy struct iommu_table_group table_group;
80184cd4a3SBenjamin Herrenschmidt
81cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */
82cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled;
83cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base;
84184cd4a3SBenjamin Herrenschmidt
8501e12629SOliver O'Halloran /*
8601e12629SOliver O'Halloran * Used to track whether we've done DMA setup for this PE or not. We
8701e12629SOliver O'Halloran * want to defer allocating TCE tables, etc until we've added a
8801e12629SOliver O'Halloran * non-bridge device to the PE.
8901e12629SOliver O'Halloran */
9001e12629SOliver O'Halloran bool dma_setup_done;
9101e12629SOliver O'Halloran
9286052e40SRandy Dunlap /* MSIs. MVE index is identical for 32 and 64 bit MSI
93184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the
94184cd4a3SBenjamin Herrenschmidt * PE number)
95184cd4a3SBenjamin Herrenschmidt */
96184cd4a3SBenjamin Herrenschmidt int mve_number;
97184cd4a3SBenjamin Herrenschmidt
98262af557SGuo Chao /* PEs in compound case */
99262af557SGuo Chao struct pnv_ioda_pe *master;
100262af557SGuo Chao struct list_head slaves;
101262af557SGuo Chao
102184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */
1037ebdf956SGavin Shan struct list_head list;
104184cd4a3SBenjamin Herrenschmidt };
105184cd4a3SBenjamin Herrenschmidt
106f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0)
107f5bc6b70SGavin Shan
10861305a96SBenjamin Herrenschmidt struct pnv_phb {
10961305a96SBenjamin Herrenschmidt struct pci_controller *hose;
11061305a96SBenjamin Herrenschmidt enum pnv_phb_type type;
111cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model;
1128747f363SGavin Shan u64 hub_id;
11361305a96SBenjamin Herrenschmidt u64 opal_id;
114f5bc6b70SGavin Shan int flags;
11561305a96SBenjamin Herrenschmidt void __iomem *regs;
116fd141d1aSBenjamin Herrenschmidt u64 regs_phys;
11761305a96SBenjamin Herrenschmidt spinlock_t lock;
11861305a96SBenjamin Herrenschmidt
11937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS
1207f52a526SGavin Shan int has_dbgfs;
12137c367f2SGavin Shan struct dentry *dbgfs;
12237c367f2SGavin Shan #endif
12337c367f2SGavin Shan
124c1a2562aSBenjamin Herrenschmidt unsigned int msi_base;
125fb1b55d6SGavin Shan struct msi_bitmap msi_bmp;
126262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb);
12749dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
12849dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
12949dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
13061305a96SBenjamin Herrenschmidt
131184cd4a3SBenjamin Herrenschmidt struct {
132184cd4a3SBenjamin Herrenschmidt /* Global bridge info */
13392b8f137SGavin Shan unsigned int total_pe_num;
13492b8f137SGavin Shan unsigned int reserved_pe_idx;
13563803c39SGavin Shan unsigned int root_pe_idx;
136262af557SGuo Chao
137262af557SGuo Chao /* 32-bit MMIO window */
138184cd4a3SBenjamin Herrenschmidt unsigned int m32_size;
139184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize;
140184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base;
141262af557SGuo Chao
142262af557SGuo Chao /* 64-bit MMIO window */
143262af557SGuo Chao unsigned int m64_bar_idx;
144262af557SGuo Chao unsigned long m64_size;
145262af557SGuo Chao unsigned long m64_segsize;
146262af557SGuo Chao unsigned long m64_base;
147ad9add52SOliver O'Halloran #define MAX_M64_BARS 64
148262af557SGuo Chao unsigned long m64_bar_alloc;
149262af557SGuo Chao
150262af557SGuo Chao /* IO ports */
151184cd4a3SBenjamin Herrenschmidt unsigned int io_size;
152184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize;
153184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base;
154184cd4a3SBenjamin Herrenschmidt
15513ce7598SGavin Shan /* PE allocation */
156781a868fSWei Yang struct mutex pe_alloc_mutex;
15713ce7598SGavin Shan unsigned long *pe_alloc;
15813ce7598SGavin Shan struct pnv_ioda_pe *pe_array;
159184cd4a3SBenjamin Herrenschmidt
160184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */
16193289d8cSGavin Shan unsigned int *m64_segmap;
162184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap;
163184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap;
164184cd4a3SBenjamin Herrenschmidt
165137436c9SGavin Shan /* IRQ chip */
166137436c9SGavin Shan int irq_chip_init;
167137436c9SGavin Shan struct irq_chip irq_chip;
168137436c9SGavin Shan
1697ebdf956SGavin Shan /* Sorted list of used PE's based
1707ebdf956SGavin Shan * on the sequence of creation
1717ebdf956SGavin Shan */
1727ebdf956SGavin Shan struct list_head pe_list;
173781a868fSWei Yang struct mutex pe_list_mutex;
1747ebdf956SGavin Shan
175c127562aSGavin Shan /* Reverse map of PEs, indexed by {bus, devfn} */
176c127562aSGavin Shan unsigned int pe_rmap[0x10000];
177184cd4a3SBenjamin Herrenschmidt } ioda;
178cee72d5bSBenjamin Herrenschmidt
1795cb1f8fdSRussell Currey /* PHB and hub diagnostics */
1805cb1f8fdSRussell Currey unsigned int diag_data_size;
1815cb1f8fdSRussell Currey u8 *diag_data;
18261305a96SBenjamin Herrenschmidt };
18361305a96SBenjamin Herrenschmidt
18437b59ef0SOliver O'Halloran
18537b59ef0SOliver O'Halloran /* IODA PE management */
18637b59ef0SOliver O'Halloran
pnv_pci_is_m64(struct pnv_phb * phb,struct resource * r)18737b59ef0SOliver O'Halloran static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
18837b59ef0SOliver O'Halloran {
18937b59ef0SOliver O'Halloran /*
19037b59ef0SOliver O'Halloran * WARNING: We cannot rely on the resource flags. The Linux PCI
19137b59ef0SOliver O'Halloran * allocation code sometimes decides to put a 64-bit prefetchable
19237b59ef0SOliver O'Halloran * BAR in the 32-bit window, so we have to compare the addresses.
19337b59ef0SOliver O'Halloran *
19437b59ef0SOliver O'Halloran * For simplicity we only test resource start.
19537b59ef0SOliver O'Halloran */
19637b59ef0SOliver O'Halloran return (r->start >= phb->ioda.m64_base &&
19737b59ef0SOliver O'Halloran r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
19837b59ef0SOliver O'Halloran }
19937b59ef0SOliver O'Halloran
pnv_pci_is_m64_flags(unsigned long resource_flags)20037b59ef0SOliver O'Halloran static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
20137b59ef0SOliver O'Halloran {
20237b59ef0SOliver O'Halloran unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
20337b59ef0SOliver O'Halloran
20437b59ef0SOliver O'Halloran return (resource_flags & flags) == flags;
20537b59ef0SOliver O'Halloran }
20637b59ef0SOliver O'Halloran
20737b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
20837b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
20937b59ef0SOliver O'Halloran
21037b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
21137b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe);
21237b59ef0SOliver O'Halloran
213a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count);
21437b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe);
21537b59ef0SOliver O'Halloran
21637b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV
21737b59ef0SOliver O'Halloran /*
21837b59ef0SOliver O'Halloran * For SR-IOV we want to put each VF's MMIO resource in to a separate PE.
21937b59ef0SOliver O'Halloran * This requires a bit of acrobatics with the MMIO -> PE configuration
22037b59ef0SOliver O'Halloran * and this structure is used to keep track of it all.
22137b59ef0SOliver O'Halloran */
22237b59ef0SOliver O'Halloran struct pnv_iov_data {
22337b59ef0SOliver O'Halloran /* number of VFs enabled */
22437b59ef0SOliver O'Halloran u16 num_vfs;
225d29a2488SOliver O'Halloran
226052da31dSOliver O'Halloran /* pointer to the array of VF PEs. num_vfs long*/
227d29a2488SOliver O'Halloran struct pnv_ioda_pe *vf_pe_arr;
22837b59ef0SOliver O'Halloran
2294c51f3e1SOliver O'Halloran /* Did we map the VF BAR with single-PE IODA BARs? */
2304c51f3e1SOliver O'Halloran bool m64_single_mode[PCI_SRIOV_NUM_BARS];
2314c51f3e1SOliver O'Halloran
2324c51f3e1SOliver O'Halloran /*
2334c51f3e1SOliver O'Halloran * True if we're using any segmented windows. In that case we need
2344c51f3e1SOliver O'Halloran * shift the start of the IOV resource the segment corresponding to
2354c51f3e1SOliver O'Halloran * the allocated PE.
2364c51f3e1SOliver O'Halloran */
2374c51f3e1SOliver O'Halloran bool need_shift;
23837b59ef0SOliver O'Halloran
239ad9add52SOliver O'Halloran /*
240ad9add52SOliver O'Halloran * Bit mask used to track which m64 windows are used to map the
241ad9add52SOliver O'Halloran * SR-IOV BARs for this device.
242ad9add52SOliver O'Halloran */
243ad9add52SOliver O'Halloran DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS);
24437b59ef0SOliver O'Halloran
24537b59ef0SOliver O'Halloran /*
24637b59ef0SOliver O'Halloran * If we map the SR-IOV BARs with a segmented window then
24737b59ef0SOliver O'Halloran * parts of that window will be "claimed" by other PEs.
24837b59ef0SOliver O'Halloran *
24937b59ef0SOliver O'Halloran * "holes" here is used to reserve the leading portion
25037b59ef0SOliver O'Halloran * of the window that is used by other (non VF) PEs.
25137b59ef0SOliver O'Halloran */
25237b59ef0SOliver O'Halloran struct resource holes[PCI_SRIOV_NUM_BARS];
25337b59ef0SOliver O'Halloran };
25437b59ef0SOliver O'Halloran
pnv_iov_get(struct pci_dev * pdev)25537b59ef0SOliver O'Halloran static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev)
25637b59ef0SOliver O'Halloran {
25737b59ef0SOliver O'Halloran return pdev->dev.archdata.iov_data;
25837b59ef0SOliver O'Halloran }
25937b59ef0SOliver O'Halloran
26037b59ef0SOliver O'Halloran void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev);
26137b59ef0SOliver O'Halloran resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno);
26237b59ef0SOliver O'Halloran
26337b59ef0SOliver O'Halloran int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
26437b59ef0SOliver O'Halloran int pnv_pcibios_sriov_disable(struct pci_dev *pdev);
26537b59ef0SOliver O'Halloran #endif /* CONFIG_PCI_IOV */
26637b59ef0SOliver O'Halloran
26761305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops;
26861305a96SBenjamin Herrenschmidt
26993aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
27093aef2a7SGavin Shan unsigned char *log_buff);
2713532a741SGavin Shan int pnv_pci_cfg_read(struct pci_dn *pdn,
2729bf41be6SGavin Shan int where, int size, u32 *val);
2733532a741SGavin Shan int pnv_pci_cfg_write(struct pci_dn *pdn,
2749bf41be6SGavin Shan int where, int size, u32 val);
2750eaf4defSAlexey Kardashevskiy extern struct iommu_table *pnv_pci_table_alloc(int nid);
2760eaf4defSAlexey Kardashevskiy
277184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np);
278aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np);
2797f2c39e9SFrederic Barrat extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
280d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
281cadf364dSGavin Shan extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
28273ed148aSBenjamin Herrenschmidt
283a8d7d5fcSOliver O'Halloran extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn);
284f456834aSIan Munsie extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
285f456834aSIan Munsie extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
2860bd97167SAlexey Kardashevskiy extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2870bd97167SAlexey Kardashevskiy __u64 window_size, __u32 levels);
288b9fde58dSBenjamin Herrenschmidt extern int pnv_eeh_post_init(void);
28992ae0353SDaniel Axtens
2901e496391SJoe Perches __printf(3, 4)
2917d623e42SAlexey Kardashevskiy extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
2927d623e42SAlexey Kardashevskiy const char *fmt, ...);
2937d623e42SAlexey Kardashevskiy #define pe_err(pe, fmt, ...) \
2947d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
2957d623e42SAlexey Kardashevskiy #define pe_warn(pe, fmt, ...) \
2967d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
2977d623e42SAlexey Kardashevskiy #define pe_info(pe, fmt, ...) \
2987d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
2997d623e42SAlexey Kardashevskiy
300191c2287SAlexey Kardashevskiy /* pci-ioda-tce.c */
301c37c792dSAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 2
302191c2287SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5
303191c2287SAlexey Kardashevskiy
304191c2287SAlexey Kardashevskiy extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
305191c2287SAlexey Kardashevskiy unsigned long uaddr, enum dma_data_direction direction,
306191c2287SAlexey Kardashevskiy unsigned long attrs);
307191c2287SAlexey Kardashevskiy extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
308191c2287SAlexey Kardashevskiy extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
309*cad32d9dSAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction);
310a68bd126SAlexey Kardashevskiy extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index,
311a68bd126SAlexey Kardashevskiy bool alloc);
312191c2287SAlexey Kardashevskiy extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
313191c2287SAlexey Kardashevskiy
314191c2287SAlexey Kardashevskiy extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
315191c2287SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels,
316090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table *tbl);
317191c2287SAlexey Kardashevskiy extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
318191c2287SAlexey Kardashevskiy
319191c2287SAlexey Kardashevskiy extern long pnv_pci_link_table_and_group(int node, int num,
320191c2287SAlexey Kardashevskiy struct iommu_table *tbl,
321191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group);
322191c2287SAlexey Kardashevskiy extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
323191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group);
324191c2287SAlexey Kardashevskiy extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
325191c2287SAlexey Kardashevskiy void *tce_mem, u64 tce_size,
326191c2287SAlexey Kardashevskiy u64 dma_offset, unsigned int page_shift);
327191c2287SAlexey Kardashevskiy
32896e2006aSOliver O'Halloran extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
32996e2006aSOliver O'Halloran
pci_bus_to_pnvhb(struct pci_bus * bus)3305609ffddSOliver O'Halloran static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus)
3315609ffddSOliver O'Halloran {
3325609ffddSOliver O'Halloran struct pci_controller *hose = bus->sysdata;
3335609ffddSOliver O'Halloran
3345609ffddSOliver O'Halloran if (hose)
3355609ffddSOliver O'Halloran return hose->private_data;
3365609ffddSOliver O'Halloran
3375609ffddSOliver O'Halloran return NULL;
3385609ffddSOliver O'Halloran }
3395609ffddSOliver O'Halloran
34061305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */
341