161305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 261305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt 461305a96SBenjamin Herrenschmidt struct pci_dn; 561305a96SBenjamin Herrenschmidt 661305a96SBenjamin Herrenschmidt enum pnv_phb_type { 72de50e96SRussell Currey PNV_PHB_IODA1 = 0, 82de50e96SRussell Currey PNV_PHB_IODA2 = 1, 92de50e96SRussell Currey PNV_PHB_NPU = 2, 1061305a96SBenjamin Herrenschmidt }; 1161305a96SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 13cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 14cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 15cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 16aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 175d2aa710SAlistair Popple PNV_PHB_MODEL_NPU, 18cee72d5bSBenjamin Herrenschmidt }; 19cee72d5bSBenjamin Herrenschmidt 205c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 217ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 227ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 237ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 25262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 26781a868fSWei Yang #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 275d2aa710SAlistair Popple #define PNV_IODA_PE_PEER (1 << 6) /* PE has peers */ 28cee72d5bSBenjamin Herrenschmidt 29184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 304cce9550SGavin Shan struct pnv_phb; 31184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 327ebdf956SGavin Shan unsigned long flags; 334cce9550SGavin Shan struct pnv_phb *phb; 347ebdf956SGavin Shan 355d2aa710SAlistair Popple #define PNV_IODA_MAX_PEER_PES 8 365d2aa710SAlistair Popple struct pnv_ioda_pe *peers[PNV_IODA_MAX_PEER_PES]; 375d2aa710SAlistair Popple 38184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 39184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 40184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 41184cd4a3SBenjamin Herrenschmidt */ 42781a868fSWei Yang #ifdef CONFIG_PCI_IOV 43781a868fSWei Yang struct pci_dev *parent_dev; 44781a868fSWei Yang #endif 45184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 46184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 49184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 50184cd4a3SBenjamin Herrenschmidt */ 51184cd4a3SBenjamin Herrenschmidt unsigned int rid; 52184cd4a3SBenjamin Herrenschmidt 53184cd4a3SBenjamin Herrenschmidt /* PE number */ 54184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 55184cd4a3SBenjamin Herrenschmidt 56184cd4a3SBenjamin Herrenschmidt /* "Weight" assigned to the PE for the sake of DMA resource 57184cd4a3SBenjamin Herrenschmidt * allocations 58184cd4a3SBenjamin Herrenschmidt */ 59184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 60184cd4a3SBenjamin Herrenschmidt 61184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 62184cd4a3SBenjamin Herrenschmidt int tce32_seg; 63184cd4a3SBenjamin Herrenschmidt int tce32_segcount; 64b348aa65SAlexey Kardashevskiy struct iommu_table_group table_group; 65184cd4a3SBenjamin Herrenschmidt 66cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 67cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 68cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 69184cd4a3SBenjamin Herrenschmidt 70184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 71184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 72184cd4a3SBenjamin Herrenschmidt * PE number) 73184cd4a3SBenjamin Herrenschmidt */ 74184cd4a3SBenjamin Herrenschmidt int mve_number; 75184cd4a3SBenjamin Herrenschmidt 76262af557SGuo Chao /* PEs in compound case */ 77262af557SGuo Chao struct pnv_ioda_pe *master; 78262af557SGuo Chao struct list_head slaves; 79262af557SGuo Chao 80184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 817ebdf956SGavin Shan struct list_head dma_link; 827ebdf956SGavin Shan struct list_head list; 83184cd4a3SBenjamin Herrenschmidt }; 84184cd4a3SBenjamin Herrenschmidt 85f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 86f5bc6b70SGavin Shan 8761305a96SBenjamin Herrenschmidt struct pnv_phb { 8861305a96SBenjamin Herrenschmidt struct pci_controller *hose; 8961305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 90cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 918747f363SGavin Shan u64 hub_id; 9261305a96SBenjamin Herrenschmidt u64 opal_id; 93f5bc6b70SGavin Shan int flags; 9461305a96SBenjamin Herrenschmidt void __iomem *regs; 95db1266c8SGavin Shan int initialized; 9661305a96SBenjamin Herrenschmidt spinlock_t lock; 9761305a96SBenjamin Herrenschmidt 9837c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 997f52a526SGavin Shan int has_dbgfs; 10037c367f2SGavin Shan struct dentry *dbgfs; 10137c367f2SGavin Shan #endif 10237c367f2SGavin Shan 103c1a2562aSBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 104c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 105c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 106fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 107c1a2562aSBenjamin Herrenschmidt #endif 108c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 109137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 110137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 11161305a96SBenjamin Herrenschmidt void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 11261305a96SBenjamin Herrenschmidt void (*fixup_phb)(struct pci_controller *hose); 113262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 11496a2f92bSGavin Shan void (*reserve_m64_pe)(struct pci_bus *bus, 11596a2f92bSGavin Shan unsigned long *pe_bitmap, bool all); 116689ee8c9SGavin Shan unsigned int (*pick_m64_pe)(struct pci_bus *bus, bool all); 11749dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 11849dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 11949dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 12061305a96SBenjamin Herrenschmidt 121184cd4a3SBenjamin Herrenschmidt struct { 122184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 12392b8f137SGavin Shan unsigned int total_pe_num; 12492b8f137SGavin Shan unsigned int reserved_pe_idx; 125262af557SGuo Chao 126262af557SGuo Chao /* 32-bit MMIO window */ 127184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 128184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 129184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 130262af557SGuo Chao 131262af557SGuo Chao /* 64-bit MMIO window */ 132262af557SGuo Chao unsigned int m64_bar_idx; 133262af557SGuo Chao unsigned long m64_size; 134262af557SGuo Chao unsigned long m64_segsize; 135262af557SGuo Chao unsigned long m64_base; 136262af557SGuo Chao unsigned long m64_bar_alloc; 137262af557SGuo Chao 138262af557SGuo Chao /* IO ports */ 139184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 140184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 141184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 142184cd4a3SBenjamin Herrenschmidt 14313ce7598SGavin Shan /* PE allocation */ 144781a868fSWei Yang struct mutex pe_alloc_mutex; 14513ce7598SGavin Shan unsigned long *pe_alloc; 14613ce7598SGavin Shan struct pnv_ioda_pe *pe_array; 147184cd4a3SBenjamin Herrenschmidt 148184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 14993289d8cSGavin Shan unsigned int *m64_segmap; 150184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 151184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 152184cd4a3SBenjamin Herrenschmidt 153137436c9SGavin Shan /* IRQ chip */ 154137436c9SGavin Shan int irq_chip_init; 155137436c9SGavin Shan struct irq_chip irq_chip; 156137436c9SGavin Shan 1577ebdf956SGavin Shan /* Sorted list of used PE's based 1587ebdf956SGavin Shan * on the sequence of creation 1597ebdf956SGavin Shan */ 1607ebdf956SGavin Shan struct list_head pe_list; 161781a868fSWei Yang struct mutex pe_list_mutex; 1627ebdf956SGavin Shan 163184cd4a3SBenjamin Herrenschmidt /* Reverse map of PEs, will have to extend if 164184cd4a3SBenjamin Herrenschmidt * we are to support more than 256 PEs, indexed 165184cd4a3SBenjamin Herrenschmidt * bus { bus, devfn } 166184cd4a3SBenjamin Herrenschmidt */ 167184cd4a3SBenjamin Herrenschmidt unsigned char pe_rmap[0x10000]; 168184cd4a3SBenjamin Herrenschmidt 169184cd4a3SBenjamin Herrenschmidt /* 32-bit TCE tables allocation */ 170184cd4a3SBenjamin Herrenschmidt unsigned long tce32_count; 171184cd4a3SBenjamin Herrenschmidt 172184cd4a3SBenjamin Herrenschmidt /* Total "weight" for the sake of DMA resources 173184cd4a3SBenjamin Herrenschmidt * allocation 174184cd4a3SBenjamin Herrenschmidt */ 175184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 176184cd4a3SBenjamin Herrenschmidt unsigned int dma_pe_count; 177184cd4a3SBenjamin Herrenschmidt 178184cd4a3SBenjamin Herrenschmidt /* Sorted list of used PE's, sorted at 179184cd4a3SBenjamin Herrenschmidt * boot for resource allocation purposes 180184cd4a3SBenjamin Herrenschmidt */ 1817ebdf956SGavin Shan struct list_head pe_dma_list; 1825780fb04SAlexey Kardashevskiy 1835780fb04SAlexey Kardashevskiy /* TCE cache invalidate registers (physical and 1845780fb04SAlexey Kardashevskiy * remapped) 1855780fb04SAlexey Kardashevskiy */ 1865780fb04SAlexey Kardashevskiy phys_addr_t tce_inval_reg_phys; 1875780fb04SAlexey Kardashevskiy __be64 __iomem *tce_inval_reg; 188184cd4a3SBenjamin Herrenschmidt } ioda; 189cee72d5bSBenjamin Herrenschmidt 190ca1de5deSBrian W Hart /* PHB and hub status structure */ 191cee72d5bSBenjamin Herrenschmidt union { 192cee72d5bSBenjamin Herrenschmidt unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 193cee72d5bSBenjamin Herrenschmidt struct OpalIoP7IOCPhbErrorData p7ioc; 19493aef2a7SGavin Shan struct OpalIoPhb3ErrorData phb3; 195ca1de5deSBrian W Hart struct OpalIoP7IOCErrorData hub_diag; 196cee72d5bSBenjamin Herrenschmidt } diag; 197ca1de5deSBrian W Hart 19861305a96SBenjamin Herrenschmidt }; 19961305a96SBenjamin Herrenschmidt 20061305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 201da004c36SAlexey Kardashevskiy extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 202da004c36SAlexey Kardashevskiy unsigned long uaddr, enum dma_data_direction direction, 203da004c36SAlexey Kardashevskiy struct dma_attrs *attrs); 204da004c36SAlexey Kardashevskiy extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 20505c6cfb9SAlexey Kardashevskiy extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 20605c6cfb9SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction); 207da004c36SAlexey Kardashevskiy extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 20861305a96SBenjamin Herrenschmidt 20993aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 21093aef2a7SGavin Shan unsigned char *log_buff); 2113532a741SGavin Shan int pnv_pci_cfg_read(struct pci_dn *pdn, 2129bf41be6SGavin Shan int where, int size, u32 *val); 2133532a741SGavin Shan int pnv_pci_cfg_write(struct pci_dn *pdn, 2149bf41be6SGavin Shan int where, int size, u32 val); 2150eaf4defSAlexey Kardashevskiy extern struct iommu_table *pnv_pci_table_alloc(int nid); 2160eaf4defSAlexey Kardashevskiy 2170eaf4defSAlexey Kardashevskiy extern long pnv_pci_link_table_and_group(int node, int num, 2180eaf4defSAlexey Kardashevskiy struct iommu_table *tbl, 2190eaf4defSAlexey Kardashevskiy struct iommu_table_group *table_group); 2200eaf4defSAlexey Kardashevskiy extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 2210eaf4defSAlexey Kardashevskiy struct iommu_table_group *table_group); 22261305a96SBenjamin Herrenschmidt extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 22361305a96SBenjamin Herrenschmidt void *tce_mem, u64 tce_size, 2248fa5d454SAlexey Kardashevskiy u64 dma_offset, unsigned page_shift); 225184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 226aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2275d2aa710SAlistair Popple extern void pnv_pci_init_npu_phb(struct device_node *np); 2284cce9550SGavin Shan extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 2293ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm); 230d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 231cadf364dSGavin Shan extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 23273ed148aSBenjamin Herrenschmidt 23392ae0353SDaniel Axtens extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 2341bc74f1cSGavin Shan extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 23592ae0353SDaniel Axtens extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 23692ae0353SDaniel Axtens extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 23792ae0353SDaniel Axtens 2385d2aa710SAlistair Popple /* Nvlink functions */ 2395d2aa710SAlistair Popple extern void pnv_npu_tce_invalidate_entire(struct pnv_ioda_pe *npe); 2405d2aa710SAlistair Popple extern void pnv_npu_tce_invalidate(struct pnv_ioda_pe *npe, 2415d2aa710SAlistair Popple struct iommu_table *tbl, 2425d2aa710SAlistair Popple unsigned long index, 2435d2aa710SAlistair Popple unsigned long npages, 2445d2aa710SAlistair Popple bool rm); 2455d2aa710SAlistair Popple extern void pnv_npu_init_dma_pe(struct pnv_ioda_pe *npe); 2465d2aa710SAlistair Popple extern void pnv_npu_setup_dma_pe(struct pnv_ioda_pe *npe); 2475d2aa710SAlistair Popple extern int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe, bool enabled); 2485d2aa710SAlistair Popple extern int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask); 2495d2aa710SAlistair Popple 25061305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 251