161305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 261305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt 461305a96SBenjamin Herrenschmidt struct pci_dn; 561305a96SBenjamin Herrenschmidt 661305a96SBenjamin Herrenschmidt enum pnv_phb_type { 7aa0c033fSGavin Shan PNV_PHB_P5IOC2 = 0, 8aa0c033fSGavin Shan PNV_PHB_IODA1 = 1, 9aa0c033fSGavin Shan PNV_PHB_IODA2 = 2, 1061305a96SBenjamin Herrenschmidt }; 1161305a96SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 13cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 14cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 15cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P5IOC2, 16cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 17aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 18cee72d5bSBenjamin Herrenschmidt }; 19cee72d5bSBenjamin Herrenschmidt 205c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 217ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 227ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 237ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 25262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 26781a868fSWei Yang #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 27cee72d5bSBenjamin Herrenschmidt 28184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 294cce9550SGavin Shan struct pnv_phb; 30184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 317ebdf956SGavin Shan unsigned long flags; 324cce9550SGavin Shan struct pnv_phb *phb; 337ebdf956SGavin Shan 34184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 35184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 36184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 37184cd4a3SBenjamin Herrenschmidt */ 38781a868fSWei Yang #ifdef CONFIG_PCI_IOV 39781a868fSWei Yang struct pci_dev *parent_dev; 40781a868fSWei Yang #endif 41184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 42184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 43184cd4a3SBenjamin Herrenschmidt 44184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 45184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 46184cd4a3SBenjamin Herrenschmidt */ 47184cd4a3SBenjamin Herrenschmidt unsigned int rid; 48184cd4a3SBenjamin Herrenschmidt 49184cd4a3SBenjamin Herrenschmidt /* PE number */ 50184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 51184cd4a3SBenjamin Herrenschmidt 52184cd4a3SBenjamin Herrenschmidt /* "Weight" assigned to the PE for the sake of DMA resource 53184cd4a3SBenjamin Herrenschmidt * allocations 54184cd4a3SBenjamin Herrenschmidt */ 55184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 56184cd4a3SBenjamin Herrenschmidt 57184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 58184cd4a3SBenjamin Herrenschmidt int tce32_seg; 59184cd4a3SBenjamin Herrenschmidt int tce32_segcount; 609e8d4a19SWei Yang struct iommu_table *tce32_table; 618e0a1611SAlexey Kardashevskiy phys_addr_t tce_inval_reg_phys; 62184cd4a3SBenjamin Herrenschmidt 63cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 64cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 65cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 66184cd4a3SBenjamin Herrenschmidt 67184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 68184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 69184cd4a3SBenjamin Herrenschmidt * PE number) 70184cd4a3SBenjamin Herrenschmidt */ 71184cd4a3SBenjamin Herrenschmidt int mve_number; 72184cd4a3SBenjamin Herrenschmidt 73262af557SGuo Chao /* PEs in compound case */ 74262af557SGuo Chao struct pnv_ioda_pe *master; 75262af557SGuo Chao struct list_head slaves; 76262af557SGuo Chao 77184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 787ebdf956SGavin Shan struct list_head dma_link; 797ebdf956SGavin Shan struct list_head list; 80184cd4a3SBenjamin Herrenschmidt }; 81184cd4a3SBenjamin Herrenschmidt 82f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 83f5bc6b70SGavin Shan 8461305a96SBenjamin Herrenschmidt struct pnv_phb { 8561305a96SBenjamin Herrenschmidt struct pci_controller *hose; 8661305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 87cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 888747f363SGavin Shan u64 hub_id; 8961305a96SBenjamin Herrenschmidt u64 opal_id; 90f5bc6b70SGavin Shan int flags; 9161305a96SBenjamin Herrenschmidt void __iomem *regs; 92db1266c8SGavin Shan int initialized; 9361305a96SBenjamin Herrenschmidt spinlock_t lock; 9461305a96SBenjamin Herrenschmidt 9537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 967f52a526SGavin Shan int has_dbgfs; 9737c367f2SGavin Shan struct dentry *dbgfs; 9837c367f2SGavin Shan #endif 9937c367f2SGavin Shan 100c1a2562aSBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 101c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 102c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 103fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 104c1a2562aSBenjamin Herrenschmidt #endif 105c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 106137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 107137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 10861305a96SBenjamin Herrenschmidt void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 109cd15b048SBenjamin Herrenschmidt int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev, 110cd15b048SBenjamin Herrenschmidt u64 dma_mask); 111fe7e85c6SGavin Shan u64 (*dma_get_required_mask)(struct pnv_phb *phb, 112fe7e85c6SGavin Shan struct pci_dev *pdev); 11361305a96SBenjamin Herrenschmidt void (*fixup_phb)(struct pci_controller *hose); 11461305a96SBenjamin Herrenschmidt u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 11573ed148aSBenjamin Herrenschmidt void (*shutdown)(struct pnv_phb *phb); 116262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 1175ef73567SGavin Shan void (*reserve_m64_pe)(struct pnv_phb *phb); 118262af557SGuo Chao int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all); 11949dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 12049dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 12149dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 12261305a96SBenjamin Herrenschmidt 12361305a96SBenjamin Herrenschmidt union { 12461305a96SBenjamin Herrenschmidt struct { 12561305a96SBenjamin Herrenschmidt struct iommu_table iommu_table; 12661305a96SBenjamin Herrenschmidt } p5ioc2; 127184cd4a3SBenjamin Herrenschmidt 128184cd4a3SBenjamin Herrenschmidt struct { 129184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 130184cd4a3SBenjamin Herrenschmidt unsigned int total_pe; 13136954dc7SGavin Shan unsigned int reserved_pe; 132262af557SGuo Chao 133262af557SGuo Chao /* 32-bit MMIO window */ 134184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 135184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 136184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 137262af557SGuo Chao 138262af557SGuo Chao /* 64-bit MMIO window */ 139262af557SGuo Chao unsigned int m64_bar_idx; 140262af557SGuo Chao unsigned long m64_size; 141262af557SGuo Chao unsigned long m64_segsize; 142262af557SGuo Chao unsigned long m64_base; 143262af557SGuo Chao unsigned long m64_bar_alloc; 144262af557SGuo Chao 145262af557SGuo Chao /* IO ports */ 146184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 147184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 148184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 149184cd4a3SBenjamin Herrenschmidt 150184cd4a3SBenjamin Herrenschmidt /* PE allocation bitmap */ 151184cd4a3SBenjamin Herrenschmidt unsigned long *pe_alloc; 152781a868fSWei Yang /* PE allocation mutex */ 153781a868fSWei Yang struct mutex pe_alloc_mutex; 154184cd4a3SBenjamin Herrenschmidt 155184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 156184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 157184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 158184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe_array; 159184cd4a3SBenjamin Herrenschmidt 160137436c9SGavin Shan /* IRQ chip */ 161137436c9SGavin Shan int irq_chip_init; 162137436c9SGavin Shan struct irq_chip irq_chip; 163137436c9SGavin Shan 1647ebdf956SGavin Shan /* Sorted list of used PE's based 1657ebdf956SGavin Shan * on the sequence of creation 1667ebdf956SGavin Shan */ 1677ebdf956SGavin Shan struct list_head pe_list; 168781a868fSWei Yang struct mutex pe_list_mutex; 1697ebdf956SGavin Shan 170184cd4a3SBenjamin Herrenschmidt /* Reverse map of PEs, will have to extend if 171184cd4a3SBenjamin Herrenschmidt * we are to support more than 256 PEs, indexed 172184cd4a3SBenjamin Herrenschmidt * bus { bus, devfn } 173184cd4a3SBenjamin Herrenschmidt */ 174184cd4a3SBenjamin Herrenschmidt unsigned char pe_rmap[0x10000]; 175184cd4a3SBenjamin Herrenschmidt 176184cd4a3SBenjamin Herrenschmidt /* 32-bit TCE tables allocation */ 177184cd4a3SBenjamin Herrenschmidt unsigned long tce32_count; 178184cd4a3SBenjamin Herrenschmidt 179184cd4a3SBenjamin Herrenschmidt /* Total "weight" for the sake of DMA resources 180184cd4a3SBenjamin Herrenschmidt * allocation 181184cd4a3SBenjamin Herrenschmidt */ 182184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 183184cd4a3SBenjamin Herrenschmidt unsigned int dma_pe_count; 184184cd4a3SBenjamin Herrenschmidt 185184cd4a3SBenjamin Herrenschmidt /* Sorted list of used PE's, sorted at 186184cd4a3SBenjamin Herrenschmidt * boot for resource allocation purposes 187184cd4a3SBenjamin Herrenschmidt */ 1887ebdf956SGavin Shan struct list_head pe_dma_list; 189184cd4a3SBenjamin Herrenschmidt } ioda; 19061305a96SBenjamin Herrenschmidt }; 191cee72d5bSBenjamin Herrenschmidt 192ca1de5deSBrian W Hart /* PHB and hub status structure */ 193cee72d5bSBenjamin Herrenschmidt union { 194cee72d5bSBenjamin Herrenschmidt unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 195cee72d5bSBenjamin Herrenschmidt struct OpalIoP7IOCPhbErrorData p7ioc; 19693aef2a7SGavin Shan struct OpalIoPhb3ErrorData phb3; 197ca1de5deSBrian W Hart struct OpalIoP7IOCErrorData hub_diag; 198cee72d5bSBenjamin Herrenschmidt } diag; 199ca1de5deSBrian W Hart 20061305a96SBenjamin Herrenschmidt }; 20161305a96SBenjamin Herrenschmidt 20261305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 20361305a96SBenjamin Herrenschmidt 20493aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 20593aef2a7SGavin Shan unsigned char *log_buff); 2063532a741SGavin Shan int pnv_pci_cfg_read(struct pci_dn *pdn, 2079bf41be6SGavin Shan int where, int size, u32 *val); 2083532a741SGavin Shan int pnv_pci_cfg_write(struct pci_dn *pdn, 2099bf41be6SGavin Shan int where, int size, u32 val); 21061305a96SBenjamin Herrenschmidt extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 21161305a96SBenjamin Herrenschmidt void *tce_mem, u64 tce_size, 2128fa5d454SAlexey Kardashevskiy u64 dma_offset, unsigned page_shift); 21361305a96SBenjamin Herrenschmidt extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 214184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 215aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2164cce9550SGavin Shan extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 2173ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm); 218d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 219cadf364dSGavin Shan extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 22073ed148aSBenjamin Herrenschmidt 22161305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 222