161305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 261305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt 461305a96SBenjamin Herrenschmidt struct pci_dn; 561305a96SBenjamin Herrenschmidt 661305a96SBenjamin Herrenschmidt enum pnv_phb_type { 7aa0c033fSGavin Shan PNV_PHB_P5IOC2 = 0, 8aa0c033fSGavin Shan PNV_PHB_IODA1 = 1, 9aa0c033fSGavin Shan PNV_PHB_IODA2 = 2, 1061305a96SBenjamin Herrenschmidt }; 1161305a96SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 13cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 14cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 15cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P5IOC2, 16cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 17aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 18cee72d5bSBenjamin Herrenschmidt }; 19cee72d5bSBenjamin Herrenschmidt 205c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 217ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 227ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 237ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 25262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 26cee72d5bSBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 284cce9550SGavin Shan struct pnv_phb; 29184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 307ebdf956SGavin Shan unsigned long flags; 314cce9550SGavin Shan struct pnv_phb *phb; 327ebdf956SGavin Shan 33184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 34184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 35184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 36184cd4a3SBenjamin Herrenschmidt */ 37184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 38184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 39184cd4a3SBenjamin Herrenschmidt 40184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 41184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 42184cd4a3SBenjamin Herrenschmidt */ 43184cd4a3SBenjamin Herrenschmidt unsigned int rid; 44184cd4a3SBenjamin Herrenschmidt 45184cd4a3SBenjamin Herrenschmidt /* PE number */ 46184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt /* "Weight" assigned to the PE for the sake of DMA resource 49184cd4a3SBenjamin Herrenschmidt * allocations 50184cd4a3SBenjamin Herrenschmidt */ 51184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 52184cd4a3SBenjamin Herrenschmidt 53184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 54184cd4a3SBenjamin Herrenschmidt int tce32_seg; 55184cd4a3SBenjamin Herrenschmidt int tce32_segcount; 56184cd4a3SBenjamin Herrenschmidt struct iommu_table tce32_table; 578e0a1611SAlexey Kardashevskiy phys_addr_t tce_inval_reg_phys; 58184cd4a3SBenjamin Herrenschmidt 59cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 60cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 61cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 62184cd4a3SBenjamin Herrenschmidt 63184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 64184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 65184cd4a3SBenjamin Herrenschmidt * PE number) 66184cd4a3SBenjamin Herrenschmidt */ 67184cd4a3SBenjamin Herrenschmidt int mve_number; 68184cd4a3SBenjamin Herrenschmidt 69262af557SGuo Chao /* PEs in compound case */ 70262af557SGuo Chao struct pnv_ioda_pe *master; 71262af557SGuo Chao struct list_head slaves; 72262af557SGuo Chao 73184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 747ebdf956SGavin Shan struct list_head dma_link; 757ebdf956SGavin Shan struct list_head list; 76184cd4a3SBenjamin Herrenschmidt }; 77184cd4a3SBenjamin Herrenschmidt 788747f363SGavin Shan /* IOC dependent EEH operations */ 798747f363SGavin Shan #ifdef CONFIG_EEH 808747f363SGavin Shan struct pnv_eeh_ops { 818747f363SGavin Shan int (*post_init)(struct pci_controller *hose); 828747f363SGavin Shan int (*set_option)(struct eeh_pe *pe, int option); 838747f363SGavin Shan int (*get_state)(struct eeh_pe *pe); 848747f363SGavin Shan int (*reset)(struct eeh_pe *pe, int option); 858747f363SGavin Shan int (*get_log)(struct eeh_pe *pe, int severity, 868747f363SGavin Shan char *drv_log, unsigned long len); 878747f363SGavin Shan int (*configure_bridge)(struct eeh_pe *pe); 88131c123aSGavin Shan int (*err_inject)(struct eeh_pe *pe, int type, int func, 89131c123aSGavin Shan unsigned long addr, unsigned long mask); 908747f363SGavin Shan int (*next_error)(struct eeh_pe **pe); 918747f363SGavin Shan }; 928747f363SGavin Shan #endif /* CONFIG_EEH */ 938747f363SGavin Shan 94f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 95f5bc6b70SGavin Shan 9661305a96SBenjamin Herrenschmidt struct pnv_phb { 9761305a96SBenjamin Herrenschmidt struct pci_controller *hose; 9861305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 99cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 1008747f363SGavin Shan u64 hub_id; 10161305a96SBenjamin Herrenschmidt u64 opal_id; 102f5bc6b70SGavin Shan int flags; 10361305a96SBenjamin Herrenschmidt void __iomem *regs; 104db1266c8SGavin Shan int initialized; 10561305a96SBenjamin Herrenschmidt spinlock_t lock; 10661305a96SBenjamin Herrenschmidt 1078747f363SGavin Shan #ifdef CONFIG_EEH 1088747f363SGavin Shan struct pnv_eeh_ops *eeh_ops; 1098747f363SGavin Shan #endif 1108747f363SGavin Shan 11137c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 1127f52a526SGavin Shan int has_dbgfs; 11337c367f2SGavin Shan struct dentry *dbgfs; 11437c367f2SGavin Shan #endif 11537c367f2SGavin Shan 116c1a2562aSBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 117c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 118c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 119fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 120c1a2562aSBenjamin Herrenschmidt #endif 121c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 122137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 123137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 12461305a96SBenjamin Herrenschmidt void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 125cd15b048SBenjamin Herrenschmidt int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev, 126cd15b048SBenjamin Herrenschmidt u64 dma_mask); 127fe7e85c6SGavin Shan u64 (*dma_get_required_mask)(struct pnv_phb *phb, 128fe7e85c6SGavin Shan struct pci_dev *pdev); 12961305a96SBenjamin Herrenschmidt void (*fixup_phb)(struct pci_controller *hose); 13061305a96SBenjamin Herrenschmidt u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 13173ed148aSBenjamin Herrenschmidt void (*shutdown)(struct pnv_phb *phb); 132262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 1335ef73567SGavin Shan void (*reserve_m64_pe)(struct pnv_phb *phb); 134262af557SGuo Chao int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all); 13549dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 13649dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 13749dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 13861305a96SBenjamin Herrenschmidt 13961305a96SBenjamin Herrenschmidt union { 14061305a96SBenjamin Herrenschmidt struct { 14161305a96SBenjamin Herrenschmidt struct iommu_table iommu_table; 14261305a96SBenjamin Herrenschmidt } p5ioc2; 143184cd4a3SBenjamin Herrenschmidt 144184cd4a3SBenjamin Herrenschmidt struct { 145184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 146184cd4a3SBenjamin Herrenschmidt unsigned int total_pe; 14736954dc7SGavin Shan unsigned int reserved_pe; 148262af557SGuo Chao 149262af557SGuo Chao /* 32-bit MMIO window */ 150184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 151184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 152184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 153262af557SGuo Chao 154262af557SGuo Chao /* 64-bit MMIO window */ 155262af557SGuo Chao unsigned int m64_bar_idx; 156262af557SGuo Chao unsigned long m64_size; 157262af557SGuo Chao unsigned long m64_segsize; 158262af557SGuo Chao unsigned long m64_base; 159262af557SGuo Chao unsigned long m64_bar_alloc; 160262af557SGuo Chao 161262af557SGuo Chao /* IO ports */ 162184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 163184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 164184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 165184cd4a3SBenjamin Herrenschmidt 166184cd4a3SBenjamin Herrenschmidt /* PE allocation bitmap */ 167184cd4a3SBenjamin Herrenschmidt unsigned long *pe_alloc; 168184cd4a3SBenjamin Herrenschmidt 169184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 170184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 171184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 172184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe_array; 173184cd4a3SBenjamin Herrenschmidt 174137436c9SGavin Shan /* IRQ chip */ 175137436c9SGavin Shan int irq_chip_init; 176137436c9SGavin Shan struct irq_chip irq_chip; 177137436c9SGavin Shan 1787ebdf956SGavin Shan /* Sorted list of used PE's based 1797ebdf956SGavin Shan * on the sequence of creation 1807ebdf956SGavin Shan */ 1817ebdf956SGavin Shan struct list_head pe_list; 1827ebdf956SGavin Shan 183184cd4a3SBenjamin Herrenschmidt /* Reverse map of PEs, will have to extend if 184184cd4a3SBenjamin Herrenschmidt * we are to support more than 256 PEs, indexed 185184cd4a3SBenjamin Herrenschmidt * bus { bus, devfn } 186184cd4a3SBenjamin Herrenschmidt */ 187184cd4a3SBenjamin Herrenschmidt unsigned char pe_rmap[0x10000]; 188184cd4a3SBenjamin Herrenschmidt 189184cd4a3SBenjamin Herrenschmidt /* 32-bit TCE tables allocation */ 190184cd4a3SBenjamin Herrenschmidt unsigned long tce32_count; 191184cd4a3SBenjamin Herrenschmidt 192184cd4a3SBenjamin Herrenschmidt /* Total "weight" for the sake of DMA resources 193184cd4a3SBenjamin Herrenschmidt * allocation 194184cd4a3SBenjamin Herrenschmidt */ 195184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 196184cd4a3SBenjamin Herrenschmidt unsigned int dma_pe_count; 197184cd4a3SBenjamin Herrenschmidt 198184cd4a3SBenjamin Herrenschmidt /* Sorted list of used PE's, sorted at 199184cd4a3SBenjamin Herrenschmidt * boot for resource allocation purposes 200184cd4a3SBenjamin Herrenschmidt */ 2017ebdf956SGavin Shan struct list_head pe_dma_list; 202184cd4a3SBenjamin Herrenschmidt } ioda; 20361305a96SBenjamin Herrenschmidt }; 204cee72d5bSBenjamin Herrenschmidt 205ca1de5deSBrian W Hart /* PHB and hub status structure */ 206cee72d5bSBenjamin Herrenschmidt union { 207cee72d5bSBenjamin Herrenschmidt unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 208cee72d5bSBenjamin Herrenschmidt struct OpalIoP7IOCPhbErrorData p7ioc; 20993aef2a7SGavin Shan struct OpalIoPhb3ErrorData phb3; 210ca1de5deSBrian W Hart struct OpalIoP7IOCErrorData hub_diag; 211cee72d5bSBenjamin Herrenschmidt } diag; 212ca1de5deSBrian W Hart 21361305a96SBenjamin Herrenschmidt }; 21461305a96SBenjamin Herrenschmidt 21561305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 2168747f363SGavin Shan #ifdef CONFIG_EEH 2178747f363SGavin Shan extern struct pnv_eeh_ops ioda_eeh_ops; 2188747f363SGavin Shan #endif 21961305a96SBenjamin Herrenschmidt 22093aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 22193aef2a7SGavin Shan unsigned char *log_buff); 2229bf41be6SGavin Shan int pnv_pci_cfg_read(struct device_node *dn, 2239bf41be6SGavin Shan int where, int size, u32 *val); 2249bf41be6SGavin Shan int pnv_pci_cfg_write(struct device_node *dn, 2259bf41be6SGavin Shan int where, int size, u32 val); 22661305a96SBenjamin Herrenschmidt extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 22761305a96SBenjamin Herrenschmidt void *tce_mem, u64 tce_size, 2288fa5d454SAlexey Kardashevskiy u64 dma_offset, unsigned page_shift); 22961305a96SBenjamin Herrenschmidt extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 230184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 231aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2324cce9550SGavin Shan extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 2333ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm); 234d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 235361f2a2aSGavin Shan extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option); 23673ed148aSBenjamin Herrenschmidt 23761305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 238