1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 261305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 461305a96SBenjamin Herrenschmidt 51e496391SJoe Perches #include <linux/compiler.h> /* for __printf */ 6f456834aSIan Munsie #include <linux/iommu.h> 7f456834aSIan Munsie #include <asm/iommu.h> 8f456834aSIan Munsie #include <asm/msi_bitmap.h> 9f456834aSIan Munsie 1061305a96SBenjamin Herrenschmidt struct pci_dn; 1161305a96SBenjamin Herrenschmidt 1261305a96SBenjamin Herrenschmidt enum pnv_phb_type { 132de50e96SRussell Currey PNV_PHB_IODA1 = 0, 142de50e96SRussell Currey PNV_PHB_IODA2 = 1, 157f2c39e9SFrederic Barrat PNV_PHB_NPU_NVLINK = 2, 167f2c39e9SFrederic Barrat PNV_PHB_NPU_OCAPI = 3, 1761305a96SBenjamin Herrenschmidt }; 1861305a96SBenjamin Herrenschmidt 19cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 20cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 21cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 22cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 23aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 245d2aa710SAlistair Popple PNV_PHB_MODEL_NPU, 25616badd2SAlistair Popple PNV_PHB_MODEL_NPU2, 26cee72d5bSBenjamin Herrenschmidt }; 27cee72d5bSBenjamin Herrenschmidt 285c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 297ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 307ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 317ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34781a868fSWei Yang #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35cee72d5bSBenjamin Herrenschmidt 369d0879a2SOliver O'Halloran /* 379d0879a2SOliver O'Halloran * A brief note on PNV_IODA_PE_BUS_ALL 389d0879a2SOliver O'Halloran * 399d0879a2SOliver O'Halloran * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses 409d0879a2SOliver O'Halloran * the Requester ID field of the PCIe request header to determine the device 419d0879a2SOliver O'Halloran * (and PE) that initiated a DMA. In legacy PCI individual memory read/write 429d0879a2SOliver O'Halloran * requests aren't tagged with the RID. To work around this the PCIe-to-PCI 439d0879a2SOliver O'Halloran * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side. 449d0879a2SOliver O'Halloran * 459d0879a2SOliver O'Halloran * PCIe-to-X bridges have a similar issue even though PCI-X requests also have 469d0879a2SOliver O'Halloran * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take 479d0879a2SOliver O'Halloran * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe 489d0879a2SOliver O'Halloran * side of the bridge. 499d0879a2SOliver O'Halloran * 509d0879a2SOliver O'Halloran * To work around these problems we use the BUS_ALL flag since every subordinate 519d0879a2SOliver O'Halloran * bus of the bridge should go into the same PE. 529d0879a2SOliver O'Halloran */ 539d0879a2SOliver O'Halloran 5431bbd45aSRussell Currey /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 5531bbd45aSRussell Currey #define PNV_IODA_STOPPED_STATE 0x8000000000000000 5631bbd45aSRussell Currey 57184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 584cce9550SGavin Shan struct pnv_phb; 59184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 607ebdf956SGavin Shan unsigned long flags; 614cce9550SGavin Shan struct pnv_phb *phb; 62c5f7700bSGavin Shan int device_count; 637ebdf956SGavin Shan 64184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 65184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 66184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 67184cd4a3SBenjamin Herrenschmidt */ 68781a868fSWei Yang #ifdef CONFIG_PCI_IOV 69781a868fSWei Yang struct pci_dev *parent_dev; 70781a868fSWei Yang #endif 71184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 72184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 73184cd4a3SBenjamin Herrenschmidt 74184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 75184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 76184cd4a3SBenjamin Herrenschmidt */ 77184cd4a3SBenjamin Herrenschmidt unsigned int rid; 78184cd4a3SBenjamin Herrenschmidt 79184cd4a3SBenjamin Herrenschmidt /* PE number */ 80184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 81184cd4a3SBenjamin Herrenschmidt 82184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 83b348aa65SAlexey Kardashevskiy struct iommu_table_group table_group; 840bd97167SAlexey Kardashevskiy struct npu_comp *npucomp; 85184cd4a3SBenjamin Herrenschmidt 86cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 87cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 88cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 89184cd4a3SBenjamin Herrenschmidt 90184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 91184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 92184cd4a3SBenjamin Herrenschmidt * PE number) 93184cd4a3SBenjamin Herrenschmidt */ 94184cd4a3SBenjamin Herrenschmidt int mve_number; 95184cd4a3SBenjamin Herrenschmidt 96262af557SGuo Chao /* PEs in compound case */ 97262af557SGuo Chao struct pnv_ioda_pe *master; 98262af557SGuo Chao struct list_head slaves; 99262af557SGuo Chao 100184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 1017ebdf956SGavin Shan struct list_head list; 102184cd4a3SBenjamin Herrenschmidt }; 103184cd4a3SBenjamin Herrenschmidt 104f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 105f5bc6b70SGavin Shan 10661305a96SBenjamin Herrenschmidt struct pnv_phb { 10761305a96SBenjamin Herrenschmidt struct pci_controller *hose; 10861305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 109cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 1108747f363SGavin Shan u64 hub_id; 11161305a96SBenjamin Herrenschmidt u64 opal_id; 112f5bc6b70SGavin Shan int flags; 11361305a96SBenjamin Herrenschmidt void __iomem *regs; 114fd141d1aSBenjamin Herrenschmidt u64 regs_phys; 115db1266c8SGavin Shan int initialized; 11661305a96SBenjamin Herrenschmidt spinlock_t lock; 11761305a96SBenjamin Herrenschmidt 11837c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 1197f52a526SGavin Shan int has_dbgfs; 12037c367f2SGavin Shan struct dentry *dbgfs; 12137c367f2SGavin Shan #endif 12237c367f2SGavin Shan 123c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 124c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 125fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 126c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 127137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 128137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 129262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 13049dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 13149dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 13249dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 13361305a96SBenjamin Herrenschmidt 134184cd4a3SBenjamin Herrenschmidt struct { 135184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 13692b8f137SGavin Shan unsigned int total_pe_num; 13792b8f137SGavin Shan unsigned int reserved_pe_idx; 13863803c39SGavin Shan unsigned int root_pe_idx; 139262af557SGuo Chao 140262af557SGuo Chao /* 32-bit MMIO window */ 141184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 142184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 143184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 144262af557SGuo Chao 145262af557SGuo Chao /* 64-bit MMIO window */ 146262af557SGuo Chao unsigned int m64_bar_idx; 147262af557SGuo Chao unsigned long m64_size; 148262af557SGuo Chao unsigned long m64_segsize; 149262af557SGuo Chao unsigned long m64_base; 150262af557SGuo Chao unsigned long m64_bar_alloc; 151262af557SGuo Chao 152262af557SGuo Chao /* IO ports */ 153184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 154184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 155184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 156184cd4a3SBenjamin Herrenschmidt 15713ce7598SGavin Shan /* PE allocation */ 158781a868fSWei Yang struct mutex pe_alloc_mutex; 15913ce7598SGavin Shan unsigned long *pe_alloc; 16013ce7598SGavin Shan struct pnv_ioda_pe *pe_array; 161184cd4a3SBenjamin Herrenschmidt 162184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 16393289d8cSGavin Shan unsigned int *m64_segmap; 164184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 165184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 166184cd4a3SBenjamin Herrenschmidt 1672b923ed1SGavin Shan /* DMA32 segment maps - IODA1 only */ 1682b923ed1SGavin Shan unsigned int dma32_count; 1692b923ed1SGavin Shan unsigned int *dma32_segmap; 1702b923ed1SGavin Shan 171137436c9SGavin Shan /* IRQ chip */ 172137436c9SGavin Shan int irq_chip_init; 173137436c9SGavin Shan struct irq_chip irq_chip; 174137436c9SGavin Shan 1757ebdf956SGavin Shan /* Sorted list of used PE's based 1767ebdf956SGavin Shan * on the sequence of creation 1777ebdf956SGavin Shan */ 1787ebdf956SGavin Shan struct list_head pe_list; 179781a868fSWei Yang struct mutex pe_list_mutex; 1807ebdf956SGavin Shan 181c127562aSGavin Shan /* Reverse map of PEs, indexed by {bus, devfn} */ 182c127562aSGavin Shan unsigned int pe_rmap[0x10000]; 183184cd4a3SBenjamin Herrenschmidt } ioda; 184cee72d5bSBenjamin Herrenschmidt 1855cb1f8fdSRussell Currey /* PHB and hub diagnostics */ 1865cb1f8fdSRussell Currey unsigned int diag_data_size; 1875cb1f8fdSRussell Currey u8 *diag_data; 18861305a96SBenjamin Herrenschmidt }; 18961305a96SBenjamin Herrenschmidt 19061305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 19161305a96SBenjamin Herrenschmidt 19293aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 19393aef2a7SGavin Shan unsigned char *log_buff); 1943532a741SGavin Shan int pnv_pci_cfg_read(struct pci_dn *pdn, 1959bf41be6SGavin Shan int where, int size, u32 *val); 1963532a741SGavin Shan int pnv_pci_cfg_write(struct pci_dn *pdn, 1979bf41be6SGavin Shan int where, int size, u32 val); 1980eaf4defSAlexey Kardashevskiy extern struct iommu_table *pnv_pci_table_alloc(int nid); 1990eaf4defSAlexey Kardashevskiy 200184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 201aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2025d2aa710SAlistair Popple extern void pnv_pci_init_npu_phb(struct device_node *np); 2037f2c39e9SFrederic Barrat extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 2040e759bd7SAlexey Kardashevskiy extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr); 205d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 206cadf364dSGavin Shan extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 20773ed148aSBenjamin Herrenschmidt 20892ae0353SDaniel Axtens extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 20992ae0353SDaniel Axtens extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 210a8d7d5fcSOliver O'Halloran extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn); 211f456834aSIan Munsie extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 212f456834aSIan Munsie extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 2130bd97167SAlexey Kardashevskiy extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 2140bd97167SAlexey Kardashevskiy __u64 window_size, __u32 levels); 215b9fde58dSBenjamin Herrenschmidt extern int pnv_eeh_post_init(void); 21692ae0353SDaniel Axtens 2171e496391SJoe Perches __printf(3, 4) 2187d623e42SAlexey Kardashevskiy extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 2197d623e42SAlexey Kardashevskiy const char *fmt, ...); 2207d623e42SAlexey Kardashevskiy #define pe_err(pe, fmt, ...) \ 2217d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 2227d623e42SAlexey Kardashevskiy #define pe_warn(pe, fmt, ...) \ 2237d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 2247d623e42SAlexey Kardashevskiy #define pe_info(pe, fmt, ...) \ 2257d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 2267d623e42SAlexey Kardashevskiy 2275d2aa710SAlistair Popple /* Nvlink functions */ 228f9f83456SAlexey Kardashevskiy extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 2296b3d12a9SAlistair Popple extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 23003b7bf34SOliver O'Halloran extern void pnv_pci_npu_setup_iommu_groups(void); 2314361b034SIan Munsie 232191c2287SAlexey Kardashevskiy /* pci-ioda-tce.c */ 233c37c792dSAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 2 234191c2287SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 235191c2287SAlexey Kardashevskiy 236191c2287SAlexey Kardashevskiy extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 237191c2287SAlexey Kardashevskiy unsigned long uaddr, enum dma_data_direction direction, 238191c2287SAlexey Kardashevskiy unsigned long attrs); 239191c2287SAlexey Kardashevskiy extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 240191c2287SAlexey Kardashevskiy extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 241a68bd126SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 242a68bd126SAlexey Kardashevskiy bool alloc); 243a68bd126SAlexey Kardashevskiy extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 244a68bd126SAlexey Kardashevskiy bool alloc); 245191c2287SAlexey Kardashevskiy extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 246191c2287SAlexey Kardashevskiy 247191c2287SAlexey Kardashevskiy extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 248191c2287SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 249090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table *tbl); 250191c2287SAlexey Kardashevskiy extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 251191c2287SAlexey Kardashevskiy 252191c2287SAlexey Kardashevskiy extern long pnv_pci_link_table_and_group(int node, int num, 253191c2287SAlexey Kardashevskiy struct iommu_table *tbl, 254191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group); 255191c2287SAlexey Kardashevskiy extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 256191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group); 257191c2287SAlexey Kardashevskiy extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 258191c2287SAlexey Kardashevskiy void *tce_mem, u64 tce_size, 259191c2287SAlexey Kardashevskiy u64 dma_offset, unsigned int page_shift); 260191c2287SAlexey Kardashevskiy 26196e2006aSOliver O'Halloran extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 26296e2006aSOliver O'Halloran 2635609ffddSOliver O'Halloran static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus) 2645609ffddSOliver O'Halloran { 2655609ffddSOliver O'Halloran struct pci_controller *hose = bus->sysdata; 2665609ffddSOliver O'Halloran 2675609ffddSOliver O'Halloran if (hose) 2685609ffddSOliver O'Halloran return hose->private_data; 2695609ffddSOliver O'Halloran 2705609ffddSOliver O'Halloran return NULL; 2715609ffddSOliver O'Halloran } 2725609ffddSOliver O'Halloran 27361305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 274