161305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 261305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt 461305a96SBenjamin Herrenschmidt struct pci_dn; 561305a96SBenjamin Herrenschmidt 661305a96SBenjamin Herrenschmidt enum pnv_phb_type { 7aa0c033fSGavin Shan PNV_PHB_P5IOC2 = 0, 8aa0c033fSGavin Shan PNV_PHB_IODA1 = 1, 9aa0c033fSGavin Shan PNV_PHB_IODA2 = 2, 1061305a96SBenjamin Herrenschmidt }; 1161305a96SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 13cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 14cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 15cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P5IOC2, 16cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 17aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 18cee72d5bSBenjamin Herrenschmidt }; 19cee72d5bSBenjamin Herrenschmidt 205c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 217ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 227ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 237ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 25262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 26cee72d5bSBenjamin Herrenschmidt 27184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 284cce9550SGavin Shan struct pnv_phb; 29184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 307ebdf956SGavin Shan unsigned long flags; 314cce9550SGavin Shan struct pnv_phb *phb; 327ebdf956SGavin Shan 33184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 34184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 35184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 36184cd4a3SBenjamin Herrenschmidt */ 37184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 38184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 39184cd4a3SBenjamin Herrenschmidt 40184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 41184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 42184cd4a3SBenjamin Herrenschmidt */ 43184cd4a3SBenjamin Herrenschmidt unsigned int rid; 44184cd4a3SBenjamin Herrenschmidt 45184cd4a3SBenjamin Herrenschmidt /* PE number */ 46184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 47184cd4a3SBenjamin Herrenschmidt 48184cd4a3SBenjamin Herrenschmidt /* "Weight" assigned to the PE for the sake of DMA resource 49184cd4a3SBenjamin Herrenschmidt * allocations 50184cd4a3SBenjamin Herrenschmidt */ 51184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 52184cd4a3SBenjamin Herrenschmidt 53184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 54184cd4a3SBenjamin Herrenschmidt int tce32_seg; 55184cd4a3SBenjamin Herrenschmidt int tce32_segcount; 56184cd4a3SBenjamin Herrenschmidt struct iommu_table tce32_table; 578e0a1611SAlexey Kardashevskiy phys_addr_t tce_inval_reg_phys; 58184cd4a3SBenjamin Herrenschmidt 59cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 60cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 61cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 62184cd4a3SBenjamin Herrenschmidt 63184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 64184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 65184cd4a3SBenjamin Herrenschmidt * PE number) 66184cd4a3SBenjamin Herrenschmidt */ 67184cd4a3SBenjamin Herrenschmidt int mve_number; 68184cd4a3SBenjamin Herrenschmidt 69262af557SGuo Chao /* PEs in compound case */ 70262af557SGuo Chao struct pnv_ioda_pe *master; 71262af557SGuo Chao struct list_head slaves; 72262af557SGuo Chao 73184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 747ebdf956SGavin Shan struct list_head dma_link; 757ebdf956SGavin Shan struct list_head list; 76184cd4a3SBenjamin Herrenschmidt }; 77184cd4a3SBenjamin Herrenschmidt 788747f363SGavin Shan /* IOC dependent EEH operations */ 798747f363SGavin Shan #ifdef CONFIG_EEH 808747f363SGavin Shan struct pnv_eeh_ops { 818747f363SGavin Shan int (*post_init)(struct pci_controller *hose); 828747f363SGavin Shan int (*set_option)(struct eeh_pe *pe, int option); 838747f363SGavin Shan int (*get_state)(struct eeh_pe *pe); 848747f363SGavin Shan int (*reset)(struct eeh_pe *pe, int option); 858747f363SGavin Shan int (*get_log)(struct eeh_pe *pe, int severity, 868747f363SGavin Shan char *drv_log, unsigned long len); 878747f363SGavin Shan int (*configure_bridge)(struct eeh_pe *pe); 888747f363SGavin Shan int (*next_error)(struct eeh_pe **pe); 898747f363SGavin Shan }; 908747f363SGavin Shan #endif /* CONFIG_EEH */ 918747f363SGavin Shan 92f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 93f5bc6b70SGavin Shan 9461305a96SBenjamin Herrenschmidt struct pnv_phb { 9561305a96SBenjamin Herrenschmidt struct pci_controller *hose; 9661305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 97cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 988747f363SGavin Shan u64 hub_id; 9961305a96SBenjamin Herrenschmidt u64 opal_id; 100f5bc6b70SGavin Shan int flags; 10161305a96SBenjamin Herrenschmidt void __iomem *regs; 102db1266c8SGavin Shan int initialized; 10361305a96SBenjamin Herrenschmidt spinlock_t lock; 10461305a96SBenjamin Herrenschmidt 1058747f363SGavin Shan #ifdef CONFIG_EEH 1068747f363SGavin Shan struct pnv_eeh_ops *eeh_ops; 1078747f363SGavin Shan #endif 1088747f363SGavin Shan 10937c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 1107f52a526SGavin Shan int has_dbgfs; 11137c367f2SGavin Shan struct dentry *dbgfs; 11237c367f2SGavin Shan #endif 11337c367f2SGavin Shan 114c1a2562aSBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 115c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 116c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 117fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 118c1a2562aSBenjamin Herrenschmidt #endif 119c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 120137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 121137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 12261305a96SBenjamin Herrenschmidt void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 123cd15b048SBenjamin Herrenschmidt int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev, 124cd15b048SBenjamin Herrenschmidt u64 dma_mask); 12561305a96SBenjamin Herrenschmidt void (*fixup_phb)(struct pci_controller *hose); 12661305a96SBenjamin Herrenschmidt u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 12773ed148aSBenjamin Herrenschmidt void (*shutdown)(struct pnv_phb *phb); 128262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 129262af557SGuo Chao void (*alloc_m64_pe)(struct pnv_phb *phb); 130262af557SGuo Chao int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all); 13149dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 13249dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 13349dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 13461305a96SBenjamin Herrenschmidt 13561305a96SBenjamin Herrenschmidt union { 13661305a96SBenjamin Herrenschmidt struct { 13761305a96SBenjamin Herrenschmidt struct iommu_table iommu_table; 13861305a96SBenjamin Herrenschmidt } p5ioc2; 139184cd4a3SBenjamin Herrenschmidt 140184cd4a3SBenjamin Herrenschmidt struct { 141184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 142184cd4a3SBenjamin Herrenschmidt unsigned int total_pe; 14336954dc7SGavin Shan unsigned int reserved_pe; 144262af557SGuo Chao 145262af557SGuo Chao /* 32-bit MMIO window */ 146184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 147184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 148184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 149262af557SGuo Chao 150262af557SGuo Chao /* 64-bit MMIO window */ 151262af557SGuo Chao unsigned int m64_bar_idx; 152262af557SGuo Chao unsigned long m64_size; 153262af557SGuo Chao unsigned long m64_segsize; 154262af557SGuo Chao unsigned long m64_base; 155262af557SGuo Chao unsigned long m64_bar_alloc; 156262af557SGuo Chao 157262af557SGuo Chao /* IO ports */ 158184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 159184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 160184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 161184cd4a3SBenjamin Herrenschmidt 162184cd4a3SBenjamin Herrenschmidt /* PE allocation bitmap */ 163184cd4a3SBenjamin Herrenschmidt unsigned long *pe_alloc; 164184cd4a3SBenjamin Herrenschmidt 165184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 166184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 167184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 168184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe_array; 169184cd4a3SBenjamin Herrenschmidt 170137436c9SGavin Shan /* IRQ chip */ 171137436c9SGavin Shan int irq_chip_init; 172137436c9SGavin Shan struct irq_chip irq_chip; 173137436c9SGavin Shan 1747ebdf956SGavin Shan /* Sorted list of used PE's based 1757ebdf956SGavin Shan * on the sequence of creation 1767ebdf956SGavin Shan */ 1777ebdf956SGavin Shan struct list_head pe_list; 1787ebdf956SGavin Shan 179184cd4a3SBenjamin Herrenschmidt /* Reverse map of PEs, will have to extend if 180184cd4a3SBenjamin Herrenschmidt * we are to support more than 256 PEs, indexed 181184cd4a3SBenjamin Herrenschmidt * bus { bus, devfn } 182184cd4a3SBenjamin Herrenschmidt */ 183184cd4a3SBenjamin Herrenschmidt unsigned char pe_rmap[0x10000]; 184184cd4a3SBenjamin Herrenschmidt 185184cd4a3SBenjamin Herrenschmidt /* 32-bit TCE tables allocation */ 186184cd4a3SBenjamin Herrenschmidt unsigned long tce32_count; 187184cd4a3SBenjamin Herrenschmidt 188184cd4a3SBenjamin Herrenschmidt /* Total "weight" for the sake of DMA resources 189184cd4a3SBenjamin Herrenschmidt * allocation 190184cd4a3SBenjamin Herrenschmidt */ 191184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 192184cd4a3SBenjamin Herrenschmidt unsigned int dma_pe_count; 193184cd4a3SBenjamin Herrenschmidt 194184cd4a3SBenjamin Herrenschmidt /* Sorted list of used PE's, sorted at 195184cd4a3SBenjamin Herrenschmidt * boot for resource allocation purposes 196184cd4a3SBenjamin Herrenschmidt */ 1977ebdf956SGavin Shan struct list_head pe_dma_list; 198184cd4a3SBenjamin Herrenschmidt } ioda; 19961305a96SBenjamin Herrenschmidt }; 200cee72d5bSBenjamin Herrenschmidt 201ca1de5deSBrian W Hart /* PHB and hub status structure */ 202cee72d5bSBenjamin Herrenschmidt union { 203cee72d5bSBenjamin Herrenschmidt unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 204cee72d5bSBenjamin Herrenschmidt struct OpalIoP7IOCPhbErrorData p7ioc; 20593aef2a7SGavin Shan struct OpalIoPhb3ErrorData phb3; 206ca1de5deSBrian W Hart struct OpalIoP7IOCErrorData hub_diag; 207cee72d5bSBenjamin Herrenschmidt } diag; 208ca1de5deSBrian W Hart 20961305a96SBenjamin Herrenschmidt }; 21061305a96SBenjamin Herrenschmidt 21161305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 2128747f363SGavin Shan #ifdef CONFIG_EEH 2138747f363SGavin Shan extern struct pnv_eeh_ops ioda_eeh_ops; 2148747f363SGavin Shan #endif 21561305a96SBenjamin Herrenschmidt 21693aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 21793aef2a7SGavin Shan unsigned char *log_buff); 2189bf41be6SGavin Shan int pnv_pci_cfg_read(struct device_node *dn, 2199bf41be6SGavin Shan int where, int size, u32 *val); 2209bf41be6SGavin Shan int pnv_pci_cfg_write(struct device_node *dn, 2219bf41be6SGavin Shan int where, int size, u32 val); 22261305a96SBenjamin Herrenschmidt extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 22361305a96SBenjamin Herrenschmidt void *tce_mem, u64 tce_size, 2248fa5d454SAlexey Kardashevskiy u64 dma_offset, unsigned page_shift); 22561305a96SBenjamin Herrenschmidt extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 226184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 227aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2284cce9550SGavin Shan extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 2293ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm); 230d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 231361f2a2aSGavin Shan extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option); 23273ed148aSBenjamin Herrenschmidt 23361305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 234