161305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 261305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt 461305a96SBenjamin Herrenschmidt struct pci_dn; 561305a96SBenjamin Herrenschmidt 661305a96SBenjamin Herrenschmidt enum pnv_phb_type { 7aa0c033fSGavin Shan PNV_PHB_P5IOC2 = 0, 8aa0c033fSGavin Shan PNV_PHB_IODA1 = 1, 9aa0c033fSGavin Shan PNV_PHB_IODA2 = 2, 1061305a96SBenjamin Herrenschmidt }; 1161305a96SBenjamin Herrenschmidt 12cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 13cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 14cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 15cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P5IOC2, 16cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 17aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 18cee72d5bSBenjamin Herrenschmidt }; 19cee72d5bSBenjamin Herrenschmidt 205c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 217ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 227ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 237ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24cee72d5bSBenjamin Herrenschmidt 25184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 264cce9550SGavin Shan struct pnv_phb; 27184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 287ebdf956SGavin Shan unsigned long flags; 294cce9550SGavin Shan struct pnv_phb *phb; 307ebdf956SGavin Shan 31184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 32184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 33184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 34184cd4a3SBenjamin Herrenschmidt */ 35184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 36184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 37184cd4a3SBenjamin Herrenschmidt 38184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 39184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 40184cd4a3SBenjamin Herrenschmidt */ 41184cd4a3SBenjamin Herrenschmidt unsigned int rid; 42184cd4a3SBenjamin Herrenschmidt 43184cd4a3SBenjamin Herrenschmidt /* PE number */ 44184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 45184cd4a3SBenjamin Herrenschmidt 46184cd4a3SBenjamin Herrenschmidt /* "Weight" assigned to the PE for the sake of DMA resource 47184cd4a3SBenjamin Herrenschmidt * allocations 48184cd4a3SBenjamin Herrenschmidt */ 49184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 50184cd4a3SBenjamin Herrenschmidt 51184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 52184cd4a3SBenjamin Herrenschmidt int tce32_seg; 53184cd4a3SBenjamin Herrenschmidt int tce32_segcount; 54184cd4a3SBenjamin Herrenschmidt struct iommu_table tce32_table; 558e0a1611SAlexey Kardashevskiy phys_addr_t tce_inval_reg_phys; 56184cd4a3SBenjamin Herrenschmidt 57184cd4a3SBenjamin Herrenschmidt /* XXX TODO: Add support for additional 64-bit iommus */ 58184cd4a3SBenjamin Herrenschmidt 59184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 60184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 61184cd4a3SBenjamin Herrenschmidt * PE number) 62184cd4a3SBenjamin Herrenschmidt */ 63184cd4a3SBenjamin Herrenschmidt int mve_number; 64184cd4a3SBenjamin Herrenschmidt 65184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 667ebdf956SGavin Shan struct list_head dma_link; 677ebdf956SGavin Shan struct list_head list; 68184cd4a3SBenjamin Herrenschmidt }; 69184cd4a3SBenjamin Herrenschmidt 708747f363SGavin Shan /* IOC dependent EEH operations */ 718747f363SGavin Shan #ifdef CONFIG_EEH 728747f363SGavin Shan struct pnv_eeh_ops { 738747f363SGavin Shan int (*post_init)(struct pci_controller *hose); 748747f363SGavin Shan int (*set_option)(struct eeh_pe *pe, int option); 758747f363SGavin Shan int (*get_state)(struct eeh_pe *pe); 768747f363SGavin Shan int (*reset)(struct eeh_pe *pe, int option); 778747f363SGavin Shan int (*get_log)(struct eeh_pe *pe, int severity, 788747f363SGavin Shan char *drv_log, unsigned long len); 798747f363SGavin Shan int (*configure_bridge)(struct eeh_pe *pe); 808747f363SGavin Shan int (*next_error)(struct eeh_pe **pe); 818747f363SGavin Shan }; 820b9e267dSGavin Shan 830b9e267dSGavin Shan #define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */ 840b9e267dSGavin Shan #define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */ 850b9e267dSGavin Shan 868747f363SGavin Shan #endif /* CONFIG_EEH */ 878747f363SGavin Shan 8861305a96SBenjamin Herrenschmidt struct pnv_phb { 8961305a96SBenjamin Herrenschmidt struct pci_controller *hose; 9061305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 91cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 928747f363SGavin Shan u64 hub_id; 9361305a96SBenjamin Herrenschmidt u64 opal_id; 9461305a96SBenjamin Herrenschmidt void __iomem *regs; 95db1266c8SGavin Shan int initialized; 9661305a96SBenjamin Herrenschmidt spinlock_t lock; 9761305a96SBenjamin Herrenschmidt 988747f363SGavin Shan #ifdef CONFIG_EEH 998747f363SGavin Shan struct pnv_eeh_ops *eeh_ops; 1000b9e267dSGavin Shan int eeh_state; 1018747f363SGavin Shan #endif 1028747f363SGavin Shan 10337c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 10437c367f2SGavin Shan struct dentry *dbgfs; 10537c367f2SGavin Shan #endif 10637c367f2SGavin Shan 107c1a2562aSBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 108c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 109c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 110fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 111c1a2562aSBenjamin Herrenschmidt #endif 112c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 113137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 114137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 11561305a96SBenjamin Herrenschmidt void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 11661305a96SBenjamin Herrenschmidt void (*fixup_phb)(struct pci_controller *hose); 11761305a96SBenjamin Herrenschmidt u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 11873ed148aSBenjamin Herrenschmidt void (*shutdown)(struct pnv_phb *phb); 11961305a96SBenjamin Herrenschmidt 12061305a96SBenjamin Herrenschmidt union { 12161305a96SBenjamin Herrenschmidt struct { 12261305a96SBenjamin Herrenschmidt struct iommu_table iommu_table; 12361305a96SBenjamin Herrenschmidt } p5ioc2; 124184cd4a3SBenjamin Herrenschmidt 125184cd4a3SBenjamin Herrenschmidt struct { 126184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 127184cd4a3SBenjamin Herrenschmidt unsigned int total_pe; 12836954dc7SGavin Shan unsigned int reserved_pe; 129184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 130184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 131184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 132184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 133184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 134184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 135184cd4a3SBenjamin Herrenschmidt 136184cd4a3SBenjamin Herrenschmidt /* PE allocation bitmap */ 137184cd4a3SBenjamin Herrenschmidt unsigned long *pe_alloc; 138184cd4a3SBenjamin Herrenschmidt 139184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 140184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 141184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 142184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe *pe_array; 143184cd4a3SBenjamin Herrenschmidt 144137436c9SGavin Shan /* IRQ chip */ 145137436c9SGavin Shan int irq_chip_init; 146137436c9SGavin Shan struct irq_chip irq_chip; 147137436c9SGavin Shan 1487ebdf956SGavin Shan /* Sorted list of used PE's based 1497ebdf956SGavin Shan * on the sequence of creation 1507ebdf956SGavin Shan */ 1517ebdf956SGavin Shan struct list_head pe_list; 1527ebdf956SGavin Shan 153184cd4a3SBenjamin Herrenschmidt /* Reverse map of PEs, will have to extend if 154184cd4a3SBenjamin Herrenschmidt * we are to support more than 256 PEs, indexed 155184cd4a3SBenjamin Herrenschmidt * bus { bus, devfn } 156184cd4a3SBenjamin Herrenschmidt */ 157184cd4a3SBenjamin Herrenschmidt unsigned char pe_rmap[0x10000]; 158184cd4a3SBenjamin Herrenschmidt 159184cd4a3SBenjamin Herrenschmidt /* 32-bit TCE tables allocation */ 160184cd4a3SBenjamin Herrenschmidt unsigned long tce32_count; 161184cd4a3SBenjamin Herrenschmidt 162184cd4a3SBenjamin Herrenschmidt /* Total "weight" for the sake of DMA resources 163184cd4a3SBenjamin Herrenschmidt * allocation 164184cd4a3SBenjamin Herrenschmidt */ 165184cd4a3SBenjamin Herrenschmidt unsigned int dma_weight; 166184cd4a3SBenjamin Herrenschmidt unsigned int dma_pe_count; 167184cd4a3SBenjamin Herrenschmidt 168184cd4a3SBenjamin Herrenschmidt /* Sorted list of used PE's, sorted at 169184cd4a3SBenjamin Herrenschmidt * boot for resource allocation purposes 170184cd4a3SBenjamin Herrenschmidt */ 1717ebdf956SGavin Shan struct list_head pe_dma_list; 172184cd4a3SBenjamin Herrenschmidt } ioda; 17361305a96SBenjamin Herrenschmidt }; 174cee72d5bSBenjamin Herrenschmidt 175cee72d5bSBenjamin Herrenschmidt /* PHB status structure */ 176cee72d5bSBenjamin Herrenschmidt union { 177cee72d5bSBenjamin Herrenschmidt unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 178cee72d5bSBenjamin Herrenschmidt struct OpalIoP7IOCPhbErrorData p7ioc; 179cee72d5bSBenjamin Herrenschmidt } diag; 18061305a96SBenjamin Herrenschmidt }; 18161305a96SBenjamin Herrenschmidt 18261305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 1838747f363SGavin Shan #ifdef CONFIG_EEH 1848747f363SGavin Shan extern struct pnv_eeh_ops ioda_eeh_ops; 1858747f363SGavin Shan #endif 18661305a96SBenjamin Herrenschmidt 1879bf41be6SGavin Shan int pnv_pci_cfg_read(struct device_node *dn, 1889bf41be6SGavin Shan int where, int size, u32 *val); 1899bf41be6SGavin Shan int pnv_pci_cfg_write(struct device_node *dn, 1909bf41be6SGavin Shan int where, int size, u32 val); 19161305a96SBenjamin Herrenschmidt extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 19261305a96SBenjamin Herrenschmidt void *tce_mem, u64 tce_size, 19361305a96SBenjamin Herrenschmidt u64 dma_offset); 19461305a96SBenjamin Herrenschmidt extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 195184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 196aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 1974cce9550SGavin Shan extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 1983ad26e5cSBenjamin Herrenschmidt __be64 *startp, __be64 *endp, bool rm); 19973ed148aSBenjamin Herrenschmidt 20061305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 201