1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 261305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 461305a96SBenjamin Herrenschmidt 5f456834aSIan Munsie #include <linux/iommu.h> 6f456834aSIan Munsie #include <asm/iommu.h> 7f456834aSIan Munsie #include <asm/msi_bitmap.h> 8f456834aSIan Munsie 961305a96SBenjamin Herrenschmidt struct pci_dn; 1061305a96SBenjamin Herrenschmidt 111ab66d1fSAlistair Popple /* Maximum possible number of ATSD MMIO registers per NPU */ 121ab66d1fSAlistair Popple #define NV_NMMU_ATSD_REGS 8 131ab66d1fSAlistair Popple 1461305a96SBenjamin Herrenschmidt enum pnv_phb_type { 152de50e96SRussell Currey PNV_PHB_IODA1 = 0, 162de50e96SRussell Currey PNV_PHB_IODA2 = 1, 177f2c39e9SFrederic Barrat PNV_PHB_NPU_NVLINK = 2, 187f2c39e9SFrederic Barrat PNV_PHB_NPU_OCAPI = 3, 1961305a96SBenjamin Herrenschmidt }; 2061305a96SBenjamin Herrenschmidt 21cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 22cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 23cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 24cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 25aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 265d2aa710SAlistair Popple PNV_PHB_MODEL_NPU, 27616badd2SAlistair Popple PNV_PHB_MODEL_NPU2, 28cee72d5bSBenjamin Herrenschmidt }; 29cee72d5bSBenjamin Herrenschmidt 305c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 317ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 327ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 337ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 34262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 35262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 36781a868fSWei Yang #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 37cee72d5bSBenjamin Herrenschmidt 3831bbd45aSRussell Currey /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 3931bbd45aSRussell Currey #define PNV_IODA_STOPPED_STATE 0x8000000000000000 4031bbd45aSRussell Currey 41184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 424cce9550SGavin Shan struct pnv_phb; 43184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 447ebdf956SGavin Shan unsigned long flags; 454cce9550SGavin Shan struct pnv_phb *phb; 46c5f7700bSGavin Shan int device_count; 477ebdf956SGavin Shan 48184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 49184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 50184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 51184cd4a3SBenjamin Herrenschmidt */ 52781a868fSWei Yang #ifdef CONFIG_PCI_IOV 53781a868fSWei Yang struct pci_dev *parent_dev; 54781a868fSWei Yang #endif 55184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 56184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 57184cd4a3SBenjamin Herrenschmidt 58184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 59184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 60184cd4a3SBenjamin Herrenschmidt */ 61184cd4a3SBenjamin Herrenschmidt unsigned int rid; 62184cd4a3SBenjamin Herrenschmidt 63184cd4a3SBenjamin Herrenschmidt /* PE number */ 64184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 65184cd4a3SBenjamin Herrenschmidt 66184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 67b348aa65SAlexey Kardashevskiy struct iommu_table_group table_group; 68184cd4a3SBenjamin Herrenschmidt 69cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 70cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 71cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 72184cd4a3SBenjamin Herrenschmidt 73184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 74184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 75184cd4a3SBenjamin Herrenschmidt * PE number) 76184cd4a3SBenjamin Herrenschmidt */ 77184cd4a3SBenjamin Herrenschmidt int mve_number; 78184cd4a3SBenjamin Herrenschmidt 79262af557SGuo Chao /* PEs in compound case */ 80262af557SGuo Chao struct pnv_ioda_pe *master; 81262af557SGuo Chao struct list_head slaves; 82262af557SGuo Chao 8325529100SFrederic Barrat /* PCI peer-to-peer*/ 8425529100SFrederic Barrat int p2p_initiator_count; 8525529100SFrederic Barrat 86184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 877ebdf956SGavin Shan struct list_head list; 88184cd4a3SBenjamin Herrenschmidt }; 89184cd4a3SBenjamin Herrenschmidt 90f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 914361b034SIan Munsie #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */ 92f5bc6b70SGavin Shan 9361305a96SBenjamin Herrenschmidt struct pnv_phb { 9461305a96SBenjamin Herrenschmidt struct pci_controller *hose; 9561305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 96cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 978747f363SGavin Shan u64 hub_id; 9861305a96SBenjamin Herrenschmidt u64 opal_id; 99f5bc6b70SGavin Shan int flags; 10061305a96SBenjamin Herrenschmidt void __iomem *regs; 101fd141d1aSBenjamin Herrenschmidt u64 regs_phys; 102db1266c8SGavin Shan int initialized; 10361305a96SBenjamin Herrenschmidt spinlock_t lock; 10461305a96SBenjamin Herrenschmidt 10537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 1067f52a526SGavin Shan int has_dbgfs; 10737c367f2SGavin Shan struct dentry *dbgfs; 10837c367f2SGavin Shan #endif 10937c367f2SGavin Shan 110c1a2562aSBenjamin Herrenschmidt #ifdef CONFIG_PCI_MSI 111c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 112c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 113fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 114c1a2562aSBenjamin Herrenschmidt #endif 115c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 116137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 117137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 11861305a96SBenjamin Herrenschmidt void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 11961305a96SBenjamin Herrenschmidt void (*fixup_phb)(struct pci_controller *hose); 120262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 12196a2f92bSGavin Shan void (*reserve_m64_pe)(struct pci_bus *bus, 12296a2f92bSGavin Shan unsigned long *pe_bitmap, bool all); 1231e916772SGavin Shan struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all); 12449dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 12549dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 12649dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 12761305a96SBenjamin Herrenschmidt 128184cd4a3SBenjamin Herrenschmidt struct { 129184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 13092b8f137SGavin Shan unsigned int total_pe_num; 13192b8f137SGavin Shan unsigned int reserved_pe_idx; 13263803c39SGavin Shan unsigned int root_pe_idx; 13363803c39SGavin Shan bool root_pe_populated; 134262af557SGuo Chao 135262af557SGuo Chao /* 32-bit MMIO window */ 136184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 137184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 138184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 139262af557SGuo Chao 140262af557SGuo Chao /* 64-bit MMIO window */ 141262af557SGuo Chao unsigned int m64_bar_idx; 142262af557SGuo Chao unsigned long m64_size; 143262af557SGuo Chao unsigned long m64_segsize; 144262af557SGuo Chao unsigned long m64_base; 145262af557SGuo Chao unsigned long m64_bar_alloc; 146262af557SGuo Chao 147262af557SGuo Chao /* IO ports */ 148184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 149184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 150184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 151184cd4a3SBenjamin Herrenschmidt 15213ce7598SGavin Shan /* PE allocation */ 153781a868fSWei Yang struct mutex pe_alloc_mutex; 15413ce7598SGavin Shan unsigned long *pe_alloc; 15513ce7598SGavin Shan struct pnv_ioda_pe *pe_array; 156184cd4a3SBenjamin Herrenschmidt 157184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 15893289d8cSGavin Shan unsigned int *m64_segmap; 159184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 160184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 161184cd4a3SBenjamin Herrenschmidt 1622b923ed1SGavin Shan /* DMA32 segment maps - IODA1 only */ 1632b923ed1SGavin Shan unsigned int dma32_count; 1642b923ed1SGavin Shan unsigned int *dma32_segmap; 1652b923ed1SGavin Shan 166137436c9SGavin Shan /* IRQ chip */ 167137436c9SGavin Shan int irq_chip_init; 168137436c9SGavin Shan struct irq_chip irq_chip; 169137436c9SGavin Shan 1707ebdf956SGavin Shan /* Sorted list of used PE's based 1717ebdf956SGavin Shan * on the sequence of creation 1727ebdf956SGavin Shan */ 1737ebdf956SGavin Shan struct list_head pe_list; 174781a868fSWei Yang struct mutex pe_list_mutex; 1757ebdf956SGavin Shan 176c127562aSGavin Shan /* Reverse map of PEs, indexed by {bus, devfn} */ 177c127562aSGavin Shan unsigned int pe_rmap[0x10000]; 178184cd4a3SBenjamin Herrenschmidt } ioda; 179cee72d5bSBenjamin Herrenschmidt 1805cb1f8fdSRussell Currey /* PHB and hub diagnostics */ 1815cb1f8fdSRussell Currey unsigned int diag_data_size; 1825cb1f8fdSRussell Currey u8 *diag_data; 183ca1de5deSBrian W Hart 1841ab66d1fSAlistair Popple /* Nvlink2 data */ 1851ab66d1fSAlistair Popple struct npu { 1861ab66d1fSAlistair Popple int index; 1871ab66d1fSAlistair Popple __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS]; 1881ab66d1fSAlistair Popple unsigned int mmio_atsd_count; 1891ab66d1fSAlistair Popple 1901ab66d1fSAlistair Popple /* Bitmask for MMIO register usage */ 1911ab66d1fSAlistair Popple unsigned long mmio_atsd_usage; 1921b2c2b12SAlistair Popple 1931b2c2b12SAlistair Popple /* Do we need to explicitly flush the nest mmu? */ 1941b2c2b12SAlistair Popple bool nmmu_flush; 1951ab66d1fSAlistair Popple } npu; 1961ab66d1fSAlistair Popple 1974361b034SIan Munsie #ifdef CONFIG_CXL_BASE 1984361b034SIan Munsie struct cxl_afu *cxl_afu; 1994361b034SIan Munsie #endif 20025529100SFrederic Barrat int p2p_target_count; 20161305a96SBenjamin Herrenschmidt }; 20261305a96SBenjamin Herrenschmidt 20361305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 20461305a96SBenjamin Herrenschmidt 20593aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 20693aef2a7SGavin Shan unsigned char *log_buff); 2073532a741SGavin Shan int pnv_pci_cfg_read(struct pci_dn *pdn, 2089bf41be6SGavin Shan int where, int size, u32 *val); 2093532a741SGavin Shan int pnv_pci_cfg_write(struct pci_dn *pdn, 2109bf41be6SGavin Shan int where, int size, u32 val); 2110eaf4defSAlexey Kardashevskiy extern struct iommu_table *pnv_pci_table_alloc(int nid); 2120eaf4defSAlexey Kardashevskiy 213184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 214aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2155d2aa710SAlistair Popple extern void pnv_pci_init_npu_phb(struct device_node *np); 2167f2c39e9SFrederic Barrat extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 217d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 218cadf364dSGavin Shan extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 21973ed148aSBenjamin Herrenschmidt 22092ae0353SDaniel Axtens extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 2211bc74f1cSGavin Shan extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 22292ae0353SDaniel Axtens extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 22392ae0353SDaniel Axtens extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 224f456834aSIan Munsie extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 225f456834aSIan Munsie extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 2264361b034SIan Munsie extern bool pnv_pci_enable_device_hook(struct pci_dev *dev); 22725529100SFrederic Barrat extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); 228b9fde58dSBenjamin Herrenschmidt extern int pnv_eeh_post_init(void); 22992ae0353SDaniel Axtens 2307d623e42SAlexey Kardashevskiy extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 2317d623e42SAlexey Kardashevskiy const char *fmt, ...); 2327d623e42SAlexey Kardashevskiy #define pe_err(pe, fmt, ...) \ 2337d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 2347d623e42SAlexey Kardashevskiy #define pe_warn(pe, fmt, ...) \ 2357d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 2367d623e42SAlexey Kardashevskiy #define pe_info(pe, fmt, ...) \ 2377d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 2387d623e42SAlexey Kardashevskiy 2395d2aa710SAlistair Popple /* Nvlink functions */ 240f9f83456SAlexey Kardashevskiy extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 2416b3d12a9SAlistair Popple extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 242b5cb9ab1SAlexey Kardashevskiy extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe); 243b5cb9ab1SAlexey Kardashevskiy extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num, 244b5cb9ab1SAlexey Kardashevskiy struct iommu_table *tbl); 245b5cb9ab1SAlexey Kardashevskiy extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num); 246b5cb9ab1SAlexey Kardashevskiy extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe); 247b5cb9ab1SAlexey Kardashevskiy extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe); 2481ab66d1fSAlistair Popple extern int pnv_npu2_init(struct pnv_phb *phb); 2494361b034SIan Munsie 2504361b034SIan Munsie /* cxl functions */ 2514361b034SIan Munsie extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev); 2524361b034SIan Munsie extern void pnv_cxl_disable_device(struct pci_dev *dev); 253a2f67d5eSIan Munsie extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 254a2f67d5eSIan Munsie extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev); 2554361b034SIan Munsie 2564361b034SIan Munsie 2574361b034SIan Munsie /* phb ops (cxl switches these when enabling the kernel api on the phb) */ 2584361b034SIan Munsie extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops; 2594361b034SIan Munsie 260191c2287SAlexey Kardashevskiy /* pci-ioda-tce.c */ 261191c2287SAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 1 262191c2287SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 263191c2287SAlexey Kardashevskiy 264191c2287SAlexey Kardashevskiy extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 265191c2287SAlexey Kardashevskiy unsigned long uaddr, enum dma_data_direction direction, 266191c2287SAlexey Kardashevskiy unsigned long attrs); 267191c2287SAlexey Kardashevskiy extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 268191c2287SAlexey Kardashevskiy extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 269191c2287SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction); 270090bad39SAlexey Kardashevskiy extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index); 271191c2287SAlexey Kardashevskiy extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 272191c2287SAlexey Kardashevskiy 273191c2287SAlexey Kardashevskiy extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 274191c2287SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 275090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table *tbl); 276191c2287SAlexey Kardashevskiy extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 277191c2287SAlexey Kardashevskiy 278191c2287SAlexey Kardashevskiy extern long pnv_pci_link_table_and_group(int node, int num, 279191c2287SAlexey Kardashevskiy struct iommu_table *tbl, 280191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group); 281191c2287SAlexey Kardashevskiy extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 282191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group); 283191c2287SAlexey Kardashevskiy extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 284191c2287SAlexey Kardashevskiy void *tce_mem, u64 tce_size, 285191c2287SAlexey Kardashevskiy u64 dma_offset, unsigned int page_shift); 286191c2287SAlexey Kardashevskiy 28761305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 288