1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 261305a96SBenjamin Herrenschmidt #ifndef __POWERNV_PCI_H 361305a96SBenjamin Herrenschmidt #define __POWERNV_PCI_H 461305a96SBenjamin Herrenschmidt 51e496391SJoe Perches #include <linux/compiler.h> /* for __printf */ 6f456834aSIan Munsie #include <linux/iommu.h> 7f456834aSIan Munsie #include <asm/iommu.h> 8f456834aSIan Munsie #include <asm/msi_bitmap.h> 9f456834aSIan Munsie 1061305a96SBenjamin Herrenschmidt struct pci_dn; 1161305a96SBenjamin Herrenschmidt 1261305a96SBenjamin Herrenschmidt enum pnv_phb_type { 132de50e96SRussell Currey PNV_PHB_IODA1 = 0, 142de50e96SRussell Currey PNV_PHB_IODA2 = 1, 157f2c39e9SFrederic Barrat PNV_PHB_NPU_NVLINK = 2, 167f2c39e9SFrederic Barrat PNV_PHB_NPU_OCAPI = 3, 1761305a96SBenjamin Herrenschmidt }; 1861305a96SBenjamin Herrenschmidt 19cee72d5bSBenjamin Herrenschmidt /* Precise PHB model for error management */ 20cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model { 21cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_UNKNOWN, 22cee72d5bSBenjamin Herrenschmidt PNV_PHB_MODEL_P7IOC, 23aa0c033fSGavin Shan PNV_PHB_MODEL_PHB3, 245d2aa710SAlistair Popple PNV_PHB_MODEL_NPU, 25616badd2SAlistair Popple PNV_PHB_MODEL_NPU2, 26cee72d5bSBenjamin Herrenschmidt }; 27cee72d5bSBenjamin Herrenschmidt 285c9d6d75SGavin Shan #define PNV_PCI_DIAG_BUF_SIZE 8192 297ebdf956SGavin Shan #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 307ebdf956SGavin Shan #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 317ebdf956SGavin Shan #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 32262af557SGuo Chao #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 33262af557SGuo Chao #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 34781a868fSWei Yang #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 35cee72d5bSBenjamin Herrenschmidt 369d0879a2SOliver O'Halloran /* 379d0879a2SOliver O'Halloran * A brief note on PNV_IODA_PE_BUS_ALL 389d0879a2SOliver O'Halloran * 399d0879a2SOliver O'Halloran * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses 409d0879a2SOliver O'Halloran * the Requester ID field of the PCIe request header to determine the device 419d0879a2SOliver O'Halloran * (and PE) that initiated a DMA. In legacy PCI individual memory read/write 429d0879a2SOliver O'Halloran * requests aren't tagged with the RID. To work around this the PCIe-to-PCI 439d0879a2SOliver O'Halloran * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side. 449d0879a2SOliver O'Halloran * 459d0879a2SOliver O'Halloran * PCIe-to-X bridges have a similar issue even though PCI-X requests also have 469d0879a2SOliver O'Halloran * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take 479d0879a2SOliver O'Halloran * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe 489d0879a2SOliver O'Halloran * side of the bridge. 499d0879a2SOliver O'Halloran * 509d0879a2SOliver O'Halloran * To work around these problems we use the BUS_ALL flag since every subordinate 519d0879a2SOliver O'Halloran * bus of the bridge should go into the same PE. 529d0879a2SOliver O'Halloran */ 539d0879a2SOliver O'Halloran 5431bbd45aSRussell Currey /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */ 5531bbd45aSRussell Currey #define PNV_IODA_STOPPED_STATE 0x8000000000000000 5631bbd45aSRussell Currey 57184cd4a3SBenjamin Herrenschmidt /* Data associated with a PE, including IOMMU tracking etc.. */ 584cce9550SGavin Shan struct pnv_phb; 59184cd4a3SBenjamin Herrenschmidt struct pnv_ioda_pe { 607ebdf956SGavin Shan unsigned long flags; 614cce9550SGavin Shan struct pnv_phb *phb; 62c5f7700bSGavin Shan int device_count; 637ebdf956SGavin Shan 64184cd4a3SBenjamin Herrenschmidt /* A PE can be associated with a single device or an 65184cd4a3SBenjamin Herrenschmidt * entire bus (& children). In the former case, pdev 66184cd4a3SBenjamin Herrenschmidt * is populated, in the later case, pbus is. 67184cd4a3SBenjamin Herrenschmidt */ 68781a868fSWei Yang #ifdef CONFIG_PCI_IOV 69781a868fSWei Yang struct pci_dev *parent_dev; 70781a868fSWei Yang #endif 71184cd4a3SBenjamin Herrenschmidt struct pci_dev *pdev; 72184cd4a3SBenjamin Herrenschmidt struct pci_bus *pbus; 73184cd4a3SBenjamin Herrenschmidt 74184cd4a3SBenjamin Herrenschmidt /* Effective RID (device RID for a device PE and base bus 75184cd4a3SBenjamin Herrenschmidt * RID with devfn 0 for a bus PE) 76184cd4a3SBenjamin Herrenschmidt */ 77184cd4a3SBenjamin Herrenschmidt unsigned int rid; 78184cd4a3SBenjamin Herrenschmidt 79184cd4a3SBenjamin Herrenschmidt /* PE number */ 80184cd4a3SBenjamin Herrenschmidt unsigned int pe_number; 81184cd4a3SBenjamin Herrenschmidt 82184cd4a3SBenjamin Herrenschmidt /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 83b348aa65SAlexey Kardashevskiy struct iommu_table_group table_group; 840bd97167SAlexey Kardashevskiy struct npu_comp *npucomp; 85184cd4a3SBenjamin Herrenschmidt 86cd15b048SBenjamin Herrenschmidt /* 64-bit TCE bypass region */ 87cd15b048SBenjamin Herrenschmidt bool tce_bypass_enabled; 88cd15b048SBenjamin Herrenschmidt uint64_t tce_bypass_base; 89184cd4a3SBenjamin Herrenschmidt 9001e12629SOliver O'Halloran /* 9101e12629SOliver O'Halloran * Used to track whether we've done DMA setup for this PE or not. We 9201e12629SOliver O'Halloran * want to defer allocating TCE tables, etc until we've added a 9301e12629SOliver O'Halloran * non-bridge device to the PE. 9401e12629SOliver O'Halloran */ 9501e12629SOliver O'Halloran bool dma_setup_done; 9601e12629SOliver O'Halloran 97184cd4a3SBenjamin Herrenschmidt /* MSIs. MVE index is identical for for 32 and 64 bit MSI 98184cd4a3SBenjamin Herrenschmidt * and -1 if not supported. (It's actually identical to the 99184cd4a3SBenjamin Herrenschmidt * PE number) 100184cd4a3SBenjamin Herrenschmidt */ 101184cd4a3SBenjamin Herrenschmidt int mve_number; 102184cd4a3SBenjamin Herrenschmidt 103262af557SGuo Chao /* PEs in compound case */ 104262af557SGuo Chao struct pnv_ioda_pe *master; 105262af557SGuo Chao struct list_head slaves; 106262af557SGuo Chao 107184cd4a3SBenjamin Herrenschmidt /* Link in list of PE#s */ 1087ebdf956SGavin Shan struct list_head list; 109184cd4a3SBenjamin Herrenschmidt }; 110184cd4a3SBenjamin Herrenschmidt 111f5bc6b70SGavin Shan #define PNV_PHB_FLAG_EEH (1 << 0) 112f5bc6b70SGavin Shan 11361305a96SBenjamin Herrenschmidt struct pnv_phb { 11461305a96SBenjamin Herrenschmidt struct pci_controller *hose; 11561305a96SBenjamin Herrenschmidt enum pnv_phb_type type; 116cee72d5bSBenjamin Herrenschmidt enum pnv_phb_model model; 1178747f363SGavin Shan u64 hub_id; 11861305a96SBenjamin Herrenschmidt u64 opal_id; 119f5bc6b70SGavin Shan int flags; 12061305a96SBenjamin Herrenschmidt void __iomem *regs; 121fd141d1aSBenjamin Herrenschmidt u64 regs_phys; 122db1266c8SGavin Shan int initialized; 12361305a96SBenjamin Herrenschmidt spinlock_t lock; 12461305a96SBenjamin Herrenschmidt 12537c367f2SGavin Shan #ifdef CONFIG_DEBUG_FS 1267f52a526SGavin Shan int has_dbgfs; 12737c367f2SGavin Shan struct dentry *dbgfs; 12837c367f2SGavin Shan #endif 12937c367f2SGavin Shan 130c1a2562aSBenjamin Herrenschmidt unsigned int msi_base; 131c1a2562aSBenjamin Herrenschmidt unsigned int msi32_support; 132fb1b55d6SGavin Shan struct msi_bitmap msi_bmp; 133c1a2562aSBenjamin Herrenschmidt int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 134137436c9SGavin Shan unsigned int hwirq, unsigned int virq, 135137436c9SGavin Shan unsigned int is_64, struct msi_msg *msg); 136262af557SGuo Chao int (*init_m64)(struct pnv_phb *phb); 13749dec922SGavin Shan int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 13849dec922SGavin Shan void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 13949dec922SGavin Shan int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 14061305a96SBenjamin Herrenschmidt 141184cd4a3SBenjamin Herrenschmidt struct { 142184cd4a3SBenjamin Herrenschmidt /* Global bridge info */ 14392b8f137SGavin Shan unsigned int total_pe_num; 14492b8f137SGavin Shan unsigned int reserved_pe_idx; 14563803c39SGavin Shan unsigned int root_pe_idx; 146262af557SGuo Chao 147262af557SGuo Chao /* 32-bit MMIO window */ 148184cd4a3SBenjamin Herrenschmidt unsigned int m32_size; 149184cd4a3SBenjamin Herrenschmidt unsigned int m32_segsize; 150184cd4a3SBenjamin Herrenschmidt unsigned int m32_pci_base; 151262af557SGuo Chao 152262af557SGuo Chao /* 64-bit MMIO window */ 153262af557SGuo Chao unsigned int m64_bar_idx; 154262af557SGuo Chao unsigned long m64_size; 155262af557SGuo Chao unsigned long m64_segsize; 156262af557SGuo Chao unsigned long m64_base; 157ad9add52SOliver O'Halloran #define MAX_M64_BARS 64 158262af557SGuo Chao unsigned long m64_bar_alloc; 159262af557SGuo Chao 160262af557SGuo Chao /* IO ports */ 161184cd4a3SBenjamin Herrenschmidt unsigned int io_size; 162184cd4a3SBenjamin Herrenschmidt unsigned int io_segsize; 163184cd4a3SBenjamin Herrenschmidt unsigned int io_pci_base; 164184cd4a3SBenjamin Herrenschmidt 16513ce7598SGavin Shan /* PE allocation */ 166781a868fSWei Yang struct mutex pe_alloc_mutex; 16713ce7598SGavin Shan unsigned long *pe_alloc; 16813ce7598SGavin Shan struct pnv_ioda_pe *pe_array; 169184cd4a3SBenjamin Herrenschmidt 170184cd4a3SBenjamin Herrenschmidt /* M32 & IO segment maps */ 17193289d8cSGavin Shan unsigned int *m64_segmap; 172184cd4a3SBenjamin Herrenschmidt unsigned int *m32_segmap; 173184cd4a3SBenjamin Herrenschmidt unsigned int *io_segmap; 174184cd4a3SBenjamin Herrenschmidt 1752b923ed1SGavin Shan /* DMA32 segment maps - IODA1 only */ 1762b923ed1SGavin Shan unsigned int dma32_count; 1772b923ed1SGavin Shan unsigned int *dma32_segmap; 1782b923ed1SGavin Shan 179137436c9SGavin Shan /* IRQ chip */ 180137436c9SGavin Shan int irq_chip_init; 181137436c9SGavin Shan struct irq_chip irq_chip; 182137436c9SGavin Shan 1837ebdf956SGavin Shan /* Sorted list of used PE's based 1847ebdf956SGavin Shan * on the sequence of creation 1857ebdf956SGavin Shan */ 1867ebdf956SGavin Shan struct list_head pe_list; 187781a868fSWei Yang struct mutex pe_list_mutex; 1887ebdf956SGavin Shan 189c127562aSGavin Shan /* Reverse map of PEs, indexed by {bus, devfn} */ 190c127562aSGavin Shan unsigned int pe_rmap[0x10000]; 191184cd4a3SBenjamin Herrenschmidt } ioda; 192cee72d5bSBenjamin Herrenschmidt 1935cb1f8fdSRussell Currey /* PHB and hub diagnostics */ 1945cb1f8fdSRussell Currey unsigned int diag_data_size; 1955cb1f8fdSRussell Currey u8 *diag_data; 19661305a96SBenjamin Herrenschmidt }; 19761305a96SBenjamin Herrenschmidt 19837b59ef0SOliver O'Halloran 19937b59ef0SOliver O'Halloran /* IODA PE management */ 20037b59ef0SOliver O'Halloran 20137b59ef0SOliver O'Halloran static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) 20237b59ef0SOliver O'Halloran { 20337b59ef0SOliver O'Halloran /* 20437b59ef0SOliver O'Halloran * WARNING: We cannot rely on the resource flags. The Linux PCI 20537b59ef0SOliver O'Halloran * allocation code sometimes decides to put a 64-bit prefetchable 20637b59ef0SOliver O'Halloran * BAR in the 32-bit window, so we have to compare the addresses. 20737b59ef0SOliver O'Halloran * 20837b59ef0SOliver O'Halloran * For simplicity we only test resource start. 20937b59ef0SOliver O'Halloran */ 21037b59ef0SOliver O'Halloran return (r->start >= phb->ioda.m64_base && 21137b59ef0SOliver O'Halloran r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); 21237b59ef0SOliver O'Halloran } 21337b59ef0SOliver O'Halloran 21437b59ef0SOliver O'Halloran static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) 21537b59ef0SOliver O'Halloran { 21637b59ef0SOliver O'Halloran unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); 21737b59ef0SOliver O'Halloran 21837b59ef0SOliver O'Halloran return (resource_flags & flags) == flags; 21937b59ef0SOliver O'Halloran } 22037b59ef0SOliver O'Halloran 22137b59ef0SOliver O'Halloran int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 22237b59ef0SOliver O'Halloran int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 22337b59ef0SOliver O'Halloran 22437b59ef0SOliver O'Halloran void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe); 22537b59ef0SOliver O'Halloran void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe); 22637b59ef0SOliver O'Halloran 227a4bc676eSOliver O'Halloran struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count); 22837b59ef0SOliver O'Halloran void pnv_ioda_free_pe(struct pnv_ioda_pe *pe); 22937b59ef0SOliver O'Halloran 23037b59ef0SOliver O'Halloran #ifdef CONFIG_PCI_IOV 23137b59ef0SOliver O'Halloran /* 23237b59ef0SOliver O'Halloran * For SR-IOV we want to put each VF's MMIO resource in to a separate PE. 23337b59ef0SOliver O'Halloran * This requires a bit of acrobatics with the MMIO -> PE configuration 23437b59ef0SOliver O'Halloran * and this structure is used to keep track of it all. 23537b59ef0SOliver O'Halloran */ 23637b59ef0SOliver O'Halloran struct pnv_iov_data { 23737b59ef0SOliver O'Halloran /* number of VFs IOV BAR expanded. FIXME: rename this to something less bad */ 23837b59ef0SOliver O'Halloran u16 vfs_expanded; 23937b59ef0SOliver O'Halloran 24037b59ef0SOliver O'Halloran /* number of VFs enabled */ 24137b59ef0SOliver O'Halloran u16 num_vfs; 242d29a2488SOliver O'Halloran 243052da31dSOliver O'Halloran /* pointer to the array of VF PEs. num_vfs long*/ 244d29a2488SOliver O'Halloran struct pnv_ioda_pe *vf_pe_arr; 24537b59ef0SOliver O'Halloran 24637b59ef0SOliver O'Halloran /* Did we map the VF BARs with single-PE IODA BARs? */ 24737b59ef0SOliver O'Halloran bool m64_single_mode; 24837b59ef0SOliver O'Halloran 249ad9add52SOliver O'Halloran /* 250ad9add52SOliver O'Halloran * Bit mask used to track which m64 windows are used to map the 251ad9add52SOliver O'Halloran * SR-IOV BARs for this device. 252ad9add52SOliver O'Halloran */ 253ad9add52SOliver O'Halloran DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS); 25437b59ef0SOliver O'Halloran 25537b59ef0SOliver O'Halloran /* 25637b59ef0SOliver O'Halloran * If we map the SR-IOV BARs with a segmented window then 25737b59ef0SOliver O'Halloran * parts of that window will be "claimed" by other PEs. 25837b59ef0SOliver O'Halloran * 25937b59ef0SOliver O'Halloran * "holes" here is used to reserve the leading portion 26037b59ef0SOliver O'Halloran * of the window that is used by other (non VF) PEs. 26137b59ef0SOliver O'Halloran */ 26237b59ef0SOliver O'Halloran struct resource holes[PCI_SRIOV_NUM_BARS]; 26337b59ef0SOliver O'Halloran }; 26437b59ef0SOliver O'Halloran 26537b59ef0SOliver O'Halloran static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev) 26637b59ef0SOliver O'Halloran { 26737b59ef0SOliver O'Halloran return pdev->dev.archdata.iov_data; 26837b59ef0SOliver O'Halloran } 26937b59ef0SOliver O'Halloran 27037b59ef0SOliver O'Halloran void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev); 27137b59ef0SOliver O'Halloran resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno); 27237b59ef0SOliver O'Halloran 27337b59ef0SOliver O'Halloran int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 27437b59ef0SOliver O'Halloran int pnv_pcibios_sriov_disable(struct pci_dev *pdev); 27537b59ef0SOliver O'Halloran #endif /* CONFIG_PCI_IOV */ 27637b59ef0SOliver O'Halloran 27761305a96SBenjamin Herrenschmidt extern struct pci_ops pnv_pci_ops; 27861305a96SBenjamin Herrenschmidt 27993aef2a7SGavin Shan void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 28093aef2a7SGavin Shan unsigned char *log_buff); 2813532a741SGavin Shan int pnv_pci_cfg_read(struct pci_dn *pdn, 2829bf41be6SGavin Shan int where, int size, u32 *val); 2833532a741SGavin Shan int pnv_pci_cfg_write(struct pci_dn *pdn, 2849bf41be6SGavin Shan int where, int size, u32 val); 2850eaf4defSAlexey Kardashevskiy extern struct iommu_table *pnv_pci_table_alloc(int nid); 2860eaf4defSAlexey Kardashevskiy 287184cd4a3SBenjamin Herrenschmidt extern void pnv_pci_init_ioda_hub(struct device_node *np); 288aa0c033fSGavin Shan extern void pnv_pci_init_ioda2_phb(struct device_node *np); 2895d2aa710SAlistair Popple extern void pnv_pci_init_npu_phb(struct device_node *np); 2907f2c39e9SFrederic Barrat extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 2910e759bd7SAlexey Kardashevskiy extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr); 292d92a208dSGavin Shan extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 293cadf364dSGavin Shan extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 29473ed148aSBenjamin Herrenschmidt 29592ae0353SDaniel Axtens extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 29692ae0353SDaniel Axtens extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 297a8d7d5fcSOliver O'Halloran extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn); 298f456834aSIan Munsie extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev); 299f456834aSIan Munsie extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq); 3000bd97167SAlexey Kardashevskiy extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, 3010bd97167SAlexey Kardashevskiy __u64 window_size, __u32 levels); 302b9fde58dSBenjamin Herrenschmidt extern int pnv_eeh_post_init(void); 30392ae0353SDaniel Axtens 3041e496391SJoe Perches __printf(3, 4) 3057d623e42SAlexey Kardashevskiy extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 3067d623e42SAlexey Kardashevskiy const char *fmt, ...); 3077d623e42SAlexey Kardashevskiy #define pe_err(pe, fmt, ...) \ 3087d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) 3097d623e42SAlexey Kardashevskiy #define pe_warn(pe, fmt, ...) \ 3107d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) 3117d623e42SAlexey Kardashevskiy #define pe_info(pe, fmt, ...) \ 3127d623e42SAlexey Kardashevskiy pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) 3137d623e42SAlexey Kardashevskiy 3145d2aa710SAlistair Popple /* Nvlink functions */ 315f9f83456SAlexey Kardashevskiy extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass); 3166b3d12a9SAlistair Popple extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm); 31703b7bf34SOliver O'Halloran extern void pnv_pci_npu_setup_iommu_groups(void); 3184361b034SIan Munsie 319191c2287SAlexey Kardashevskiy /* pci-ioda-tce.c */ 320c37c792dSAlexey Kardashevskiy #define POWERNV_IOMMU_DEFAULT_LEVELS 2 321191c2287SAlexey Kardashevskiy #define POWERNV_IOMMU_MAX_LEVELS 5 322191c2287SAlexey Kardashevskiy 323191c2287SAlexey Kardashevskiy extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 324191c2287SAlexey Kardashevskiy unsigned long uaddr, enum dma_data_direction direction, 325191c2287SAlexey Kardashevskiy unsigned long attrs); 326191c2287SAlexey Kardashevskiy extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 327191c2287SAlexey Kardashevskiy extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 328a68bd126SAlexey Kardashevskiy unsigned long *hpa, enum dma_data_direction *direction, 329a68bd126SAlexey Kardashevskiy bool alloc); 330a68bd126SAlexey Kardashevskiy extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, 331a68bd126SAlexey Kardashevskiy bool alloc); 332191c2287SAlexey Kardashevskiy extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 333191c2287SAlexey Kardashevskiy 334191c2287SAlexey Kardashevskiy extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, 335191c2287SAlexey Kardashevskiy __u32 page_shift, __u64 window_size, __u32 levels, 336090bad39SAlexey Kardashevskiy bool alloc_userspace_copy, struct iommu_table *tbl); 337191c2287SAlexey Kardashevskiy extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); 338191c2287SAlexey Kardashevskiy 339191c2287SAlexey Kardashevskiy extern long pnv_pci_link_table_and_group(int node, int num, 340191c2287SAlexey Kardashevskiy struct iommu_table *tbl, 341191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group); 342191c2287SAlexey Kardashevskiy extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 343191c2287SAlexey Kardashevskiy struct iommu_table_group *table_group); 344191c2287SAlexey Kardashevskiy extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 345191c2287SAlexey Kardashevskiy void *tce_mem, u64 tce_size, 346191c2287SAlexey Kardashevskiy u64 dma_offset, unsigned int page_shift); 347191c2287SAlexey Kardashevskiy 34896e2006aSOliver O'Halloran extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb); 34996e2006aSOliver O'Halloran 3505609ffddSOliver O'Halloran static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus) 3515609ffddSOliver O'Halloran { 3525609ffddSOliver O'Halloran struct pci_controller *hose = bus->sysdata; 3535609ffddSOliver O'Halloran 3545609ffddSOliver O'Halloran if (hose) 3555609ffddSOliver O'Halloran return hose->private_data; 3565609ffddSOliver O'Halloran 3575609ffddSOliver O'Halloran return NULL; 3585609ffddSOliver O'Halloran } 3595609ffddSOliver O'Halloran 36061305a96SBenjamin Herrenschmidt #endif /* __POWERNV_PCI_H */ 361