1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Currently supports only P5IOC2 5 * 6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/delay.h> 17 #include <linux/string.h> 18 #include <linux/init.h> 19 #include <linux/bootmem.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/msi.h> 23 #include <linux/iommu.h> 24 25 #include <asm/sections.h> 26 #include <asm/io.h> 27 #include <asm/prom.h> 28 #include <asm/pci-bridge.h> 29 #include <asm/machdep.h> 30 #include <asm/msi_bitmap.h> 31 #include <asm/ppc-pci.h> 32 #include <asm/opal.h> 33 #include <asm/iommu.h> 34 #include <asm/tce.h> 35 #include <asm/firmware.h> 36 #include <asm/eeh_event.h> 37 #include <asm/eeh.h> 38 39 #include "powernv.h" 40 #include "pci.h" 41 42 /* Delay in usec */ 43 #define PCI_RESET_DELAY_US 3000000 44 45 #define cfg_dbg(fmt...) do { } while(0) 46 //#define cfg_dbg(fmt...) printk(fmt) 47 48 #ifdef CONFIG_PCI_MSI 49 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type) 50 { 51 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 52 struct pnv_phb *phb = hose->private_data; 53 struct pci_dn *pdn = pci_get_pdn(pdev); 54 55 if (pdn && pdn->force_32bit_msi && !phb->msi32_support) 56 return -ENODEV; 57 58 return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV; 59 } 60 61 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 62 { 63 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 64 struct pnv_phb *phb = hose->private_data; 65 struct msi_desc *entry; 66 struct msi_msg msg; 67 int hwirq; 68 unsigned int virq; 69 int rc; 70 71 if (WARN_ON(!phb)) 72 return -ENODEV; 73 74 list_for_each_entry(entry, &pdev->msi_list, list) { 75 if (!entry->msi_attrib.is_64 && !phb->msi32_support) { 76 pr_warn("%s: Supports only 64-bit MSIs\n", 77 pci_name(pdev)); 78 return -ENXIO; 79 } 80 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); 81 if (hwirq < 0) { 82 pr_warn("%s: Failed to find a free MSI\n", 83 pci_name(pdev)); 84 return -ENOSPC; 85 } 86 virq = irq_create_mapping(NULL, phb->msi_base + hwirq); 87 if (virq == NO_IRQ) { 88 pr_warn("%s: Failed to map MSI to linux irq\n", 89 pci_name(pdev)); 90 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 91 return -ENOMEM; 92 } 93 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, 94 virq, entry->msi_attrib.is_64, &msg); 95 if (rc) { 96 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); 97 irq_dispose_mapping(virq); 98 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 99 return rc; 100 } 101 irq_set_msi_desc(virq, entry); 102 write_msi_msg(virq, &msg); 103 } 104 return 0; 105 } 106 107 static void pnv_teardown_msi_irqs(struct pci_dev *pdev) 108 { 109 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 110 struct pnv_phb *phb = hose->private_data; 111 struct msi_desc *entry; 112 113 if (WARN_ON(!phb)) 114 return; 115 116 list_for_each_entry(entry, &pdev->msi_list, list) { 117 if (entry->irq == NO_IRQ) 118 continue; 119 irq_set_msi_desc(entry->irq, NULL); 120 msi_bitmap_free_hwirqs(&phb->msi_bmp, 121 virq_to_hw(entry->irq) - phb->msi_base, 1); 122 irq_dispose_mapping(entry->irq); 123 } 124 } 125 #endif /* CONFIG_PCI_MSI */ 126 127 static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb) 128 { 129 struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc; 130 int i; 131 132 pr_info("PHB %d diagnostic data:\n", phb->hose->global_number); 133 134 pr_info(" brdgCtl = 0x%08x\n", data->brdgCtl); 135 136 pr_info(" portStatusReg = 0x%08x\n", data->portStatusReg); 137 pr_info(" rootCmplxStatus = 0x%08x\n", data->rootCmplxStatus); 138 pr_info(" busAgentStatus = 0x%08x\n", data->busAgentStatus); 139 140 pr_info(" deviceStatus = 0x%08x\n", data->deviceStatus); 141 pr_info(" slotStatus = 0x%08x\n", data->slotStatus); 142 pr_info(" linkStatus = 0x%08x\n", data->linkStatus); 143 pr_info(" devCmdStatus = 0x%08x\n", data->devCmdStatus); 144 pr_info(" devSecStatus = 0x%08x\n", data->devSecStatus); 145 146 pr_info(" rootErrorStatus = 0x%08x\n", data->rootErrorStatus); 147 pr_info(" uncorrErrorStatus = 0x%08x\n", data->uncorrErrorStatus); 148 pr_info(" corrErrorStatus = 0x%08x\n", data->corrErrorStatus); 149 pr_info(" tlpHdr1 = 0x%08x\n", data->tlpHdr1); 150 pr_info(" tlpHdr2 = 0x%08x\n", data->tlpHdr2); 151 pr_info(" tlpHdr3 = 0x%08x\n", data->tlpHdr3); 152 pr_info(" tlpHdr4 = 0x%08x\n", data->tlpHdr4); 153 pr_info(" sourceId = 0x%08x\n", data->sourceId); 154 155 pr_info(" errorClass = 0x%016llx\n", data->errorClass); 156 pr_info(" correlator = 0x%016llx\n", data->correlator); 157 158 pr_info(" p7iocPlssr = 0x%016llx\n", data->p7iocPlssr); 159 pr_info(" p7iocCsr = 0x%016llx\n", data->p7iocCsr); 160 pr_info(" lemFir = 0x%016llx\n", data->lemFir); 161 pr_info(" lemErrorMask = 0x%016llx\n", data->lemErrorMask); 162 pr_info(" lemWOF = 0x%016llx\n", data->lemWOF); 163 pr_info(" phbErrorStatus = 0x%016llx\n", data->phbErrorStatus); 164 pr_info(" phbFirstErrorStatus = 0x%016llx\n", data->phbFirstErrorStatus); 165 pr_info(" phbErrorLog0 = 0x%016llx\n", data->phbErrorLog0); 166 pr_info(" phbErrorLog1 = 0x%016llx\n", data->phbErrorLog1); 167 pr_info(" mmioErrorStatus = 0x%016llx\n", data->mmioErrorStatus); 168 pr_info(" mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus); 169 pr_info(" mmioErrorLog0 = 0x%016llx\n", data->mmioErrorLog0); 170 pr_info(" mmioErrorLog1 = 0x%016llx\n", data->mmioErrorLog1); 171 pr_info(" dma0ErrorStatus = 0x%016llx\n", data->dma0ErrorStatus); 172 pr_info(" dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus); 173 pr_info(" dma0ErrorLog0 = 0x%016llx\n", data->dma0ErrorLog0); 174 pr_info(" dma0ErrorLog1 = 0x%016llx\n", data->dma0ErrorLog1); 175 pr_info(" dma1ErrorStatus = 0x%016llx\n", data->dma1ErrorStatus); 176 pr_info(" dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus); 177 pr_info(" dma1ErrorLog0 = 0x%016llx\n", data->dma1ErrorLog0); 178 pr_info(" dma1ErrorLog1 = 0x%016llx\n", data->dma1ErrorLog1); 179 180 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { 181 if ((data->pestA[i] >> 63) == 0 && 182 (data->pestB[i] >> 63) == 0) 183 continue; 184 pr_info(" PE[%3d] PESTA = 0x%016llx\n", i, data->pestA[i]); 185 pr_info(" PESTB = 0x%016llx\n", data->pestB[i]); 186 } 187 } 188 189 static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb) 190 { 191 switch(phb->model) { 192 case PNV_PHB_MODEL_P7IOC: 193 pnv_pci_dump_p7ioc_diag_data(phb); 194 break; 195 default: 196 pr_warning("PCI %d: Can't decode this PHB diag data\n", 197 phb->hose->global_number); 198 } 199 } 200 201 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) 202 { 203 unsigned long flags, rc; 204 int has_diag; 205 206 spin_lock_irqsave(&phb->lock, flags); 207 208 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, 209 PNV_PCI_DIAG_BUF_SIZE); 210 has_diag = (rc == OPAL_SUCCESS); 211 212 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 213 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 214 if (rc) { 215 pr_warning("PCI %d: Failed to clear EEH freeze state" 216 " for PE#%d, err %ld\n", 217 phb->hose->global_number, pe_no, rc); 218 219 /* For now, let's only display the diag buffer when we fail to clear 220 * the EEH status. We'll do more sensible things later when we have 221 * proper EEH support. We need to make sure we don't pollute ourselves 222 * with the normal errors generated when probing empty slots 223 */ 224 if (has_diag) 225 pnv_pci_dump_phb_diag_data(phb); 226 else 227 pr_warning("PCI %d: No diag data available\n", 228 phb->hose->global_number); 229 } 230 231 spin_unlock_irqrestore(&phb->lock, flags); 232 } 233 234 static void pnv_pci_config_check_eeh(struct pnv_phb *phb, 235 struct device_node *dn) 236 { 237 s64 rc; 238 u8 fstate; 239 u16 pcierr; 240 u32 pe_no; 241 242 /* 243 * Get the PE#. During the PCI probe stage, we might not 244 * setup that yet. So all ER errors should be mapped to 245 * PE#0 246 */ 247 pe_no = PCI_DN(dn)->pe_number; 248 if (pe_no == IODA_INVALID_PE) 249 pe_no = 0; 250 251 /* Read freeze status */ 252 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr, 253 NULL); 254 if (rc) { 255 pr_warning("%s: Can't read EEH status (PE#%d) for " 256 "%s, err %lld\n", 257 __func__, pe_no, dn->full_name, rc); 258 return; 259 } 260 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", 261 (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn), 262 pe_no, fstate); 263 if (fstate != 0) 264 pnv_pci_handle_eeh_config(phb, pe_no); 265 } 266 267 int pnv_pci_cfg_read(struct device_node *dn, 268 int where, int size, u32 *val) 269 { 270 struct pci_dn *pdn = PCI_DN(dn); 271 struct pnv_phb *phb = pdn->phb->private_data; 272 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 273 #ifdef CONFIG_EEH 274 struct eeh_pe *phb_pe = NULL; 275 #endif 276 s64 rc; 277 278 switch (size) { 279 case 1: { 280 u8 v8; 281 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); 282 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; 283 break; 284 } 285 case 2: { 286 u16 v16; 287 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, 288 &v16); 289 *val = (rc == OPAL_SUCCESS) ? v16 : 0xffff; 290 break; 291 } 292 case 4: { 293 u32 v32; 294 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); 295 *val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff; 296 break; 297 } 298 default: 299 return PCIBIOS_FUNC_NOT_SUPPORTED; 300 } 301 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 302 __func__, pdn->busno, pdn->devfn, where, size, *val); 303 304 /* 305 * Check if the specified PE has been put into frozen 306 * state. On the other hand, we needn't do that while 307 * the PHB has been put into frozen state because of 308 * PHB-fatal errors. 309 */ 310 #ifdef CONFIG_EEH 311 phb_pe = eeh_phb_pe_get(pdn->phb); 312 if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED)) 313 return PCIBIOS_SUCCESSFUL; 314 315 if (phb->eeh_state & PNV_EEH_STATE_ENABLED) { 316 if (*val == EEH_IO_ERROR_VALUE(size) && 317 eeh_dev_check_failure(of_node_to_eeh_dev(dn))) 318 return PCIBIOS_DEVICE_NOT_FOUND; 319 } else { 320 pnv_pci_config_check_eeh(phb, dn); 321 } 322 #else 323 pnv_pci_config_check_eeh(phb, dn); 324 #endif 325 326 return PCIBIOS_SUCCESSFUL; 327 } 328 329 int pnv_pci_cfg_write(struct device_node *dn, 330 int where, int size, u32 val) 331 { 332 struct pci_dn *pdn = PCI_DN(dn); 333 struct pnv_phb *phb = pdn->phb->private_data; 334 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 335 336 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 337 pdn->busno, pdn->devfn, where, size, val); 338 switch (size) { 339 case 1: 340 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); 341 break; 342 case 2: 343 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); 344 break; 345 case 4: 346 opal_pci_config_write_word(phb->opal_id, bdfn, where, val); 347 break; 348 default: 349 return PCIBIOS_FUNC_NOT_SUPPORTED; 350 } 351 352 /* Check if the PHB got frozen due to an error (no response) */ 353 #ifdef CONFIG_EEH 354 if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED)) 355 pnv_pci_config_check_eeh(phb, dn); 356 #else 357 pnv_pci_config_check_eeh(phb, dn); 358 #endif 359 360 return PCIBIOS_SUCCESSFUL; 361 } 362 363 static int pnv_pci_read_config(struct pci_bus *bus, 364 unsigned int devfn, 365 int where, int size, u32 *val) 366 { 367 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); 368 struct pci_dn *pdn; 369 370 for (dn = busdn->child; dn; dn = dn->sibling) { 371 pdn = PCI_DN(dn); 372 if (pdn && pdn->devfn == devfn) 373 return pnv_pci_cfg_read(dn, where, size, val); 374 } 375 376 *val = 0xFFFFFFFF; 377 return PCIBIOS_DEVICE_NOT_FOUND; 378 379 } 380 381 static int pnv_pci_write_config(struct pci_bus *bus, 382 unsigned int devfn, 383 int where, int size, u32 val) 384 { 385 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); 386 struct pci_dn *pdn; 387 388 for (dn = busdn->child; dn; dn = dn->sibling) { 389 pdn = PCI_DN(dn); 390 if (pdn && pdn->devfn == devfn) 391 return pnv_pci_cfg_write(dn, where, size, val); 392 } 393 394 return PCIBIOS_DEVICE_NOT_FOUND; 395 } 396 397 struct pci_ops pnv_pci_ops = { 398 .read = pnv_pci_read_config, 399 .write = pnv_pci_write_config, 400 }; 401 402 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 403 unsigned long uaddr, enum dma_data_direction direction, 404 struct dma_attrs *attrs) 405 { 406 u64 proto_tce; 407 u64 *tcep, *tces; 408 u64 rpn; 409 410 proto_tce = TCE_PCI_READ; // Read allowed 411 412 if (direction != DMA_TO_DEVICE) 413 proto_tce |= TCE_PCI_WRITE; 414 415 tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset; 416 rpn = __pa(uaddr) >> TCE_SHIFT; 417 418 while (npages--) 419 *(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT); 420 421 /* Some implementations won't cache invalid TCEs and thus may not 422 * need that flush. We'll probably turn it_type into a bit mask 423 * of flags if that becomes the case 424 */ 425 if (tbl->it_type & TCE_PCI_SWINV_CREATE) 426 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1); 427 428 return 0; 429 } 430 431 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages) 432 { 433 u64 *tcep, *tces; 434 435 tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset; 436 437 while (npages--) 438 *(tcep++) = 0; 439 440 if (tbl->it_type & TCE_PCI_SWINV_FREE) 441 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1); 442 } 443 444 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index) 445 { 446 return ((u64 *)tbl->it_base)[index - tbl->it_offset]; 447 } 448 449 void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 450 void *tce_mem, u64 tce_size, 451 u64 dma_offset) 452 { 453 tbl->it_blocksize = 16; 454 tbl->it_base = (unsigned long)tce_mem; 455 tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT; 456 tbl->it_index = 0; 457 tbl->it_size = tce_size >> 3; 458 tbl->it_busno = 0; 459 tbl->it_type = TCE_PCI; 460 } 461 462 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose) 463 { 464 struct iommu_table *tbl; 465 const __be64 *basep, *swinvp; 466 const __be32 *sizep; 467 468 basep = of_get_property(hose->dn, "linux,tce-base", NULL); 469 sizep = of_get_property(hose->dn, "linux,tce-size", NULL); 470 if (basep == NULL || sizep == NULL) { 471 pr_err("PCI: %s has missing tce entries !\n", 472 hose->dn->full_name); 473 return NULL; 474 } 475 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node); 476 if (WARN_ON(!tbl)) 477 return NULL; 478 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)), 479 be32_to_cpup(sizep), 0); 480 iommu_init_table(tbl, hose->node); 481 iommu_register_group(tbl, pci_domain_nr(hose->bus), 0); 482 483 /* Deal with SW invalidated TCEs when needed (BML way) */ 484 swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info", 485 NULL); 486 if (swinvp) { 487 tbl->it_busno = swinvp[1]; 488 tbl->it_index = (unsigned long)ioremap(swinvp[0], 8); 489 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; 490 } 491 return tbl; 492 } 493 494 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose, 495 struct pci_dev *pdev) 496 { 497 struct device_node *np = pci_bus_to_OF_node(hose->bus); 498 struct pci_dn *pdn; 499 500 if (np == NULL) 501 return; 502 pdn = PCI_DN(np); 503 if (!pdn->iommu_table) 504 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose); 505 if (!pdn->iommu_table) 506 return; 507 set_iommu_table_base(&pdev->dev, pdn->iommu_table); 508 } 509 510 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev) 511 { 512 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 513 struct pnv_phb *phb = hose->private_data; 514 515 /* If we have no phb structure, try to setup a fallback based on 516 * the device-tree (RTAS PCI for example) 517 */ 518 if (phb && phb->dma_dev_setup) 519 phb->dma_dev_setup(phb, pdev); 520 else 521 pnv_pci_dma_fallback_setup(hose, pdev); 522 } 523 524 void pnv_pci_shutdown(void) 525 { 526 struct pci_controller *hose; 527 528 list_for_each_entry(hose, &hose_list, list_node) { 529 struct pnv_phb *phb = hose->private_data; 530 531 if (phb && phb->shutdown) 532 phb->shutdown(phb); 533 } 534 } 535 536 /* Fixup wrong class code in p7ioc and p8 root complex */ 537 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) 538 { 539 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 540 } 541 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); 542 543 static int pnv_pci_probe_mode(struct pci_bus *bus) 544 { 545 struct pci_controller *hose = pci_bus_to_host(bus); 546 const __be64 *tstamp; 547 u64 now, target; 548 549 550 /* We hijack this as a way to ensure we have waited long 551 * enough since the reset was lifted on the PCI bus 552 */ 553 if (bus != hose->bus) 554 return PCI_PROBE_NORMAL; 555 tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL); 556 if (!tstamp || !*tstamp) 557 return PCI_PROBE_NORMAL; 558 559 now = mftb() / tb_ticks_per_usec; 560 target = (be64_to_cpup(tstamp) / tb_ticks_per_usec) 561 + PCI_RESET_DELAY_US; 562 563 pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n", 564 hose->global_number, target, now); 565 566 if (now < target) 567 msleep((target - now + 999) / 1000); 568 569 return PCI_PROBE_NORMAL; 570 } 571 572 void __init pnv_pci_init(void) 573 { 574 struct device_node *np; 575 576 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); 577 578 /* OPAL absent, try POPAL first then RTAS detection of PHBs */ 579 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 580 #ifdef CONFIG_PPC_POWERNV_RTAS 581 init_pci_config_tokens(); 582 find_and_init_phbs(); 583 #endif /* CONFIG_PPC_POWERNV_RTAS */ 584 } 585 /* OPAL is here, do our normal stuff */ 586 else { 587 int found_ioda = 0; 588 589 /* Look for IODA IO-Hubs. We don't support mixing IODA 590 * and p5ioc2 due to the need to change some global 591 * probing flags 592 */ 593 for_each_compatible_node(np, NULL, "ibm,ioda-hub") { 594 pnv_pci_init_ioda_hub(np); 595 found_ioda = 1; 596 } 597 598 /* Look for p5ioc2 IO-Hubs */ 599 if (!found_ioda) 600 for_each_compatible_node(np, NULL, "ibm,p5ioc2") 601 pnv_pci_init_p5ioc2_hub(np); 602 603 /* Look for ioda2 built-in PHB3's */ 604 for_each_compatible_node(np, NULL, "ibm,ioda2-phb") 605 pnv_pci_init_ioda2_phb(np); 606 } 607 608 /* Setup the linkage between OF nodes and PHBs */ 609 pci_devs_phb_init(); 610 611 /* Configure IOMMU DMA hooks */ 612 ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup; 613 ppc_md.tce_build = pnv_tce_build; 614 ppc_md.tce_free = pnv_tce_free; 615 ppc_md.tce_get = pnv_tce_get; 616 ppc_md.pci_probe_mode = pnv_pci_probe_mode; 617 set_pci_dma_ops(&dma_iommu_ops); 618 619 /* Configure MSIs */ 620 #ifdef CONFIG_PCI_MSI 621 ppc_md.msi_check_device = pnv_msi_check_device; 622 ppc_md.setup_msi_irqs = pnv_setup_msi_irqs; 623 ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs; 624 #endif 625 } 626