1 /*
2  * Support PCI/PCIe on PowerNV platforms
3  *
4  * Currently supports only P5IOC2
5  *
6  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * as published by the Free Software Foundation; either version
11  * 2 of the License, or (at your option) any later version.
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/bootmem.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22 #include <linux/msi.h>
23 #include <linux/iommu.h>
24 
25 #include <asm/sections.h>
26 #include <asm/io.h>
27 #include <asm/prom.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/machdep.h>
30 #include <asm/msi_bitmap.h>
31 #include <asm/ppc-pci.h>
32 #include <asm/opal.h>
33 #include <asm/iommu.h>
34 #include <asm/tce.h>
35 #include <asm/firmware.h>
36 #include <asm/eeh_event.h>
37 #include <asm/eeh.h>
38 
39 #include "powernv.h"
40 #include "pci.h"
41 
42 /* Delay in usec */
43 #define PCI_RESET_DELAY_US	3000000
44 
45 #define cfg_dbg(fmt...)	do { } while(0)
46 //#define cfg_dbg(fmt...)	printk(fmt)
47 
48 #ifdef CONFIG_PCI_MSI
49 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
50 {
51 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
52 	struct pnv_phb *phb = hose->private_data;
53 	struct pci_dn *pdn = pci_get_pdn(pdev);
54 
55 	if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
56 		return -ENODEV;
57 
58 	return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
59 }
60 
61 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
62 {
63 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
64 	struct pnv_phb *phb = hose->private_data;
65 	struct msi_desc *entry;
66 	struct msi_msg msg;
67 	int hwirq;
68 	unsigned int virq;
69 	int rc;
70 
71 	if (WARN_ON(!phb))
72 		return -ENODEV;
73 
74 	list_for_each_entry(entry, &pdev->msi_list, list) {
75 		if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
76 			pr_warn("%s: Supports only 64-bit MSIs\n",
77 				pci_name(pdev));
78 			return -ENXIO;
79 		}
80 		hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
81 		if (hwirq < 0) {
82 			pr_warn("%s: Failed to find a free MSI\n",
83 				pci_name(pdev));
84 			return -ENOSPC;
85 		}
86 		virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
87 		if (virq == NO_IRQ) {
88 			pr_warn("%s: Failed to map MSI to linux irq\n",
89 				pci_name(pdev));
90 			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
91 			return -ENOMEM;
92 		}
93 		rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
94 				    virq, entry->msi_attrib.is_64, &msg);
95 		if (rc) {
96 			pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
97 			irq_dispose_mapping(virq);
98 			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
99 			return rc;
100 		}
101 		irq_set_msi_desc(virq, entry);
102 		write_msi_msg(virq, &msg);
103 	}
104 	return 0;
105 }
106 
107 static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
108 {
109 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
110 	struct pnv_phb *phb = hose->private_data;
111 	struct msi_desc *entry;
112 
113 	if (WARN_ON(!phb))
114 		return;
115 
116 	list_for_each_entry(entry, &pdev->msi_list, list) {
117 		if (entry->irq == NO_IRQ)
118 			continue;
119 		irq_set_msi_desc(entry->irq, NULL);
120 		msi_bitmap_free_hwirqs(&phb->msi_bmp,
121 			virq_to_hw(entry->irq) - phb->msi_base, 1);
122 		irq_dispose_mapping(entry->irq);
123 	}
124 }
125 #endif /* CONFIG_PCI_MSI */
126 
127 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
128 					 struct OpalIoPhbErrorCommon *common)
129 {
130 	struct OpalIoP7IOCPhbErrorData *data;
131 	int i;
132 
133 	data = (struct OpalIoP7IOCPhbErrorData *)common;
134 	pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n",
135 		hose->global_number, common->version);
136 
137 	if (data->brdgCtl)
138 		pr_info("brdgCtl:     %08x\n",
139 			data->brdgCtl);
140 	if (data->portStatusReg || data->rootCmplxStatus ||
141 	    data->busAgentStatus)
142 		pr_info("UtlSts:      %08x %08x %08x\n",
143 			data->portStatusReg, data->rootCmplxStatus,
144 			data->busAgentStatus);
145 	if (data->deviceStatus || data->slotStatus   ||
146 	    data->linkStatus   || data->devCmdStatus ||
147 	    data->devSecStatus)
148 		pr_info("RootSts:     %08x %08x %08x %08x %08x\n",
149 			data->deviceStatus, data->slotStatus,
150 			data->linkStatus, data->devCmdStatus,
151 			data->devSecStatus);
152 	if (data->rootErrorStatus   || data->uncorrErrorStatus ||
153 	    data->corrErrorStatus)
154 		pr_info("RootErrSts:  %08x %08x %08x\n",
155 			data->rootErrorStatus, data->uncorrErrorStatus,
156 			data->corrErrorStatus);
157 	if (data->tlpHdr1 || data->tlpHdr2 ||
158 	    data->tlpHdr3 || data->tlpHdr4)
159 		pr_info("RootErrLog:  %08x %08x %08x %08x\n",
160 			data->tlpHdr1, data->tlpHdr2,
161 			data->tlpHdr3, data->tlpHdr4);
162 	if (data->sourceId || data->errorClass ||
163 	    data->correlator)
164 		pr_info("RootErrLog1: %08x %016llx %016llx\n",
165 			data->sourceId, data->errorClass,
166 			data->correlator);
167 	if (data->p7iocPlssr || data->p7iocCsr)
168 		pr_info("PhbSts:      %016llx %016llx\n",
169 			data->p7iocPlssr, data->p7iocCsr);
170 	if (data->lemFir)
171 		pr_info("Lem:         %016llx %016llx %016llx\n",
172 			data->lemFir, data->lemErrorMask,
173 			data->lemWOF);
174 	if (data->phbErrorStatus)
175 		pr_info("PhbErr:      %016llx %016llx %016llx %016llx\n",
176 			data->phbErrorStatus, data->phbFirstErrorStatus,
177 			data->phbErrorLog0, data->phbErrorLog1);
178 	if (data->mmioErrorStatus)
179 		pr_info("OutErr:      %016llx %016llx %016llx %016llx\n",
180 			data->mmioErrorStatus, data->mmioFirstErrorStatus,
181 			data->mmioErrorLog0, data->mmioErrorLog1);
182 	if (data->dma0ErrorStatus)
183 		pr_info("InAErr:      %016llx %016llx %016llx %016llx\n",
184 			data->dma0ErrorStatus, data->dma0FirstErrorStatus,
185 			data->dma0ErrorLog0, data->dma0ErrorLog1);
186 	if (data->dma1ErrorStatus)
187 		pr_info("InBErr:      %016llx %016llx %016llx %016llx\n",
188 			data->dma1ErrorStatus, data->dma1FirstErrorStatus,
189 			data->dma1ErrorLog0, data->dma1ErrorLog1);
190 
191 	for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
192 		if ((data->pestA[i] >> 63) == 0 &&
193 		    (data->pestB[i] >> 63) == 0)
194 			continue;
195 
196 		pr_info("PE[%3d] A/B: %016llx %016llx\n",
197 			i, data->pestA[i], data->pestB[i]);
198 	}
199 }
200 
201 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
202 					struct OpalIoPhbErrorCommon *common)
203 {
204 	struct OpalIoPhb3ErrorData *data;
205 	int i;
206 
207 	data = (struct OpalIoPhb3ErrorData*)common;
208 	pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n",
209 		hose->global_number, be32_to_cpu(common->version));
210 	if (data->brdgCtl)
211 		pr_info("brdgCtl:     %08x\n",
212 			be32_to_cpu(data->brdgCtl));
213 	if (data->portStatusReg || data->rootCmplxStatus ||
214 	    data->busAgentStatus)
215 		pr_info("UtlSts:      %08x %08x %08x\n",
216 			be32_to_cpu(data->portStatusReg),
217 			be32_to_cpu(data->rootCmplxStatus),
218 			be32_to_cpu(data->busAgentStatus));
219 	if (data->deviceStatus || data->slotStatus   ||
220 	    data->linkStatus   || data->devCmdStatus ||
221 	    data->devSecStatus)
222 		pr_info("RootSts:     %08x %08x %08x %08x %08x\n",
223 			be32_to_cpu(data->deviceStatus),
224 			be32_to_cpu(data->slotStatus),
225 			be32_to_cpu(data->linkStatus),
226 			be32_to_cpu(data->devCmdStatus),
227 			be32_to_cpu(data->devSecStatus));
228 	if (data->rootErrorStatus || data->uncorrErrorStatus ||
229 	    data->corrErrorStatus)
230 		pr_info("RootErrSts:  %08x %08x %08x\n",
231 			be32_to_cpu(data->rootErrorStatus),
232 			be32_to_cpu(data->uncorrErrorStatus),
233 			be32_to_cpu(data->corrErrorStatus));
234 	if (data->tlpHdr1 || data->tlpHdr2 ||
235 	    data->tlpHdr3 || data->tlpHdr4)
236 		pr_info("RootErrLog:  %08x %08x %08x %08x\n",
237 			be32_to_cpu(data->tlpHdr1),
238 			be32_to_cpu(data->tlpHdr2),
239 			be32_to_cpu(data->tlpHdr3),
240 			be32_to_cpu(data->tlpHdr4));
241 	if (data->sourceId || data->errorClass ||
242 	    data->correlator)
243 		pr_info("RootErrLog1: %08x %016llx %016llx\n",
244 			be32_to_cpu(data->sourceId),
245 			be64_to_cpu(data->errorClass),
246 			be64_to_cpu(data->correlator));
247 	if (data->nFir)
248 		pr_info("nFir:        %016llx %016llx %016llx\n",
249 			be64_to_cpu(data->nFir),
250 			be64_to_cpu(data->nFirMask),
251 			be64_to_cpu(data->nFirWOF));
252 	if (data->phbPlssr || data->phbCsr)
253 		pr_info("PhbSts:      %016llx %016llx\n",
254 			be64_to_cpu(data->phbPlssr),
255 			be64_to_cpu(data->phbCsr));
256 	if (data->lemFir)
257 		pr_info("Lem:         %016llx %016llx %016llx\n",
258 			be64_to_cpu(data->lemFir),
259 			be64_to_cpu(data->lemErrorMask),
260 			be64_to_cpu(data->lemWOF));
261 	if (data->phbErrorStatus)
262 		pr_info("PhbErr:      %016llx %016llx %016llx %016llx\n",
263 			be64_to_cpu(data->phbErrorStatus),
264 			be64_to_cpu(data->phbFirstErrorStatus),
265 			be64_to_cpu(data->phbErrorLog0),
266 			be64_to_cpu(data->phbErrorLog1));
267 	if (data->mmioErrorStatus)
268 		pr_info("OutErr:      %016llx %016llx %016llx %016llx\n",
269 			be64_to_cpu(data->mmioErrorStatus),
270 			be64_to_cpu(data->mmioFirstErrorStatus),
271 			be64_to_cpu(data->mmioErrorLog0),
272 			be64_to_cpu(data->mmioErrorLog1));
273 	if (data->dma0ErrorStatus)
274 		pr_info("InAErr:      %016llx %016llx %016llx %016llx\n",
275 			be64_to_cpu(data->dma0ErrorStatus),
276 			be64_to_cpu(data->dma0FirstErrorStatus),
277 			be64_to_cpu(data->dma0ErrorLog0),
278 			be64_to_cpu(data->dma0ErrorLog1));
279 	if (data->dma1ErrorStatus)
280 		pr_info("InBErr:      %016llx %016llx %016llx %016llx\n",
281 			be64_to_cpu(data->dma1ErrorStatus),
282 			be64_to_cpu(data->dma1FirstErrorStatus),
283 			be64_to_cpu(data->dma1ErrorLog0),
284 			be64_to_cpu(data->dma1ErrorLog1));
285 
286 	for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
287 		if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 &&
288 		    (be64_to_cpu(data->pestB[i]) >> 63) == 0)
289 			continue;
290 
291 		pr_info("PE[%3d] A/B: %016llx %016llx\n",
292 				i, be64_to_cpu(data->pestA[i]),
293 				be64_to_cpu(data->pestB[i]));
294 	}
295 }
296 
297 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
298 				unsigned char *log_buff)
299 {
300 	struct OpalIoPhbErrorCommon *common;
301 
302 	if (!hose || !log_buff)
303 		return;
304 
305 	common = (struct OpalIoPhbErrorCommon *)log_buff;
306 	switch (be32_to_cpu(common->ioType)) {
307 	case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
308 		pnv_pci_dump_p7ioc_diag_data(hose, common);
309 		break;
310 	case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
311 		pnv_pci_dump_phb3_diag_data(hose, common);
312 		break;
313 	default:
314 		pr_warn("%s: Unrecognized ioType %d\n",
315 			__func__, be32_to_cpu(common->ioType));
316 	}
317 }
318 
319 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
320 {
321 	unsigned long flags, rc;
322 	int has_diag;
323 
324 	spin_lock_irqsave(&phb->lock, flags);
325 
326 	rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
327 					 PNV_PCI_DIAG_BUF_SIZE);
328 	has_diag = (rc == OPAL_SUCCESS);
329 
330 	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
331 				       OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
332 	if (rc) {
333 		pr_warning("PCI %d: Failed to clear EEH freeze state"
334 			   " for PE#%d, err %ld\n",
335 			   phb->hose->global_number, pe_no, rc);
336 
337 		/* For now, let's only display the diag buffer when we fail to clear
338 		 * the EEH status. We'll do more sensible things later when we have
339 		 * proper EEH support. We need to make sure we don't pollute ourselves
340 		 * with the normal errors generated when probing empty slots
341 		 */
342 		if (has_diag)
343 			pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
344 		else
345 			pr_warning("PCI %d: No diag data available\n",
346 				   phb->hose->global_number);
347 	}
348 
349 	spin_unlock_irqrestore(&phb->lock, flags);
350 }
351 
352 static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
353 				     struct device_node *dn)
354 {
355 	s64	rc;
356 	u8	fstate;
357 	__be16	pcierr;
358 	u32	pe_no;
359 
360 	/*
361 	 * Get the PE#. During the PCI probe stage, we might not
362 	 * setup that yet. So all ER errors should be mapped to
363 	 * reserved PE.
364 	 */
365 	pe_no = PCI_DN(dn)->pe_number;
366 	if (pe_no == IODA_INVALID_PE) {
367 		if (phb->type == PNV_PHB_P5IOC2)
368 			pe_no = 0;
369 		else
370 			pe_no = phb->ioda.reserved_pe;
371 	}
372 
373 	/* Read freeze status */
374 	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
375 					NULL);
376 	if (rc) {
377 		pr_warning("%s: Can't read EEH status (PE#%d) for "
378 			   "%s, err %lld\n",
379 			   __func__, pe_no, dn->full_name, rc);
380 		return;
381 	}
382 	cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
383 		(PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn),
384 		pe_no, fstate);
385 	if (fstate != 0)
386 		pnv_pci_handle_eeh_config(phb, pe_no);
387 }
388 
389 int pnv_pci_cfg_read(struct device_node *dn,
390 		     int where, int size, u32 *val)
391 {
392 	struct pci_dn *pdn = PCI_DN(dn);
393 	struct pnv_phb *phb = pdn->phb->private_data;
394 	u32 bdfn = (pdn->busno << 8) | pdn->devfn;
395 	s64 rc;
396 
397 	switch (size) {
398 	case 1: {
399 		u8 v8;
400 		rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
401 		*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
402 		break;
403 	}
404 	case 2: {
405 		__be16 v16;
406 		rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
407 						   &v16);
408 		*val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
409 		break;
410 	}
411 	case 4: {
412 		__be32 v32;
413 		rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
414 		*val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
415 		break;
416 	}
417 	default:
418 		return PCIBIOS_FUNC_NOT_SUPPORTED;
419 	}
420 
421 	cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
422 		__func__, pdn->busno, pdn->devfn, where, size, *val);
423 	return PCIBIOS_SUCCESSFUL;
424 }
425 
426 int pnv_pci_cfg_write(struct device_node *dn,
427 		      int where, int size, u32 val)
428 {
429 	struct pci_dn *pdn = PCI_DN(dn);
430 	struct pnv_phb *phb = pdn->phb->private_data;
431 	u32 bdfn = (pdn->busno << 8) | pdn->devfn;
432 
433 	cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
434 		pdn->busno, pdn->devfn, where, size, val);
435 	switch (size) {
436 	case 1:
437 		opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
438 		break;
439 	case 2:
440 		opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
441 		break;
442 	case 4:
443 		opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
444 		break;
445 	default:
446 		return PCIBIOS_FUNC_NOT_SUPPORTED;
447 	}
448 
449 	return PCIBIOS_SUCCESSFUL;
450 }
451 
452 #if CONFIG_EEH
453 static bool pnv_pci_cfg_check(struct pci_controller *hose,
454 			      struct device_node *dn)
455 {
456 	struct eeh_dev *edev = NULL;
457 	struct pnv_phb *phb = hose->private_data;
458 
459 	/* EEH not enabled ? */
460 	if (!(phb->flags & PNV_PHB_FLAG_EEH))
461 		return true;
462 
463 	/* PE reset or device removed ? */
464 	edev = of_node_to_eeh_dev(dn);
465 	if (edev) {
466 		if (edev->pe &&
467 		    (edev->pe->state & EEH_PE_RESET))
468 			return false;
469 
470 		if (edev->mode & EEH_DEV_REMOVED)
471 			return false;
472 	}
473 
474 	return true;
475 }
476 #else
477 static inline pnv_pci_cfg_check(struct pci_controller *hose,
478 				struct device_node *dn)
479 {
480 	return true;
481 }
482 #endif /* CONFIG_EEH */
483 
484 static int pnv_pci_read_config(struct pci_bus *bus,
485 			       unsigned int devfn,
486 			       int where, int size, u32 *val)
487 {
488 	struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
489 	struct pci_dn *pdn;
490 	struct pnv_phb *phb;
491 	bool found = false;
492 	int ret;
493 
494 	*val = 0xFFFFFFFF;
495 	for (dn = busdn->child; dn; dn = dn->sibling) {
496 		pdn = PCI_DN(dn);
497 		if (pdn && pdn->devfn == devfn) {
498 			phb = pdn->phb->private_data;
499 			found = true;
500 			break;
501 		}
502 	}
503 
504 	if (!found || !pnv_pci_cfg_check(pdn->phb, dn))
505 		return PCIBIOS_DEVICE_NOT_FOUND;
506 
507 	ret = pnv_pci_cfg_read(dn, where, size, val);
508 	if (phb->flags & PNV_PHB_FLAG_EEH) {
509 		if (*val == EEH_IO_ERROR_VALUE(size) &&
510 		    eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
511                         return PCIBIOS_DEVICE_NOT_FOUND;
512 	} else {
513 		pnv_pci_config_check_eeh(phb, dn);
514 	}
515 
516 	return ret;
517 }
518 
519 static int pnv_pci_write_config(struct pci_bus *bus,
520 				unsigned int devfn,
521 				int where, int size, u32 val)
522 {
523 	struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
524 	struct pci_dn *pdn;
525 	struct pnv_phb *phb;
526 	bool found = false;
527 	int ret;
528 
529 	for (dn = busdn->child; dn; dn = dn->sibling) {
530 		pdn = PCI_DN(dn);
531 		if (pdn && pdn->devfn == devfn) {
532 			phb = pdn->phb->private_data;
533 			found = true;
534 			break;
535 		}
536 	}
537 
538 	if (!found || !pnv_pci_cfg_check(pdn->phb, dn))
539 		return PCIBIOS_DEVICE_NOT_FOUND;
540 
541 	ret = pnv_pci_cfg_write(dn, where, size, val);
542 	if (!(phb->flags & PNV_PHB_FLAG_EEH))
543 		pnv_pci_config_check_eeh(phb, dn);
544 
545 	return ret;
546 }
547 
548 struct pci_ops pnv_pci_ops = {
549 	.read  = pnv_pci_read_config,
550 	.write = pnv_pci_write_config,
551 };
552 
553 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
554 			 unsigned long uaddr, enum dma_data_direction direction,
555 			 struct dma_attrs *attrs, bool rm)
556 {
557 	u64 proto_tce;
558 	__be64 *tcep, *tces;
559 	u64 rpn;
560 
561 	proto_tce = TCE_PCI_READ; // Read allowed
562 
563 	if (direction != DMA_TO_DEVICE)
564 		proto_tce |= TCE_PCI_WRITE;
565 
566 	tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset;
567 	rpn = __pa(uaddr) >> TCE_SHIFT;
568 
569 	while (npages--)
570 		*(tcep++) = cpu_to_be64(proto_tce | (rpn++ << TCE_RPN_SHIFT));
571 
572 	/* Some implementations won't cache invalid TCEs and thus may not
573 	 * need that flush. We'll probably turn it_type into a bit mask
574 	 * of flags if that becomes the case
575 	 */
576 	if (tbl->it_type & TCE_PCI_SWINV_CREATE)
577 		pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm);
578 
579 	return 0;
580 }
581 
582 static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages,
583 			    unsigned long uaddr,
584 			    enum dma_data_direction direction,
585 			    struct dma_attrs *attrs)
586 {
587 	return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs,
588 			false);
589 }
590 
591 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages,
592 		bool rm)
593 {
594 	__be64 *tcep, *tces;
595 
596 	tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset;
597 
598 	while (npages--)
599 		*(tcep++) = cpu_to_be64(0);
600 
601 	if (tbl->it_type & TCE_PCI_SWINV_FREE)
602 		pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm);
603 }
604 
605 static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages)
606 {
607 	pnv_tce_free(tbl, index, npages, false);
608 }
609 
610 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
611 {
612 	return ((u64 *)tbl->it_base)[index - tbl->it_offset];
613 }
614 
615 static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages,
616 			    unsigned long uaddr,
617 			    enum dma_data_direction direction,
618 			    struct dma_attrs *attrs)
619 {
620 	return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true);
621 }
622 
623 static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages)
624 {
625 	pnv_tce_free(tbl, index, npages, true);
626 }
627 
628 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
629 			       void *tce_mem, u64 tce_size,
630 			       u64 dma_offset)
631 {
632 	tbl->it_blocksize = 16;
633 	tbl->it_base = (unsigned long)tce_mem;
634 	tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
635 	tbl->it_offset = dma_offset >> tbl->it_page_shift;
636 	tbl->it_index = 0;
637 	tbl->it_size = tce_size >> 3;
638 	tbl->it_busno = 0;
639 	tbl->it_type = TCE_PCI;
640 }
641 
642 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
643 {
644 	struct iommu_table *tbl;
645 	const __be64 *basep, *swinvp;
646 	const __be32 *sizep;
647 
648 	basep = of_get_property(hose->dn, "linux,tce-base", NULL);
649 	sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
650 	if (basep == NULL || sizep == NULL) {
651 		pr_err("PCI: %s has missing tce entries !\n",
652 		       hose->dn->full_name);
653 		return NULL;
654 	}
655 	tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
656 	if (WARN_ON(!tbl))
657 		return NULL;
658 	pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
659 				  be32_to_cpup(sizep), 0);
660 	iommu_init_table(tbl, hose->node);
661 	iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
662 
663 	/* Deal with SW invalidated TCEs when needed (BML way) */
664 	swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
665 				 NULL);
666 	if (swinvp) {
667 		tbl->it_busno = be64_to_cpu(swinvp[1]);
668 		tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
669 		tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
670 	}
671 	return tbl;
672 }
673 
674 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
675 				       struct pci_dev *pdev)
676 {
677 	struct device_node *np = pci_bus_to_OF_node(hose->bus);
678 	struct pci_dn *pdn;
679 
680 	if (np == NULL)
681 		return;
682 	pdn = PCI_DN(np);
683 	if (!pdn->iommu_table)
684 		pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
685 	if (!pdn->iommu_table)
686 		return;
687 	set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table);
688 }
689 
690 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
691 {
692 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
693 	struct pnv_phb *phb = hose->private_data;
694 
695 	/* If we have no phb structure, try to setup a fallback based on
696 	 * the device-tree (RTAS PCI for example)
697 	 */
698 	if (phb && phb->dma_dev_setup)
699 		phb->dma_dev_setup(phb, pdev);
700 	else
701 		pnv_pci_dma_fallback_setup(hose, pdev);
702 }
703 
704 int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
705 {
706 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
707 	struct pnv_phb *phb = hose->private_data;
708 
709 	if (phb && phb->dma_set_mask)
710 		return phb->dma_set_mask(phb, pdev, dma_mask);
711 	return __dma_set_mask(&pdev->dev, dma_mask);
712 }
713 
714 void pnv_pci_shutdown(void)
715 {
716 	struct pci_controller *hose;
717 
718 	list_for_each_entry(hose, &hose_list, list_node) {
719 		struct pnv_phb *phb = hose->private_data;
720 
721 		if (phb && phb->shutdown)
722 			phb->shutdown(phb);
723 	}
724 }
725 
726 /* Fixup wrong class code in p7ioc and p8 root complex */
727 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
728 {
729 	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
730 }
731 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
732 
733 static int pnv_pci_probe_mode(struct pci_bus *bus)
734 {
735 	struct pci_controller *hose = pci_bus_to_host(bus);
736 	const __be64 *tstamp;
737 	u64 now, target;
738 
739 
740 	/* We hijack this as a way to ensure we have waited long
741 	 * enough since the reset was lifted on the PCI bus
742 	 */
743 	if (bus != hose->bus)
744 		return PCI_PROBE_NORMAL;
745 	tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
746 	if (!tstamp || !*tstamp)
747 		return PCI_PROBE_NORMAL;
748 
749 	now = mftb() / tb_ticks_per_usec;
750 	target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
751 		+ PCI_RESET_DELAY_US;
752 
753 	pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
754 		 hose->global_number, target, now);
755 
756 	if (now < target)
757 		msleep((target - now + 999) / 1000);
758 
759 	return PCI_PROBE_NORMAL;
760 }
761 
762 void __init pnv_pci_init(void)
763 {
764 	struct device_node *np;
765 
766 	pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
767 
768 	/* OPAL absent, try POPAL first then RTAS detection of PHBs */
769 	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
770 #ifdef CONFIG_PPC_POWERNV_RTAS
771 		init_pci_config_tokens();
772 		find_and_init_phbs();
773 #endif /* CONFIG_PPC_POWERNV_RTAS */
774 	}
775 	/* OPAL is here, do our normal stuff */
776 	else {
777 		int found_ioda = 0;
778 
779 		/* Look for IODA IO-Hubs. We don't support mixing IODA
780 		 * and p5ioc2 due to the need to change some global
781 		 * probing flags
782 		 */
783 		for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
784 			pnv_pci_init_ioda_hub(np);
785 			found_ioda = 1;
786 		}
787 
788 		/* Look for p5ioc2 IO-Hubs */
789 		if (!found_ioda)
790 			for_each_compatible_node(np, NULL, "ibm,p5ioc2")
791 				pnv_pci_init_p5ioc2_hub(np);
792 
793 		/* Look for ioda2 built-in PHB3's */
794 		for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
795 			pnv_pci_init_ioda2_phb(np);
796 	}
797 
798 	/* Setup the linkage between OF nodes and PHBs */
799 	pci_devs_phb_init();
800 
801 	/* Configure IOMMU DMA hooks */
802 	ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
803 	ppc_md.tce_build = pnv_tce_build_vm;
804 	ppc_md.tce_free = pnv_tce_free_vm;
805 	ppc_md.tce_build_rm = pnv_tce_build_rm;
806 	ppc_md.tce_free_rm = pnv_tce_free_rm;
807 	ppc_md.tce_get = pnv_tce_get;
808 	ppc_md.pci_probe_mode = pnv_pci_probe_mode;
809 	set_pci_dma_ops(&dma_iommu_ops);
810 
811 	/* Configure MSIs */
812 #ifdef CONFIG_PCI_MSI
813 	ppc_md.msi_check_device = pnv_msi_check_device;
814 	ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
815 	ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
816 #endif
817 }
818 
819 static int tce_iommu_bus_notifier(struct notifier_block *nb,
820 		unsigned long action, void *data)
821 {
822 	struct device *dev = data;
823 
824 	switch (action) {
825 	case BUS_NOTIFY_ADD_DEVICE:
826 		return iommu_add_device(dev);
827 	case BUS_NOTIFY_DEL_DEVICE:
828 		if (dev->iommu_group)
829 			iommu_del_device(dev);
830 		return 0;
831 	default:
832 		return 0;
833 	}
834 }
835 
836 static struct notifier_block tce_iommu_bus_nb = {
837 	.notifier_call = tce_iommu_bus_notifier,
838 };
839 
840 static int __init tce_iommu_bus_notifier_init(void)
841 {
842 	bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
843 	return 0;
844 }
845 
846 subsys_initcall_sync(tce_iommu_bus_notifier_init);
847