1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/pci.h> 14 #include <linux/delay.h> 15 #include <linux/string.h> 16 #include <linux/init.h> 17 #include <linux/irq.h> 18 #include <linux/io.h> 19 #include <linux/msi.h> 20 #include <linux/iommu.h> 21 22 #include <asm/sections.h> 23 #include <asm/io.h> 24 #include <asm/prom.h> 25 #include <asm/pci-bridge.h> 26 #include <asm/machdep.h> 27 #include <asm/msi_bitmap.h> 28 #include <asm/ppc-pci.h> 29 #include <asm/pnv-pci.h> 30 #include <asm/opal.h> 31 #include <asm/iommu.h> 32 #include <asm/tce.h> 33 #include <asm/firmware.h> 34 #include <asm/eeh_event.h> 35 #include <asm/eeh.h> 36 37 #include "powernv.h" 38 #include "pci.h" 39 40 int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id) 41 { 42 struct device_node *parent = np; 43 u32 bdfn; 44 u64 phbid; 45 int ret; 46 47 ret = of_property_read_u32(np, "reg", &bdfn); 48 if (ret) 49 return -ENXIO; 50 51 bdfn = ((bdfn & 0x00ffff00) >> 8); 52 while ((parent = of_get_parent(parent))) { 53 if (!PCI_DN(parent)) { 54 of_node_put(parent); 55 break; 56 } 57 58 if (!of_device_is_compatible(parent, "ibm,ioda2-phb")) { 59 of_node_put(parent); 60 continue; 61 } 62 63 ret = of_property_read_u64(parent, "ibm,opal-phbid", &phbid); 64 if (ret) { 65 of_node_put(parent); 66 return -ENXIO; 67 } 68 69 *id = PCI_SLOT_ID(phbid, bdfn); 70 return 0; 71 } 72 73 return -ENODEV; 74 } 75 EXPORT_SYMBOL_GPL(pnv_pci_get_slot_id); 76 77 int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len) 78 { 79 int64_t rc; 80 81 if (!opal_check_token(OPAL_GET_DEVICE_TREE)) 82 return -ENXIO; 83 84 rc = opal_get_device_tree(phandle, (uint64_t)buf, len); 85 if (rc < OPAL_SUCCESS) 86 return -EIO; 87 88 return rc; 89 } 90 EXPORT_SYMBOL_GPL(pnv_pci_get_device_tree); 91 92 int pnv_pci_get_presence_state(uint64_t id, uint8_t *state) 93 { 94 int64_t rc; 95 96 if (!opal_check_token(OPAL_PCI_GET_PRESENCE_STATE)) 97 return -ENXIO; 98 99 rc = opal_pci_get_presence_state(id, (uint64_t)state); 100 if (rc != OPAL_SUCCESS) 101 return -EIO; 102 103 return 0; 104 } 105 EXPORT_SYMBOL_GPL(pnv_pci_get_presence_state); 106 107 int pnv_pci_get_power_state(uint64_t id, uint8_t *state) 108 { 109 int64_t rc; 110 111 if (!opal_check_token(OPAL_PCI_GET_POWER_STATE)) 112 return -ENXIO; 113 114 rc = opal_pci_get_power_state(id, (uint64_t)state); 115 if (rc != OPAL_SUCCESS) 116 return -EIO; 117 118 return 0; 119 } 120 EXPORT_SYMBOL_GPL(pnv_pci_get_power_state); 121 122 int pnv_pci_set_power_state(uint64_t id, uint8_t state, struct opal_msg *msg) 123 { 124 struct opal_msg m; 125 int token, ret; 126 int64_t rc; 127 128 if (!opal_check_token(OPAL_PCI_SET_POWER_STATE)) 129 return -ENXIO; 130 131 token = opal_async_get_token_interruptible(); 132 if (unlikely(token < 0)) 133 return token; 134 135 rc = opal_pci_set_power_state(token, id, (uint64_t)&state); 136 if (rc == OPAL_SUCCESS) { 137 ret = 0; 138 goto exit; 139 } else if (rc != OPAL_ASYNC_COMPLETION) { 140 ret = -EIO; 141 goto exit; 142 } 143 144 ret = opal_async_wait_response(token, &m); 145 if (ret < 0) 146 goto exit; 147 148 if (msg) { 149 ret = 1; 150 memcpy(msg, &m, sizeof(m)); 151 } 152 153 exit: 154 opal_async_release_token(token); 155 return ret; 156 } 157 EXPORT_SYMBOL_GPL(pnv_pci_set_power_state); 158 159 #ifdef CONFIG_PCI_MSI 160 int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 161 { 162 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 163 struct pnv_phb *phb = hose->private_data; 164 struct msi_desc *entry; 165 struct msi_msg msg; 166 int hwirq; 167 unsigned int virq; 168 int rc; 169 170 if (WARN_ON(!phb) || !phb->msi_bmp.bitmap) 171 return -ENODEV; 172 173 if (pdev->no_64bit_msi && !phb->msi32_support) 174 return -ENODEV; 175 176 for_each_pci_msi_entry(entry, pdev) { 177 if (!entry->msi_attrib.is_64 && !phb->msi32_support) { 178 pr_warn("%s: Supports only 64-bit MSIs\n", 179 pci_name(pdev)); 180 return -ENXIO; 181 } 182 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); 183 if (hwirq < 0) { 184 pr_warn("%s: Failed to find a free MSI\n", 185 pci_name(pdev)); 186 return -ENOSPC; 187 } 188 virq = irq_create_mapping(NULL, phb->msi_base + hwirq); 189 if (!virq) { 190 pr_warn("%s: Failed to map MSI to linux irq\n", 191 pci_name(pdev)); 192 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 193 return -ENOMEM; 194 } 195 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, 196 virq, entry->msi_attrib.is_64, &msg); 197 if (rc) { 198 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); 199 irq_dispose_mapping(virq); 200 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 201 return rc; 202 } 203 irq_set_msi_desc(virq, entry); 204 pci_write_msi_msg(virq, &msg); 205 } 206 return 0; 207 } 208 209 void pnv_teardown_msi_irqs(struct pci_dev *pdev) 210 { 211 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 212 struct pnv_phb *phb = hose->private_data; 213 struct msi_desc *entry; 214 irq_hw_number_t hwirq; 215 216 if (WARN_ON(!phb)) 217 return; 218 219 for_each_pci_msi_entry(entry, pdev) { 220 if (!entry->irq) 221 continue; 222 hwirq = virq_to_hw(entry->irq); 223 irq_set_msi_desc(entry->irq, NULL); 224 irq_dispose_mapping(entry->irq); 225 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1); 226 } 227 } 228 #endif /* CONFIG_PCI_MSI */ 229 230 /* Nicely print the contents of the PE State Tables (PEST). */ 231 static void pnv_pci_dump_pest(__be64 pestA[], __be64 pestB[], int pest_size) 232 { 233 __be64 prevA = ULONG_MAX, prevB = ULONG_MAX; 234 bool dup = false; 235 int i; 236 237 for (i = 0; i < pest_size; i++) { 238 __be64 peA = be64_to_cpu(pestA[i]); 239 __be64 peB = be64_to_cpu(pestB[i]); 240 241 if (peA != prevA || peB != prevB) { 242 if (dup) { 243 pr_info("PE[..%03x] A/B: as above\n", i-1); 244 dup = false; 245 } 246 prevA = peA; 247 prevB = peB; 248 if (peA & PNV_IODA_STOPPED_STATE || 249 peB & PNV_IODA_STOPPED_STATE) 250 pr_info("PE[%03x] A/B: %016llx %016llx\n", 251 i, peA, peB); 252 } else if (!dup && (peA & PNV_IODA_STOPPED_STATE || 253 peB & PNV_IODA_STOPPED_STATE)) { 254 dup = true; 255 } 256 } 257 } 258 259 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, 260 struct OpalIoPhbErrorCommon *common) 261 { 262 struct OpalIoP7IOCPhbErrorData *data; 263 264 data = (struct OpalIoP7IOCPhbErrorData *)common; 265 pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n", 266 hose->global_number, be32_to_cpu(common->version)); 267 268 if (data->brdgCtl) 269 pr_info("brdgCtl: %08x\n", 270 be32_to_cpu(data->brdgCtl)); 271 if (data->portStatusReg || data->rootCmplxStatus || 272 data->busAgentStatus) 273 pr_info("UtlSts: %08x %08x %08x\n", 274 be32_to_cpu(data->portStatusReg), 275 be32_to_cpu(data->rootCmplxStatus), 276 be32_to_cpu(data->busAgentStatus)); 277 if (data->deviceStatus || data->slotStatus || 278 data->linkStatus || data->devCmdStatus || 279 data->devSecStatus) 280 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 281 be32_to_cpu(data->deviceStatus), 282 be32_to_cpu(data->slotStatus), 283 be32_to_cpu(data->linkStatus), 284 be32_to_cpu(data->devCmdStatus), 285 be32_to_cpu(data->devSecStatus)); 286 if (data->rootErrorStatus || data->uncorrErrorStatus || 287 data->corrErrorStatus) 288 pr_info("RootErrSts: %08x %08x %08x\n", 289 be32_to_cpu(data->rootErrorStatus), 290 be32_to_cpu(data->uncorrErrorStatus), 291 be32_to_cpu(data->corrErrorStatus)); 292 if (data->tlpHdr1 || data->tlpHdr2 || 293 data->tlpHdr3 || data->tlpHdr4) 294 pr_info("RootErrLog: %08x %08x %08x %08x\n", 295 be32_to_cpu(data->tlpHdr1), 296 be32_to_cpu(data->tlpHdr2), 297 be32_to_cpu(data->tlpHdr3), 298 be32_to_cpu(data->tlpHdr4)); 299 if (data->sourceId || data->errorClass || 300 data->correlator) 301 pr_info("RootErrLog1: %08x %016llx %016llx\n", 302 be32_to_cpu(data->sourceId), 303 be64_to_cpu(data->errorClass), 304 be64_to_cpu(data->correlator)); 305 if (data->p7iocPlssr || data->p7iocCsr) 306 pr_info("PhbSts: %016llx %016llx\n", 307 be64_to_cpu(data->p7iocPlssr), 308 be64_to_cpu(data->p7iocCsr)); 309 if (data->lemFir) 310 pr_info("Lem: %016llx %016llx %016llx\n", 311 be64_to_cpu(data->lemFir), 312 be64_to_cpu(data->lemErrorMask), 313 be64_to_cpu(data->lemWOF)); 314 if (data->phbErrorStatus) 315 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 316 be64_to_cpu(data->phbErrorStatus), 317 be64_to_cpu(data->phbFirstErrorStatus), 318 be64_to_cpu(data->phbErrorLog0), 319 be64_to_cpu(data->phbErrorLog1)); 320 if (data->mmioErrorStatus) 321 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 322 be64_to_cpu(data->mmioErrorStatus), 323 be64_to_cpu(data->mmioFirstErrorStatus), 324 be64_to_cpu(data->mmioErrorLog0), 325 be64_to_cpu(data->mmioErrorLog1)); 326 if (data->dma0ErrorStatus) 327 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 328 be64_to_cpu(data->dma0ErrorStatus), 329 be64_to_cpu(data->dma0FirstErrorStatus), 330 be64_to_cpu(data->dma0ErrorLog0), 331 be64_to_cpu(data->dma0ErrorLog1)); 332 if (data->dma1ErrorStatus) 333 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 334 be64_to_cpu(data->dma1ErrorStatus), 335 be64_to_cpu(data->dma1FirstErrorStatus), 336 be64_to_cpu(data->dma1ErrorLog0), 337 be64_to_cpu(data->dma1ErrorLog1)); 338 339 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_P7IOC_NUM_PEST_REGS); 340 } 341 342 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, 343 struct OpalIoPhbErrorCommon *common) 344 { 345 struct OpalIoPhb3ErrorData *data; 346 347 data = (struct OpalIoPhb3ErrorData*)common; 348 pr_info("PHB3 PHB#%x Diag-data (Version: %d)\n", 349 hose->global_number, be32_to_cpu(common->version)); 350 if (data->brdgCtl) 351 pr_info("brdgCtl: %08x\n", 352 be32_to_cpu(data->brdgCtl)); 353 if (data->portStatusReg || data->rootCmplxStatus || 354 data->busAgentStatus) 355 pr_info("UtlSts: %08x %08x %08x\n", 356 be32_to_cpu(data->portStatusReg), 357 be32_to_cpu(data->rootCmplxStatus), 358 be32_to_cpu(data->busAgentStatus)); 359 if (data->deviceStatus || data->slotStatus || 360 data->linkStatus || data->devCmdStatus || 361 data->devSecStatus) 362 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 363 be32_to_cpu(data->deviceStatus), 364 be32_to_cpu(data->slotStatus), 365 be32_to_cpu(data->linkStatus), 366 be32_to_cpu(data->devCmdStatus), 367 be32_to_cpu(data->devSecStatus)); 368 if (data->rootErrorStatus || data->uncorrErrorStatus || 369 data->corrErrorStatus) 370 pr_info("RootErrSts: %08x %08x %08x\n", 371 be32_to_cpu(data->rootErrorStatus), 372 be32_to_cpu(data->uncorrErrorStatus), 373 be32_to_cpu(data->corrErrorStatus)); 374 if (data->tlpHdr1 || data->tlpHdr2 || 375 data->tlpHdr3 || data->tlpHdr4) 376 pr_info("RootErrLog: %08x %08x %08x %08x\n", 377 be32_to_cpu(data->tlpHdr1), 378 be32_to_cpu(data->tlpHdr2), 379 be32_to_cpu(data->tlpHdr3), 380 be32_to_cpu(data->tlpHdr4)); 381 if (data->sourceId || data->errorClass || 382 data->correlator) 383 pr_info("RootErrLog1: %08x %016llx %016llx\n", 384 be32_to_cpu(data->sourceId), 385 be64_to_cpu(data->errorClass), 386 be64_to_cpu(data->correlator)); 387 if (data->nFir) 388 pr_info("nFir: %016llx %016llx %016llx\n", 389 be64_to_cpu(data->nFir), 390 be64_to_cpu(data->nFirMask), 391 be64_to_cpu(data->nFirWOF)); 392 if (data->phbPlssr || data->phbCsr) 393 pr_info("PhbSts: %016llx %016llx\n", 394 be64_to_cpu(data->phbPlssr), 395 be64_to_cpu(data->phbCsr)); 396 if (data->lemFir) 397 pr_info("Lem: %016llx %016llx %016llx\n", 398 be64_to_cpu(data->lemFir), 399 be64_to_cpu(data->lemErrorMask), 400 be64_to_cpu(data->lemWOF)); 401 if (data->phbErrorStatus) 402 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 403 be64_to_cpu(data->phbErrorStatus), 404 be64_to_cpu(data->phbFirstErrorStatus), 405 be64_to_cpu(data->phbErrorLog0), 406 be64_to_cpu(data->phbErrorLog1)); 407 if (data->mmioErrorStatus) 408 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 409 be64_to_cpu(data->mmioErrorStatus), 410 be64_to_cpu(data->mmioFirstErrorStatus), 411 be64_to_cpu(data->mmioErrorLog0), 412 be64_to_cpu(data->mmioErrorLog1)); 413 if (data->dma0ErrorStatus) 414 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 415 be64_to_cpu(data->dma0ErrorStatus), 416 be64_to_cpu(data->dma0FirstErrorStatus), 417 be64_to_cpu(data->dma0ErrorLog0), 418 be64_to_cpu(data->dma0ErrorLog1)); 419 if (data->dma1ErrorStatus) 420 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 421 be64_to_cpu(data->dma1ErrorStatus), 422 be64_to_cpu(data->dma1FirstErrorStatus), 423 be64_to_cpu(data->dma1ErrorLog0), 424 be64_to_cpu(data->dma1ErrorLog1)); 425 426 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_PHB3_NUM_PEST_REGS); 427 } 428 429 static void pnv_pci_dump_phb4_diag_data(struct pci_controller *hose, 430 struct OpalIoPhbErrorCommon *common) 431 { 432 struct OpalIoPhb4ErrorData *data; 433 434 data = (struct OpalIoPhb4ErrorData*)common; 435 pr_info("PHB4 PHB#%d Diag-data (Version: %d)\n", 436 hose->global_number, be32_to_cpu(common->version)); 437 if (data->brdgCtl) 438 pr_info("brdgCtl: %08x\n", 439 be32_to_cpu(data->brdgCtl)); 440 if (data->deviceStatus || data->slotStatus || 441 data->linkStatus || data->devCmdStatus || 442 data->devSecStatus) 443 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 444 be32_to_cpu(data->deviceStatus), 445 be32_to_cpu(data->slotStatus), 446 be32_to_cpu(data->linkStatus), 447 be32_to_cpu(data->devCmdStatus), 448 be32_to_cpu(data->devSecStatus)); 449 if (data->rootErrorStatus || data->uncorrErrorStatus || 450 data->corrErrorStatus) 451 pr_info("RootErrSts: %08x %08x %08x\n", 452 be32_to_cpu(data->rootErrorStatus), 453 be32_to_cpu(data->uncorrErrorStatus), 454 be32_to_cpu(data->corrErrorStatus)); 455 if (data->tlpHdr1 || data->tlpHdr2 || 456 data->tlpHdr3 || data->tlpHdr4) 457 pr_info("RootErrLog: %08x %08x %08x %08x\n", 458 be32_to_cpu(data->tlpHdr1), 459 be32_to_cpu(data->tlpHdr2), 460 be32_to_cpu(data->tlpHdr3), 461 be32_to_cpu(data->tlpHdr4)); 462 if (data->sourceId) 463 pr_info("sourceId: %08x\n", be32_to_cpu(data->sourceId)); 464 if (data->nFir) 465 pr_info("nFir: %016llx %016llx %016llx\n", 466 be64_to_cpu(data->nFir), 467 be64_to_cpu(data->nFirMask), 468 be64_to_cpu(data->nFirWOF)); 469 if (data->phbPlssr || data->phbCsr) 470 pr_info("PhbSts: %016llx %016llx\n", 471 be64_to_cpu(data->phbPlssr), 472 be64_to_cpu(data->phbCsr)); 473 if (data->lemFir) 474 pr_info("Lem: %016llx %016llx %016llx\n", 475 be64_to_cpu(data->lemFir), 476 be64_to_cpu(data->lemErrorMask), 477 be64_to_cpu(data->lemWOF)); 478 if (data->phbErrorStatus) 479 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 480 be64_to_cpu(data->phbErrorStatus), 481 be64_to_cpu(data->phbFirstErrorStatus), 482 be64_to_cpu(data->phbErrorLog0), 483 be64_to_cpu(data->phbErrorLog1)); 484 if (data->phbTxeErrorStatus) 485 pr_info("PhbTxeErr: %016llx %016llx %016llx %016llx\n", 486 be64_to_cpu(data->phbTxeErrorStatus), 487 be64_to_cpu(data->phbTxeFirstErrorStatus), 488 be64_to_cpu(data->phbTxeErrorLog0), 489 be64_to_cpu(data->phbTxeErrorLog1)); 490 if (data->phbRxeArbErrorStatus) 491 pr_info("RxeArbErr: %016llx %016llx %016llx %016llx\n", 492 be64_to_cpu(data->phbRxeArbErrorStatus), 493 be64_to_cpu(data->phbRxeArbFirstErrorStatus), 494 be64_to_cpu(data->phbRxeArbErrorLog0), 495 be64_to_cpu(data->phbRxeArbErrorLog1)); 496 if (data->phbRxeMrgErrorStatus) 497 pr_info("RxeMrgErr: %016llx %016llx %016llx %016llx\n", 498 be64_to_cpu(data->phbRxeMrgErrorStatus), 499 be64_to_cpu(data->phbRxeMrgFirstErrorStatus), 500 be64_to_cpu(data->phbRxeMrgErrorLog0), 501 be64_to_cpu(data->phbRxeMrgErrorLog1)); 502 if (data->phbRxeTceErrorStatus) 503 pr_info("RxeTceErr: %016llx %016llx %016llx %016llx\n", 504 be64_to_cpu(data->phbRxeTceErrorStatus), 505 be64_to_cpu(data->phbRxeTceFirstErrorStatus), 506 be64_to_cpu(data->phbRxeTceErrorLog0), 507 be64_to_cpu(data->phbRxeTceErrorLog1)); 508 509 if (data->phbPblErrorStatus) 510 pr_info("PblErr: %016llx %016llx %016llx %016llx\n", 511 be64_to_cpu(data->phbPblErrorStatus), 512 be64_to_cpu(data->phbPblFirstErrorStatus), 513 be64_to_cpu(data->phbPblErrorLog0), 514 be64_to_cpu(data->phbPblErrorLog1)); 515 if (data->phbPcieDlpErrorStatus) 516 pr_info("PcieDlp: %016llx %016llx %016llx\n", 517 be64_to_cpu(data->phbPcieDlpErrorLog1), 518 be64_to_cpu(data->phbPcieDlpErrorLog2), 519 be64_to_cpu(data->phbPcieDlpErrorStatus)); 520 if (data->phbRegbErrorStatus) 521 pr_info("RegbErr: %016llx %016llx %016llx %016llx\n", 522 be64_to_cpu(data->phbRegbErrorStatus), 523 be64_to_cpu(data->phbRegbFirstErrorStatus), 524 be64_to_cpu(data->phbRegbErrorLog0), 525 be64_to_cpu(data->phbRegbErrorLog1)); 526 527 528 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_PHB4_NUM_PEST_REGS); 529 } 530 531 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 532 unsigned char *log_buff) 533 { 534 struct OpalIoPhbErrorCommon *common; 535 536 if (!hose || !log_buff) 537 return; 538 539 common = (struct OpalIoPhbErrorCommon *)log_buff; 540 switch (be32_to_cpu(common->ioType)) { 541 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: 542 pnv_pci_dump_p7ioc_diag_data(hose, common); 543 break; 544 case OPAL_PHB_ERROR_DATA_TYPE_PHB3: 545 pnv_pci_dump_phb3_diag_data(hose, common); 546 break; 547 case OPAL_PHB_ERROR_DATA_TYPE_PHB4: 548 pnv_pci_dump_phb4_diag_data(hose, common); 549 break; 550 default: 551 pr_warn("%s: Unrecognized ioType %d\n", 552 __func__, be32_to_cpu(common->ioType)); 553 } 554 } 555 556 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) 557 { 558 unsigned long flags, rc; 559 int has_diag, ret = 0; 560 561 spin_lock_irqsave(&phb->lock, flags); 562 563 /* Fetch PHB diag-data */ 564 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, 565 phb->diag_data_size); 566 has_diag = (rc == OPAL_SUCCESS); 567 568 /* If PHB supports compound PE, to handle it */ 569 if (phb->unfreeze_pe) { 570 ret = phb->unfreeze_pe(phb, 571 pe_no, 572 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 573 } else { 574 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 575 pe_no, 576 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 577 if (rc) { 578 pr_warn("%s: Failure %ld clearing frozen " 579 "PHB#%x-PE#%x\n", 580 __func__, rc, phb->hose->global_number, 581 pe_no); 582 ret = -EIO; 583 } 584 } 585 586 /* 587 * For now, let's only display the diag buffer when we fail to clear 588 * the EEH status. We'll do more sensible things later when we have 589 * proper EEH support. We need to make sure we don't pollute ourselves 590 * with the normal errors generated when probing empty slots 591 */ 592 if (has_diag && ret) 593 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); 594 595 spin_unlock_irqrestore(&phb->lock, flags); 596 } 597 598 static void pnv_pci_config_check_eeh(struct pci_dn *pdn) 599 { 600 struct pnv_phb *phb = pdn->phb->private_data; 601 u8 fstate; 602 __be16 pcierr; 603 unsigned int pe_no; 604 s64 rc; 605 606 /* 607 * Get the PE#. During the PCI probe stage, we might not 608 * setup that yet. So all ER errors should be mapped to 609 * reserved PE. 610 */ 611 pe_no = pdn->pe_number; 612 if (pe_no == IODA_INVALID_PE) { 613 pe_no = phb->ioda.reserved_pe_idx; 614 } 615 616 /* 617 * Fetch frozen state. If the PHB support compound PE, 618 * we need handle that case. 619 */ 620 if (phb->get_pe_state) { 621 fstate = phb->get_pe_state(phb, pe_no); 622 } else { 623 rc = opal_pci_eeh_freeze_status(phb->opal_id, 624 pe_no, 625 &fstate, 626 &pcierr, 627 NULL); 628 if (rc) { 629 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n", 630 __func__, rc, phb->hose->global_number, pe_no); 631 return; 632 } 633 } 634 635 pr_devel(" -> EEH check, bdfn=%04x PE#%x fstate=%x\n", 636 (pdn->busno << 8) | (pdn->devfn), pe_no, fstate); 637 638 /* Clear the frozen state if applicable */ 639 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE || 640 fstate == OPAL_EEH_STOPPED_DMA_FREEZE || 641 fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) { 642 /* 643 * If PHB supports compound PE, freeze it for 644 * consistency. 645 */ 646 if (phb->freeze_pe) 647 phb->freeze_pe(phb, pe_no); 648 649 pnv_pci_handle_eeh_config(phb, pe_no); 650 } 651 } 652 653 int pnv_pci_cfg_read(struct pci_dn *pdn, 654 int where, int size, u32 *val) 655 { 656 struct pnv_phb *phb = pdn->phb->private_data; 657 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 658 s64 rc; 659 660 switch (size) { 661 case 1: { 662 u8 v8; 663 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); 664 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; 665 break; 666 } 667 case 2: { 668 __be16 v16; 669 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, 670 &v16); 671 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; 672 break; 673 } 674 case 4: { 675 __be32 v32; 676 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); 677 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; 678 break; 679 } 680 default: 681 return PCIBIOS_FUNC_NOT_SUPPORTED; 682 } 683 684 pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 685 __func__, pdn->busno, pdn->devfn, where, size, *val); 686 return PCIBIOS_SUCCESSFUL; 687 } 688 689 int pnv_pci_cfg_write(struct pci_dn *pdn, 690 int where, int size, u32 val) 691 { 692 struct pnv_phb *phb = pdn->phb->private_data; 693 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 694 695 pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 696 __func__, pdn->busno, pdn->devfn, where, size, val); 697 switch (size) { 698 case 1: 699 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); 700 break; 701 case 2: 702 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); 703 break; 704 case 4: 705 opal_pci_config_write_word(phb->opal_id, bdfn, where, val); 706 break; 707 default: 708 return PCIBIOS_FUNC_NOT_SUPPORTED; 709 } 710 711 return PCIBIOS_SUCCESSFUL; 712 } 713 714 #if CONFIG_EEH 715 static bool pnv_pci_cfg_check(struct pci_dn *pdn) 716 { 717 struct eeh_dev *edev = NULL; 718 struct pnv_phb *phb = pdn->phb->private_data; 719 720 /* EEH not enabled ? */ 721 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 722 return true; 723 724 /* PE reset or device removed ? */ 725 edev = pdn->edev; 726 if (edev) { 727 if (edev->pe && 728 (edev->pe->state & EEH_PE_CFG_BLOCKED)) 729 return false; 730 731 if (edev->mode & EEH_DEV_REMOVED) 732 return false; 733 } 734 735 return true; 736 } 737 #else 738 static inline pnv_pci_cfg_check(struct pci_dn *pdn) 739 { 740 return true; 741 } 742 #endif /* CONFIG_EEH */ 743 744 static int pnv_pci_read_config(struct pci_bus *bus, 745 unsigned int devfn, 746 int where, int size, u32 *val) 747 { 748 struct pci_dn *pdn; 749 struct pnv_phb *phb; 750 int ret; 751 752 *val = 0xFFFFFFFF; 753 pdn = pci_get_pdn_by_devfn(bus, devfn); 754 if (!pdn) 755 return PCIBIOS_DEVICE_NOT_FOUND; 756 757 if (!pnv_pci_cfg_check(pdn)) 758 return PCIBIOS_DEVICE_NOT_FOUND; 759 760 ret = pnv_pci_cfg_read(pdn, where, size, val); 761 phb = pdn->phb->private_data; 762 if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) { 763 if (*val == EEH_IO_ERROR_VALUE(size) && 764 eeh_dev_check_failure(pdn->edev)) 765 return PCIBIOS_DEVICE_NOT_FOUND; 766 } else { 767 pnv_pci_config_check_eeh(pdn); 768 } 769 770 return ret; 771 } 772 773 static int pnv_pci_write_config(struct pci_bus *bus, 774 unsigned int devfn, 775 int where, int size, u32 val) 776 { 777 struct pci_dn *pdn; 778 struct pnv_phb *phb; 779 int ret; 780 781 pdn = pci_get_pdn_by_devfn(bus, devfn); 782 if (!pdn) 783 return PCIBIOS_DEVICE_NOT_FOUND; 784 785 if (!pnv_pci_cfg_check(pdn)) 786 return PCIBIOS_DEVICE_NOT_FOUND; 787 788 ret = pnv_pci_cfg_write(pdn, where, size, val); 789 phb = pdn->phb->private_data; 790 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 791 pnv_pci_config_check_eeh(pdn); 792 793 return ret; 794 } 795 796 struct pci_ops pnv_pci_ops = { 797 .read = pnv_pci_read_config, 798 .write = pnv_pci_write_config, 799 }; 800 801 static __be64 *pnv_tce(struct iommu_table *tbl, long idx) 802 { 803 __be64 *tmp = ((__be64 *)tbl->it_base); 804 int level = tbl->it_indirect_levels; 805 const long shift = ilog2(tbl->it_level_size); 806 unsigned long mask = (tbl->it_level_size - 1) << (level * shift); 807 808 while (level) { 809 int n = (idx & mask) >> (level * shift); 810 unsigned long tce = be64_to_cpu(tmp[n]); 811 812 tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE)); 813 idx &= ~mask; 814 mask >>= shift; 815 --level; 816 } 817 818 return tmp + idx; 819 } 820 821 int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 822 unsigned long uaddr, enum dma_data_direction direction, 823 unsigned long attrs) 824 { 825 u64 proto_tce = iommu_direction_to_tce_perm(direction); 826 u64 rpn = __pa(uaddr) >> tbl->it_page_shift; 827 long i; 828 829 if (proto_tce & TCE_PCI_WRITE) 830 proto_tce |= TCE_PCI_READ; 831 832 for (i = 0; i < npages; i++) { 833 unsigned long newtce = proto_tce | 834 ((rpn + i) << tbl->it_page_shift); 835 unsigned long idx = index - tbl->it_offset + i; 836 837 *(pnv_tce(tbl, idx)) = cpu_to_be64(newtce); 838 } 839 840 return 0; 841 } 842 843 #ifdef CONFIG_IOMMU_API 844 int pnv_tce_xchg(struct iommu_table *tbl, long index, 845 unsigned long *hpa, enum dma_data_direction *direction) 846 { 847 u64 proto_tce = iommu_direction_to_tce_perm(*direction); 848 unsigned long newtce = *hpa | proto_tce, oldtce; 849 unsigned long idx = index - tbl->it_offset; 850 851 BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl)); 852 853 if (newtce & TCE_PCI_WRITE) 854 newtce |= TCE_PCI_READ; 855 856 oldtce = be64_to_cpu(xchg(pnv_tce(tbl, idx), cpu_to_be64(newtce))); 857 *hpa = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE); 858 *direction = iommu_tce_direction(oldtce); 859 860 return 0; 861 } 862 #endif 863 864 void pnv_tce_free(struct iommu_table *tbl, long index, long npages) 865 { 866 long i; 867 868 for (i = 0; i < npages; i++) { 869 unsigned long idx = index - tbl->it_offset + i; 870 871 *(pnv_tce(tbl, idx)) = cpu_to_be64(0); 872 } 873 } 874 875 unsigned long pnv_tce_get(struct iommu_table *tbl, long index) 876 { 877 return be64_to_cpu(*(pnv_tce(tbl, index - tbl->it_offset))); 878 } 879 880 struct iommu_table *pnv_pci_table_alloc(int nid) 881 { 882 struct iommu_table *tbl; 883 884 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, nid); 885 if (!tbl) 886 return NULL; 887 888 INIT_LIST_HEAD_RCU(&tbl->it_group_list); 889 kref_init(&tbl->it_kref); 890 891 return tbl; 892 } 893 894 long pnv_pci_link_table_and_group(int node, int num, 895 struct iommu_table *tbl, 896 struct iommu_table_group *table_group) 897 { 898 struct iommu_table_group_link *tgl = NULL; 899 900 if (WARN_ON(!tbl || !table_group)) 901 return -EINVAL; 902 903 tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL, 904 node); 905 if (!tgl) 906 return -ENOMEM; 907 908 tgl->table_group = table_group; 909 list_add_rcu(&tgl->next, &tbl->it_group_list); 910 911 table_group->tables[num] = tbl; 912 913 return 0; 914 } 915 916 static void pnv_iommu_table_group_link_free(struct rcu_head *head) 917 { 918 struct iommu_table_group_link *tgl = container_of(head, 919 struct iommu_table_group_link, rcu); 920 921 kfree(tgl); 922 } 923 924 void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 925 struct iommu_table_group *table_group) 926 { 927 long i; 928 bool found; 929 struct iommu_table_group_link *tgl; 930 931 if (!tbl || !table_group) 932 return; 933 934 /* Remove link to a group from table's list of attached groups */ 935 found = false; 936 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { 937 if (tgl->table_group == table_group) { 938 list_del_rcu(&tgl->next); 939 call_rcu(&tgl->rcu, pnv_iommu_table_group_link_free); 940 found = true; 941 break; 942 } 943 } 944 if (WARN_ON(!found)) 945 return; 946 947 /* Clean a pointer to iommu_table in iommu_table_group::tables[] */ 948 found = false; 949 for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { 950 if (table_group->tables[i] == tbl) { 951 table_group->tables[i] = NULL; 952 found = true; 953 break; 954 } 955 } 956 WARN_ON(!found); 957 } 958 959 void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 960 void *tce_mem, u64 tce_size, 961 u64 dma_offset, unsigned page_shift) 962 { 963 tbl->it_blocksize = 16; 964 tbl->it_base = (unsigned long)tce_mem; 965 tbl->it_page_shift = page_shift; 966 tbl->it_offset = dma_offset >> tbl->it_page_shift; 967 tbl->it_index = 0; 968 tbl->it_size = tce_size >> 3; 969 tbl->it_busno = 0; 970 tbl->it_type = TCE_PCI; 971 } 972 973 void pnv_pci_dma_dev_setup(struct pci_dev *pdev) 974 { 975 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 976 struct pnv_phb *phb = hose->private_data; 977 #ifdef CONFIG_PCI_IOV 978 struct pnv_ioda_pe *pe; 979 struct pci_dn *pdn; 980 981 /* Fix the VF pdn PE number */ 982 if (pdev->is_virtfn) { 983 pdn = pci_get_pdn(pdev); 984 WARN_ON(pdn->pe_number != IODA_INVALID_PE); 985 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 986 if (pe->rid == ((pdev->bus->number << 8) | 987 (pdev->devfn & 0xff))) { 988 pdn->pe_number = pe->pe_number; 989 pe->pdev = pdev; 990 break; 991 } 992 } 993 } 994 #endif /* CONFIG_PCI_IOV */ 995 996 if (phb && phb->dma_dev_setup) 997 phb->dma_dev_setup(phb, pdev); 998 } 999 1000 void pnv_pci_dma_bus_setup(struct pci_bus *bus) 1001 { 1002 struct pci_controller *hose = bus->sysdata; 1003 struct pnv_phb *phb = hose->private_data; 1004 struct pnv_ioda_pe *pe; 1005 1006 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 1007 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) 1008 continue; 1009 1010 if (!pe->pbus) 1011 continue; 1012 1013 if (bus->number == ((pe->rid >> 8) & 0xFF)) { 1014 pe->pbus = bus; 1015 break; 1016 } 1017 } 1018 } 1019 1020 void pnv_pci_shutdown(void) 1021 { 1022 struct pci_controller *hose; 1023 1024 list_for_each_entry(hose, &hose_list, list_node) 1025 if (hose->controller_ops.shutdown) 1026 hose->controller_ops.shutdown(hose); 1027 } 1028 1029 /* Fixup wrong class code in p7ioc and p8 root complex */ 1030 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) 1031 { 1032 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 1033 } 1034 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); 1035 1036 void __init pnv_pci_init(void) 1037 { 1038 struct device_node *np; 1039 1040 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); 1041 1042 /* If we don't have OPAL, eg. in sim, just skip PCI probe */ 1043 if (!firmware_has_feature(FW_FEATURE_OPAL)) 1044 return; 1045 1046 /* Look for IODA IO-Hubs. */ 1047 for_each_compatible_node(np, NULL, "ibm,ioda-hub") { 1048 pnv_pci_init_ioda_hub(np); 1049 } 1050 1051 /* Look for ioda2 built-in PHB3's */ 1052 for_each_compatible_node(np, NULL, "ibm,ioda2-phb") 1053 pnv_pci_init_ioda2_phb(np); 1054 1055 /* Look for ioda3 built-in PHB4's, we treat them as IODA2 */ 1056 for_each_compatible_node(np, NULL, "ibm,ioda3-phb") 1057 pnv_pci_init_ioda2_phb(np); 1058 1059 /* Look for NPU PHBs */ 1060 for_each_compatible_node(np, NULL, "ibm,ioda2-npu-phb") 1061 pnv_pci_init_npu_phb(np); 1062 1063 /* 1064 * Look for NPU2 PHBs which we treat mostly as NPU PHBs with 1065 * the exception of TCE kill which requires an OPAL call. 1066 */ 1067 for_each_compatible_node(np, NULL, "ibm,ioda2-npu2-phb") 1068 pnv_pci_init_npu_phb(np); 1069 1070 /* Configure IOMMU DMA hooks */ 1071 set_pci_dma_ops(&dma_iommu_ops); 1072 } 1073 1074 machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init); 1075