1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Currently supports only P5IOC2 5 * 6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/delay.h> 17 #include <linux/string.h> 18 #include <linux/init.h> 19 #include <linux/bootmem.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/msi.h> 23 #include <linux/iommu.h> 24 25 #include <asm/sections.h> 26 #include <asm/io.h> 27 #include <asm/prom.h> 28 #include <asm/pci-bridge.h> 29 #include <asm/machdep.h> 30 #include <asm/msi_bitmap.h> 31 #include <asm/ppc-pci.h> 32 #include <asm/opal.h> 33 #include <asm/iommu.h> 34 #include <asm/tce.h> 35 #include <asm/firmware.h> 36 #include <asm/eeh_event.h> 37 #include <asm/eeh.h> 38 39 #include "powernv.h" 40 #include "pci.h" 41 42 /* Delay in usec */ 43 #define PCI_RESET_DELAY_US 3000000 44 45 #define cfg_dbg(fmt...) do { } while(0) 46 //#define cfg_dbg(fmt...) printk(fmt) 47 48 #ifdef CONFIG_PCI_MSI 49 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type) 50 { 51 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 52 struct pnv_phb *phb = hose->private_data; 53 struct pci_dn *pdn = pci_get_pdn(pdev); 54 55 if (pdn && pdn->force_32bit_msi && !phb->msi32_support) 56 return -ENODEV; 57 58 return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV; 59 } 60 61 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 62 { 63 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 64 struct pnv_phb *phb = hose->private_data; 65 struct msi_desc *entry; 66 struct msi_msg msg; 67 int hwirq; 68 unsigned int virq; 69 int rc; 70 71 if (WARN_ON(!phb)) 72 return -ENODEV; 73 74 list_for_each_entry(entry, &pdev->msi_list, list) { 75 if (!entry->msi_attrib.is_64 && !phb->msi32_support) { 76 pr_warn("%s: Supports only 64-bit MSIs\n", 77 pci_name(pdev)); 78 return -ENXIO; 79 } 80 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); 81 if (hwirq < 0) { 82 pr_warn("%s: Failed to find a free MSI\n", 83 pci_name(pdev)); 84 return -ENOSPC; 85 } 86 virq = irq_create_mapping(NULL, phb->msi_base + hwirq); 87 if (virq == NO_IRQ) { 88 pr_warn("%s: Failed to map MSI to linux irq\n", 89 pci_name(pdev)); 90 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 91 return -ENOMEM; 92 } 93 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, 94 virq, entry->msi_attrib.is_64, &msg); 95 if (rc) { 96 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); 97 irq_dispose_mapping(virq); 98 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 99 return rc; 100 } 101 irq_set_msi_desc(virq, entry); 102 write_msi_msg(virq, &msg); 103 } 104 return 0; 105 } 106 107 static void pnv_teardown_msi_irqs(struct pci_dev *pdev) 108 { 109 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 110 struct pnv_phb *phb = hose->private_data; 111 struct msi_desc *entry; 112 113 if (WARN_ON(!phb)) 114 return; 115 116 list_for_each_entry(entry, &pdev->msi_list, list) { 117 if (entry->irq == NO_IRQ) 118 continue; 119 irq_set_msi_desc(entry->irq, NULL); 120 msi_bitmap_free_hwirqs(&phb->msi_bmp, 121 virq_to_hw(entry->irq) - phb->msi_base, 1); 122 irq_dispose_mapping(entry->irq); 123 } 124 } 125 #endif /* CONFIG_PCI_MSI */ 126 127 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, 128 struct OpalIoPhbErrorCommon *common) 129 { 130 struct OpalIoP7IOCPhbErrorData *data; 131 int i; 132 133 data = (struct OpalIoP7IOCPhbErrorData *)common; 134 pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n", 135 hose->global_number, be32_to_cpu(common->version)); 136 137 if (data->brdgCtl) 138 pr_info("brdgCtl: %08x\n", 139 be32_to_cpu(data->brdgCtl)); 140 if (data->portStatusReg || data->rootCmplxStatus || 141 data->busAgentStatus) 142 pr_info("UtlSts: %08x %08x %08x\n", 143 be32_to_cpu(data->portStatusReg), 144 be32_to_cpu(data->rootCmplxStatus), 145 be32_to_cpu(data->busAgentStatus)); 146 if (data->deviceStatus || data->slotStatus || 147 data->linkStatus || data->devCmdStatus || 148 data->devSecStatus) 149 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 150 be32_to_cpu(data->deviceStatus), 151 be32_to_cpu(data->slotStatus), 152 be32_to_cpu(data->linkStatus), 153 be32_to_cpu(data->devCmdStatus), 154 be32_to_cpu(data->devSecStatus)); 155 if (data->rootErrorStatus || data->uncorrErrorStatus || 156 data->corrErrorStatus) 157 pr_info("RootErrSts: %08x %08x %08x\n", 158 be32_to_cpu(data->rootErrorStatus), 159 be32_to_cpu(data->uncorrErrorStatus), 160 be32_to_cpu(data->corrErrorStatus)); 161 if (data->tlpHdr1 || data->tlpHdr2 || 162 data->tlpHdr3 || data->tlpHdr4) 163 pr_info("RootErrLog: %08x %08x %08x %08x\n", 164 be32_to_cpu(data->tlpHdr1), 165 be32_to_cpu(data->tlpHdr2), 166 be32_to_cpu(data->tlpHdr3), 167 be32_to_cpu(data->tlpHdr4)); 168 if (data->sourceId || data->errorClass || 169 data->correlator) 170 pr_info("RootErrLog1: %08x %016llx %016llx\n", 171 be32_to_cpu(data->sourceId), 172 be64_to_cpu(data->errorClass), 173 be64_to_cpu(data->correlator)); 174 if (data->p7iocPlssr || data->p7iocCsr) 175 pr_info("PhbSts: %016llx %016llx\n", 176 be64_to_cpu(data->p7iocPlssr), 177 be64_to_cpu(data->p7iocCsr)); 178 if (data->lemFir) 179 pr_info("Lem: %016llx %016llx %016llx\n", 180 be64_to_cpu(data->lemFir), 181 be64_to_cpu(data->lemErrorMask), 182 be64_to_cpu(data->lemWOF)); 183 if (data->phbErrorStatus) 184 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 185 be64_to_cpu(data->phbErrorStatus), 186 be64_to_cpu(data->phbFirstErrorStatus), 187 be64_to_cpu(data->phbErrorLog0), 188 be64_to_cpu(data->phbErrorLog1)); 189 if (data->mmioErrorStatus) 190 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 191 be64_to_cpu(data->mmioErrorStatus), 192 be64_to_cpu(data->mmioFirstErrorStatus), 193 be64_to_cpu(data->mmioErrorLog0), 194 be64_to_cpu(data->mmioErrorLog1)); 195 if (data->dma0ErrorStatus) 196 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 197 be64_to_cpu(data->dma0ErrorStatus), 198 be64_to_cpu(data->dma0FirstErrorStatus), 199 be64_to_cpu(data->dma0ErrorLog0), 200 be64_to_cpu(data->dma0ErrorLog1)); 201 if (data->dma1ErrorStatus) 202 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 203 be64_to_cpu(data->dma1ErrorStatus), 204 be64_to_cpu(data->dma1FirstErrorStatus), 205 be64_to_cpu(data->dma1ErrorLog0), 206 be64_to_cpu(data->dma1ErrorLog1)); 207 208 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { 209 if ((data->pestA[i] >> 63) == 0 && 210 (data->pestB[i] >> 63) == 0) 211 continue; 212 213 pr_info("PE[%3d] A/B: %016llx %016llx\n", 214 i, be64_to_cpu(data->pestA[i]), 215 be64_to_cpu(data->pestB[i])); 216 } 217 } 218 219 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, 220 struct OpalIoPhbErrorCommon *common) 221 { 222 struct OpalIoPhb3ErrorData *data; 223 int i; 224 225 data = (struct OpalIoPhb3ErrorData*)common; 226 pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n", 227 hose->global_number, be32_to_cpu(common->version)); 228 if (data->brdgCtl) 229 pr_info("brdgCtl: %08x\n", 230 be32_to_cpu(data->brdgCtl)); 231 if (data->portStatusReg || data->rootCmplxStatus || 232 data->busAgentStatus) 233 pr_info("UtlSts: %08x %08x %08x\n", 234 be32_to_cpu(data->portStatusReg), 235 be32_to_cpu(data->rootCmplxStatus), 236 be32_to_cpu(data->busAgentStatus)); 237 if (data->deviceStatus || data->slotStatus || 238 data->linkStatus || data->devCmdStatus || 239 data->devSecStatus) 240 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 241 be32_to_cpu(data->deviceStatus), 242 be32_to_cpu(data->slotStatus), 243 be32_to_cpu(data->linkStatus), 244 be32_to_cpu(data->devCmdStatus), 245 be32_to_cpu(data->devSecStatus)); 246 if (data->rootErrorStatus || data->uncorrErrorStatus || 247 data->corrErrorStatus) 248 pr_info("RootErrSts: %08x %08x %08x\n", 249 be32_to_cpu(data->rootErrorStatus), 250 be32_to_cpu(data->uncorrErrorStatus), 251 be32_to_cpu(data->corrErrorStatus)); 252 if (data->tlpHdr1 || data->tlpHdr2 || 253 data->tlpHdr3 || data->tlpHdr4) 254 pr_info("RootErrLog: %08x %08x %08x %08x\n", 255 be32_to_cpu(data->tlpHdr1), 256 be32_to_cpu(data->tlpHdr2), 257 be32_to_cpu(data->tlpHdr3), 258 be32_to_cpu(data->tlpHdr4)); 259 if (data->sourceId || data->errorClass || 260 data->correlator) 261 pr_info("RootErrLog1: %08x %016llx %016llx\n", 262 be32_to_cpu(data->sourceId), 263 be64_to_cpu(data->errorClass), 264 be64_to_cpu(data->correlator)); 265 if (data->nFir) 266 pr_info("nFir: %016llx %016llx %016llx\n", 267 be64_to_cpu(data->nFir), 268 be64_to_cpu(data->nFirMask), 269 be64_to_cpu(data->nFirWOF)); 270 if (data->phbPlssr || data->phbCsr) 271 pr_info("PhbSts: %016llx %016llx\n", 272 be64_to_cpu(data->phbPlssr), 273 be64_to_cpu(data->phbCsr)); 274 if (data->lemFir) 275 pr_info("Lem: %016llx %016llx %016llx\n", 276 be64_to_cpu(data->lemFir), 277 be64_to_cpu(data->lemErrorMask), 278 be64_to_cpu(data->lemWOF)); 279 if (data->phbErrorStatus) 280 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 281 be64_to_cpu(data->phbErrorStatus), 282 be64_to_cpu(data->phbFirstErrorStatus), 283 be64_to_cpu(data->phbErrorLog0), 284 be64_to_cpu(data->phbErrorLog1)); 285 if (data->mmioErrorStatus) 286 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 287 be64_to_cpu(data->mmioErrorStatus), 288 be64_to_cpu(data->mmioFirstErrorStatus), 289 be64_to_cpu(data->mmioErrorLog0), 290 be64_to_cpu(data->mmioErrorLog1)); 291 if (data->dma0ErrorStatus) 292 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 293 be64_to_cpu(data->dma0ErrorStatus), 294 be64_to_cpu(data->dma0FirstErrorStatus), 295 be64_to_cpu(data->dma0ErrorLog0), 296 be64_to_cpu(data->dma0ErrorLog1)); 297 if (data->dma1ErrorStatus) 298 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 299 be64_to_cpu(data->dma1ErrorStatus), 300 be64_to_cpu(data->dma1FirstErrorStatus), 301 be64_to_cpu(data->dma1ErrorLog0), 302 be64_to_cpu(data->dma1ErrorLog1)); 303 304 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { 305 if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 && 306 (be64_to_cpu(data->pestB[i]) >> 63) == 0) 307 continue; 308 309 pr_info("PE[%3d] A/B: %016llx %016llx\n", 310 i, be64_to_cpu(data->pestA[i]), 311 be64_to_cpu(data->pestB[i])); 312 } 313 } 314 315 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 316 unsigned char *log_buff) 317 { 318 struct OpalIoPhbErrorCommon *common; 319 320 if (!hose || !log_buff) 321 return; 322 323 common = (struct OpalIoPhbErrorCommon *)log_buff; 324 switch (be32_to_cpu(common->ioType)) { 325 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: 326 pnv_pci_dump_p7ioc_diag_data(hose, common); 327 break; 328 case OPAL_PHB_ERROR_DATA_TYPE_PHB3: 329 pnv_pci_dump_phb3_diag_data(hose, common); 330 break; 331 default: 332 pr_warn("%s: Unrecognized ioType %d\n", 333 __func__, be32_to_cpu(common->ioType)); 334 } 335 } 336 337 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) 338 { 339 unsigned long flags, rc; 340 int has_diag, ret = 0; 341 342 spin_lock_irqsave(&phb->lock, flags); 343 344 /* Fetch PHB diag-data */ 345 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, 346 PNV_PCI_DIAG_BUF_SIZE); 347 has_diag = (rc == OPAL_SUCCESS); 348 349 /* If PHB supports compound PE, to handle it */ 350 if (phb->unfreeze_pe) { 351 ret = phb->unfreeze_pe(phb, 352 pe_no, 353 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 354 } else { 355 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 356 pe_no, 357 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 358 if (rc) { 359 pr_warn("%s: Failure %ld clearing frozen " 360 "PHB#%x-PE#%x\n", 361 __func__, rc, phb->hose->global_number, 362 pe_no); 363 ret = -EIO; 364 } 365 } 366 367 /* 368 * For now, let's only display the diag buffer when we fail to clear 369 * the EEH status. We'll do more sensible things later when we have 370 * proper EEH support. We need to make sure we don't pollute ourselves 371 * with the normal errors generated when probing empty slots 372 */ 373 if (has_diag && ret) 374 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); 375 376 spin_unlock_irqrestore(&phb->lock, flags); 377 } 378 379 static void pnv_pci_config_check_eeh(struct pnv_phb *phb, 380 struct device_node *dn) 381 { 382 u8 fstate; 383 __be16 pcierr; 384 int pe_no; 385 s64 rc; 386 387 /* 388 * Get the PE#. During the PCI probe stage, we might not 389 * setup that yet. So all ER errors should be mapped to 390 * reserved PE. 391 */ 392 pe_no = PCI_DN(dn)->pe_number; 393 if (pe_no == IODA_INVALID_PE) { 394 if (phb->type == PNV_PHB_P5IOC2) 395 pe_no = 0; 396 else 397 pe_no = phb->ioda.reserved_pe; 398 } 399 400 /* 401 * Fetch frozen state. If the PHB support compound PE, 402 * we need handle that case. 403 */ 404 if (phb->get_pe_state) { 405 fstate = phb->get_pe_state(phb, pe_no); 406 } else { 407 rc = opal_pci_eeh_freeze_status(phb->opal_id, 408 pe_no, 409 &fstate, 410 &pcierr, 411 NULL); 412 if (rc) { 413 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n", 414 __func__, rc, phb->hose->global_number, pe_no); 415 return; 416 } 417 } 418 419 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", 420 (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn), 421 pe_no, fstate); 422 423 /* Clear the frozen state if applicable */ 424 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE || 425 fstate == OPAL_EEH_STOPPED_DMA_FREEZE || 426 fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) { 427 /* 428 * If PHB supports compound PE, freeze it for 429 * consistency. 430 */ 431 if (phb->freeze_pe) 432 phb->freeze_pe(phb, pe_no); 433 434 pnv_pci_handle_eeh_config(phb, pe_no); 435 } 436 } 437 438 int pnv_pci_cfg_read(struct device_node *dn, 439 int where, int size, u32 *val) 440 { 441 struct pci_dn *pdn = PCI_DN(dn); 442 struct pnv_phb *phb = pdn->phb->private_data; 443 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 444 s64 rc; 445 446 switch (size) { 447 case 1: { 448 u8 v8; 449 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); 450 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; 451 break; 452 } 453 case 2: { 454 __be16 v16; 455 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, 456 &v16); 457 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; 458 break; 459 } 460 case 4: { 461 __be32 v32; 462 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); 463 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; 464 break; 465 } 466 default: 467 return PCIBIOS_FUNC_NOT_SUPPORTED; 468 } 469 470 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 471 __func__, pdn->busno, pdn->devfn, where, size, *val); 472 return PCIBIOS_SUCCESSFUL; 473 } 474 475 int pnv_pci_cfg_write(struct device_node *dn, 476 int where, int size, u32 val) 477 { 478 struct pci_dn *pdn = PCI_DN(dn); 479 struct pnv_phb *phb = pdn->phb->private_data; 480 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 481 482 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 483 pdn->busno, pdn->devfn, where, size, val); 484 switch (size) { 485 case 1: 486 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); 487 break; 488 case 2: 489 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); 490 break; 491 case 4: 492 opal_pci_config_write_word(phb->opal_id, bdfn, where, val); 493 break; 494 default: 495 return PCIBIOS_FUNC_NOT_SUPPORTED; 496 } 497 498 return PCIBIOS_SUCCESSFUL; 499 } 500 501 #if CONFIG_EEH 502 static bool pnv_pci_cfg_check(struct pci_controller *hose, 503 struct device_node *dn) 504 { 505 struct eeh_dev *edev = NULL; 506 struct pnv_phb *phb = hose->private_data; 507 508 /* EEH not enabled ? */ 509 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 510 return true; 511 512 /* PE reset or device removed ? */ 513 edev = of_node_to_eeh_dev(dn); 514 if (edev) { 515 if (edev->pe && 516 (edev->pe->state & EEH_PE_RESET)) 517 return false; 518 519 if (edev->mode & EEH_DEV_REMOVED) 520 return false; 521 } 522 523 return true; 524 } 525 #else 526 static inline pnv_pci_cfg_check(struct pci_controller *hose, 527 struct device_node *dn) 528 { 529 return true; 530 } 531 #endif /* CONFIG_EEH */ 532 533 static int pnv_pci_read_config(struct pci_bus *bus, 534 unsigned int devfn, 535 int where, int size, u32 *val) 536 { 537 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); 538 struct pci_dn *pdn; 539 struct pnv_phb *phb; 540 bool found = false; 541 int ret; 542 543 *val = 0xFFFFFFFF; 544 for (dn = busdn->child; dn; dn = dn->sibling) { 545 pdn = PCI_DN(dn); 546 if (pdn && pdn->devfn == devfn) { 547 phb = pdn->phb->private_data; 548 found = true; 549 break; 550 } 551 } 552 553 if (!found || !pnv_pci_cfg_check(pdn->phb, dn)) 554 return PCIBIOS_DEVICE_NOT_FOUND; 555 556 ret = pnv_pci_cfg_read(dn, where, size, val); 557 if (phb->flags & PNV_PHB_FLAG_EEH) { 558 if (*val == EEH_IO_ERROR_VALUE(size) && 559 eeh_dev_check_failure(of_node_to_eeh_dev(dn))) 560 return PCIBIOS_DEVICE_NOT_FOUND; 561 } else { 562 pnv_pci_config_check_eeh(phb, dn); 563 } 564 565 return ret; 566 } 567 568 static int pnv_pci_write_config(struct pci_bus *bus, 569 unsigned int devfn, 570 int where, int size, u32 val) 571 { 572 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); 573 struct pci_dn *pdn; 574 struct pnv_phb *phb; 575 bool found = false; 576 int ret; 577 578 for (dn = busdn->child; dn; dn = dn->sibling) { 579 pdn = PCI_DN(dn); 580 if (pdn && pdn->devfn == devfn) { 581 phb = pdn->phb->private_data; 582 found = true; 583 break; 584 } 585 } 586 587 if (!found || !pnv_pci_cfg_check(pdn->phb, dn)) 588 return PCIBIOS_DEVICE_NOT_FOUND; 589 590 ret = pnv_pci_cfg_write(dn, where, size, val); 591 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 592 pnv_pci_config_check_eeh(phb, dn); 593 594 return ret; 595 } 596 597 struct pci_ops pnv_pci_ops = { 598 .read = pnv_pci_read_config, 599 .write = pnv_pci_write_config, 600 }; 601 602 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 603 unsigned long uaddr, enum dma_data_direction direction, 604 struct dma_attrs *attrs, bool rm) 605 { 606 u64 proto_tce; 607 __be64 *tcep, *tces; 608 u64 rpn; 609 610 proto_tce = TCE_PCI_READ; // Read allowed 611 612 if (direction != DMA_TO_DEVICE) 613 proto_tce |= TCE_PCI_WRITE; 614 615 tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; 616 rpn = __pa(uaddr) >> tbl->it_page_shift; 617 618 while (npages--) 619 *(tcep++) = cpu_to_be64(proto_tce | 620 (rpn++ << tbl->it_page_shift)); 621 622 /* Some implementations won't cache invalid TCEs and thus may not 623 * need that flush. We'll probably turn it_type into a bit mask 624 * of flags if that becomes the case 625 */ 626 if (tbl->it_type & TCE_PCI_SWINV_CREATE) 627 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); 628 629 return 0; 630 } 631 632 static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages, 633 unsigned long uaddr, 634 enum dma_data_direction direction, 635 struct dma_attrs *attrs) 636 { 637 return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, 638 false); 639 } 640 641 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages, 642 bool rm) 643 { 644 __be64 *tcep, *tces; 645 646 tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; 647 648 while (npages--) 649 *(tcep++) = cpu_to_be64(0); 650 651 if (tbl->it_type & TCE_PCI_SWINV_FREE) 652 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); 653 } 654 655 static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages) 656 { 657 pnv_tce_free(tbl, index, npages, false); 658 } 659 660 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index) 661 { 662 return ((u64 *)tbl->it_base)[index - tbl->it_offset]; 663 } 664 665 static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages, 666 unsigned long uaddr, 667 enum dma_data_direction direction, 668 struct dma_attrs *attrs) 669 { 670 return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true); 671 } 672 673 static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages) 674 { 675 pnv_tce_free(tbl, index, npages, true); 676 } 677 678 void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 679 void *tce_mem, u64 tce_size, 680 u64 dma_offset, unsigned page_shift) 681 { 682 tbl->it_blocksize = 16; 683 tbl->it_base = (unsigned long)tce_mem; 684 tbl->it_page_shift = page_shift; 685 tbl->it_offset = dma_offset >> tbl->it_page_shift; 686 tbl->it_index = 0; 687 tbl->it_size = tce_size >> 3; 688 tbl->it_busno = 0; 689 tbl->it_type = TCE_PCI; 690 } 691 692 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose) 693 { 694 struct iommu_table *tbl; 695 const __be64 *basep, *swinvp; 696 const __be32 *sizep; 697 698 basep = of_get_property(hose->dn, "linux,tce-base", NULL); 699 sizep = of_get_property(hose->dn, "linux,tce-size", NULL); 700 if (basep == NULL || sizep == NULL) { 701 pr_err("PCI: %s has missing tce entries !\n", 702 hose->dn->full_name); 703 return NULL; 704 } 705 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node); 706 if (WARN_ON(!tbl)) 707 return NULL; 708 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)), 709 be32_to_cpup(sizep), 0, IOMMU_PAGE_SHIFT_4K); 710 iommu_init_table(tbl, hose->node); 711 iommu_register_group(tbl, pci_domain_nr(hose->bus), 0); 712 713 /* Deal with SW invalidated TCEs when needed (BML way) */ 714 swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info", 715 NULL); 716 if (swinvp) { 717 tbl->it_busno = be64_to_cpu(swinvp[1]); 718 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); 719 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; 720 } 721 return tbl; 722 } 723 724 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose, 725 struct pci_dev *pdev) 726 { 727 struct device_node *np = pci_bus_to_OF_node(hose->bus); 728 struct pci_dn *pdn; 729 730 if (np == NULL) 731 return; 732 pdn = PCI_DN(np); 733 if (!pdn->iommu_table) 734 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose); 735 if (!pdn->iommu_table) 736 return; 737 set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table); 738 } 739 740 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev) 741 { 742 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 743 struct pnv_phb *phb = hose->private_data; 744 745 /* If we have no phb structure, try to setup a fallback based on 746 * the device-tree (RTAS PCI for example) 747 */ 748 if (phb && phb->dma_dev_setup) 749 phb->dma_dev_setup(phb, pdev); 750 else 751 pnv_pci_dma_fallback_setup(hose, pdev); 752 } 753 754 int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 755 { 756 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 757 struct pnv_phb *phb = hose->private_data; 758 759 if (phb && phb->dma_set_mask) 760 return phb->dma_set_mask(phb, pdev, dma_mask); 761 return __dma_set_mask(&pdev->dev, dma_mask); 762 } 763 764 void pnv_pci_shutdown(void) 765 { 766 struct pci_controller *hose; 767 768 list_for_each_entry(hose, &hose_list, list_node) { 769 struct pnv_phb *phb = hose->private_data; 770 771 if (phb && phb->shutdown) 772 phb->shutdown(phb); 773 } 774 } 775 776 /* Fixup wrong class code in p7ioc and p8 root complex */ 777 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) 778 { 779 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 780 } 781 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); 782 783 static int pnv_pci_probe_mode(struct pci_bus *bus) 784 { 785 struct pci_controller *hose = pci_bus_to_host(bus); 786 const __be64 *tstamp; 787 u64 now, target; 788 789 790 /* We hijack this as a way to ensure we have waited long 791 * enough since the reset was lifted on the PCI bus 792 */ 793 if (bus != hose->bus) 794 return PCI_PROBE_NORMAL; 795 tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL); 796 if (!tstamp || !*tstamp) 797 return PCI_PROBE_NORMAL; 798 799 now = mftb() / tb_ticks_per_usec; 800 target = (be64_to_cpup(tstamp) / tb_ticks_per_usec) 801 + PCI_RESET_DELAY_US; 802 803 pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n", 804 hose->global_number, target, now); 805 806 if (now < target) 807 msleep((target - now + 999) / 1000); 808 809 return PCI_PROBE_NORMAL; 810 } 811 812 void __init pnv_pci_init(void) 813 { 814 struct device_node *np; 815 816 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); 817 818 /* OPAL absent, try POPAL first then RTAS detection of PHBs */ 819 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 820 #ifdef CONFIG_PPC_POWERNV_RTAS 821 init_pci_config_tokens(); 822 find_and_init_phbs(); 823 #endif /* CONFIG_PPC_POWERNV_RTAS */ 824 } 825 /* OPAL is here, do our normal stuff */ 826 else { 827 int found_ioda = 0; 828 829 /* Look for IODA IO-Hubs. We don't support mixing IODA 830 * and p5ioc2 due to the need to change some global 831 * probing flags 832 */ 833 for_each_compatible_node(np, NULL, "ibm,ioda-hub") { 834 pnv_pci_init_ioda_hub(np); 835 found_ioda = 1; 836 } 837 838 /* Look for p5ioc2 IO-Hubs */ 839 if (!found_ioda) 840 for_each_compatible_node(np, NULL, "ibm,p5ioc2") 841 pnv_pci_init_p5ioc2_hub(np); 842 843 /* Look for ioda2 built-in PHB3's */ 844 for_each_compatible_node(np, NULL, "ibm,ioda2-phb") 845 pnv_pci_init_ioda2_phb(np); 846 } 847 848 /* Setup the linkage between OF nodes and PHBs */ 849 pci_devs_phb_init(); 850 851 /* Configure IOMMU DMA hooks */ 852 ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup; 853 ppc_md.tce_build = pnv_tce_build_vm; 854 ppc_md.tce_free = pnv_tce_free_vm; 855 ppc_md.tce_build_rm = pnv_tce_build_rm; 856 ppc_md.tce_free_rm = pnv_tce_free_rm; 857 ppc_md.tce_get = pnv_tce_get; 858 ppc_md.pci_probe_mode = pnv_pci_probe_mode; 859 set_pci_dma_ops(&dma_iommu_ops); 860 861 /* Configure MSIs */ 862 #ifdef CONFIG_PCI_MSI 863 ppc_md.msi_check_device = pnv_msi_check_device; 864 ppc_md.setup_msi_irqs = pnv_setup_msi_irqs; 865 ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs; 866 #endif 867 } 868 869 static int tce_iommu_bus_notifier(struct notifier_block *nb, 870 unsigned long action, void *data) 871 { 872 struct device *dev = data; 873 874 switch (action) { 875 case BUS_NOTIFY_ADD_DEVICE: 876 return iommu_add_device(dev); 877 case BUS_NOTIFY_DEL_DEVICE: 878 if (dev->iommu_group) 879 iommu_del_device(dev); 880 return 0; 881 default: 882 return 0; 883 } 884 } 885 886 static struct notifier_block tce_iommu_bus_nb = { 887 .notifier_call = tce_iommu_bus_notifier, 888 }; 889 890 static int __init tce_iommu_bus_notifier_init(void) 891 { 892 bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb); 893 return 0; 894 } 895 machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init); 896