1 /* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Currently supports only P5IOC2 5 * 6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/delay.h> 17 #include <linux/string.h> 18 #include <linux/init.h> 19 #include <linux/bootmem.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/msi.h> 23 24 #include <asm/sections.h> 25 #include <asm/io.h> 26 #include <asm/prom.h> 27 #include <asm/pci-bridge.h> 28 #include <asm/machdep.h> 29 #include <asm/ppc-pci.h> 30 #include <asm/opal.h> 31 #include <asm/iommu.h> 32 #include <asm/tce.h> 33 #include <asm/abs_addr.h> 34 35 #include "powernv.h" 36 #include "pci.h" 37 38 /* Delay in usec */ 39 #define PCI_RESET_DELAY_US 3000000 40 41 #define cfg_dbg(fmt...) do { } while(0) 42 //#define cfg_dbg(fmt...) printk(fmt) 43 44 #ifdef CONFIG_PCI_MSI 45 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type) 46 { 47 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 48 struct pnv_phb *phb = hose->private_data; 49 50 return (phb && phb->msi_map) ? 0 : -ENODEV; 51 } 52 53 static unsigned int pnv_get_one_msi(struct pnv_phb *phb) 54 { 55 unsigned int id; 56 57 spin_lock(&phb->lock); 58 id = find_next_zero_bit(phb->msi_map, phb->msi_count, phb->msi_next); 59 if (id >= phb->msi_count && phb->msi_next) 60 id = find_next_zero_bit(phb->msi_map, phb->msi_count, 0); 61 if (id >= phb->msi_count) { 62 spin_unlock(&phb->lock); 63 return 0; 64 } 65 __set_bit(id, phb->msi_map); 66 spin_unlock(&phb->lock); 67 return id + phb->msi_base; 68 } 69 70 static void pnv_put_msi(struct pnv_phb *phb, unsigned int hwirq) 71 { 72 unsigned int id; 73 74 if (WARN_ON(hwirq < phb->msi_base || 75 hwirq >= (phb->msi_base + phb->msi_count))) 76 return; 77 id = hwirq - phb->msi_base; 78 spin_lock(&phb->lock); 79 __clear_bit(id, phb->msi_map); 80 spin_unlock(&phb->lock); 81 } 82 83 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 84 { 85 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 86 struct pnv_phb *phb = hose->private_data; 87 struct msi_desc *entry; 88 struct msi_msg msg; 89 unsigned int hwirq, virq; 90 int rc; 91 92 if (WARN_ON(!phb)) 93 return -ENODEV; 94 95 list_for_each_entry(entry, &pdev->msi_list, list) { 96 if (!entry->msi_attrib.is_64 && !phb->msi32_support) { 97 pr_warn("%s: Supports only 64-bit MSIs\n", 98 pci_name(pdev)); 99 return -ENXIO; 100 } 101 hwirq = pnv_get_one_msi(phb); 102 if (!hwirq) { 103 pr_warn("%s: Failed to find a free MSI\n", 104 pci_name(pdev)); 105 return -ENOSPC; 106 } 107 virq = irq_create_mapping(NULL, hwirq); 108 if (virq == NO_IRQ) { 109 pr_warn("%s: Failed to map MSI to linux irq\n", 110 pci_name(pdev)); 111 pnv_put_msi(phb, hwirq); 112 return -ENOMEM; 113 } 114 rc = phb->msi_setup(phb, pdev, hwirq, entry->msi_attrib.is_64, 115 &msg); 116 if (rc) { 117 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); 118 irq_dispose_mapping(virq); 119 pnv_put_msi(phb, hwirq); 120 return rc; 121 } 122 irq_set_msi_desc(virq, entry); 123 write_msi_msg(virq, &msg); 124 } 125 return 0; 126 } 127 128 static void pnv_teardown_msi_irqs(struct pci_dev *pdev) 129 { 130 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 131 struct pnv_phb *phb = hose->private_data; 132 struct msi_desc *entry; 133 134 if (WARN_ON(!phb)) 135 return; 136 137 list_for_each_entry(entry, &pdev->msi_list, list) { 138 if (entry->irq == NO_IRQ) 139 continue; 140 irq_set_msi_desc(entry->irq, NULL); 141 pnv_put_msi(phb, virq_to_hw(entry->irq)); 142 irq_dispose_mapping(entry->irq); 143 } 144 } 145 #endif /* CONFIG_PCI_MSI */ 146 147 static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb) 148 { 149 struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc; 150 int i; 151 152 pr_info("PHB %d diagnostic data:\n", phb->hose->global_number); 153 154 pr_info(" brdgCtl = 0x%08x\n", data->brdgCtl); 155 156 pr_info(" portStatusReg = 0x%08x\n", data->portStatusReg); 157 pr_info(" rootCmplxStatus = 0x%08x\n", data->rootCmplxStatus); 158 pr_info(" busAgentStatus = 0x%08x\n", data->busAgentStatus); 159 160 pr_info(" deviceStatus = 0x%08x\n", data->deviceStatus); 161 pr_info(" slotStatus = 0x%08x\n", data->slotStatus); 162 pr_info(" linkStatus = 0x%08x\n", data->linkStatus); 163 pr_info(" devCmdStatus = 0x%08x\n", data->devCmdStatus); 164 pr_info(" devSecStatus = 0x%08x\n", data->devSecStatus); 165 166 pr_info(" rootErrorStatus = 0x%08x\n", data->rootErrorStatus); 167 pr_info(" uncorrErrorStatus = 0x%08x\n", data->uncorrErrorStatus); 168 pr_info(" corrErrorStatus = 0x%08x\n", data->corrErrorStatus); 169 pr_info(" tlpHdr1 = 0x%08x\n", data->tlpHdr1); 170 pr_info(" tlpHdr2 = 0x%08x\n", data->tlpHdr2); 171 pr_info(" tlpHdr3 = 0x%08x\n", data->tlpHdr3); 172 pr_info(" tlpHdr4 = 0x%08x\n", data->tlpHdr4); 173 pr_info(" sourceId = 0x%08x\n", data->sourceId); 174 175 pr_info(" errorClass = 0x%016llx\n", data->errorClass); 176 pr_info(" correlator = 0x%016llx\n", data->correlator); 177 178 pr_info(" p7iocPlssr = 0x%016llx\n", data->p7iocPlssr); 179 pr_info(" p7iocCsr = 0x%016llx\n", data->p7iocCsr); 180 pr_info(" lemFir = 0x%016llx\n", data->lemFir); 181 pr_info(" lemErrorMask = 0x%016llx\n", data->lemErrorMask); 182 pr_info(" lemWOF = 0x%016llx\n", data->lemWOF); 183 pr_info(" phbErrorStatus = 0x%016llx\n", data->phbErrorStatus); 184 pr_info(" phbFirstErrorStatus = 0x%016llx\n", data->phbFirstErrorStatus); 185 pr_info(" phbErrorLog0 = 0x%016llx\n", data->phbErrorLog0); 186 pr_info(" phbErrorLog1 = 0x%016llx\n", data->phbErrorLog1); 187 pr_info(" mmioErrorStatus = 0x%016llx\n", data->mmioErrorStatus); 188 pr_info(" mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus); 189 pr_info(" mmioErrorLog0 = 0x%016llx\n", data->mmioErrorLog0); 190 pr_info(" mmioErrorLog1 = 0x%016llx\n", data->mmioErrorLog1); 191 pr_info(" dma0ErrorStatus = 0x%016llx\n", data->dma0ErrorStatus); 192 pr_info(" dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus); 193 pr_info(" dma0ErrorLog0 = 0x%016llx\n", data->dma0ErrorLog0); 194 pr_info(" dma0ErrorLog1 = 0x%016llx\n", data->dma0ErrorLog1); 195 pr_info(" dma1ErrorStatus = 0x%016llx\n", data->dma1ErrorStatus); 196 pr_info(" dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus); 197 pr_info(" dma1ErrorLog0 = 0x%016llx\n", data->dma1ErrorLog0); 198 pr_info(" dma1ErrorLog1 = 0x%016llx\n", data->dma1ErrorLog1); 199 200 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { 201 if ((data->pestA[i] >> 63) == 0 && 202 (data->pestB[i] >> 63) == 0) 203 continue; 204 pr_info(" PE[%3d] PESTA = 0x%016llx\n", i, data->pestA[i]); 205 pr_info(" PESTB = 0x%016llx\n", data->pestB[i]); 206 } 207 } 208 209 static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb) 210 { 211 switch(phb->model) { 212 case PNV_PHB_MODEL_P7IOC: 213 pnv_pci_dump_p7ioc_diag_data(phb); 214 break; 215 default: 216 pr_warning("PCI %d: Can't decode this PHB diag data\n", 217 phb->hose->global_number); 218 } 219 } 220 221 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) 222 { 223 unsigned long flags, rc; 224 int has_diag; 225 226 spin_lock_irqsave(&phb->lock, flags); 227 228 rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE); 229 has_diag = (rc == OPAL_SUCCESS); 230 231 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, 232 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 233 if (rc) { 234 pr_warning("PCI %d: Failed to clear EEH freeze state" 235 " for PE#%d, err %ld\n", 236 phb->hose->global_number, pe_no, rc); 237 238 /* For now, let's only display the diag buffer when we fail to clear 239 * the EEH status. We'll do more sensible things later when we have 240 * proper EEH support. We need to make sure we don't pollute ourselves 241 * with the normal errors generated when probing empty slots 242 */ 243 if (has_diag) 244 pnv_pci_dump_phb_diag_data(phb); 245 else 246 pr_warning("PCI %d: No diag data available\n", 247 phb->hose->global_number); 248 } 249 250 spin_unlock_irqrestore(&phb->lock, flags); 251 } 252 253 static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus, 254 u32 bdfn) 255 { 256 s64 rc; 257 u8 fstate; 258 u16 pcierr; 259 u32 pe_no; 260 261 /* Get PE# if we support IODA */ 262 pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0; 263 264 /* Read freeze status */ 265 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr, 266 NULL); 267 if (rc) { 268 pr_warning("PCI %d: Failed to read EEH status for PE#%d," 269 " err %lld\n", phb->hose->global_number, pe_no, rc); 270 return; 271 } 272 cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n", 273 bdfn, pe_no, fstate); 274 if (fstate != 0) 275 pnv_pci_handle_eeh_config(phb, pe_no); 276 } 277 278 static int pnv_pci_read_config(struct pci_bus *bus, 279 unsigned int devfn, 280 int where, int size, u32 *val) 281 { 282 struct pci_controller *hose = pci_bus_to_host(bus); 283 struct pnv_phb *phb = hose->private_data; 284 u32 bdfn = (((uint64_t)bus->number) << 8) | devfn; 285 s64 rc; 286 287 if (hose == NULL) 288 return PCIBIOS_DEVICE_NOT_FOUND; 289 290 switch (size) { 291 case 1: { 292 u8 v8; 293 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); 294 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; 295 break; 296 } 297 case 2: { 298 u16 v16; 299 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, 300 &v16); 301 *val = (rc == OPAL_SUCCESS) ? v16 : 0xffff; 302 break; 303 } 304 case 4: { 305 u32 v32; 306 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); 307 *val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff; 308 break; 309 } 310 default: 311 return PCIBIOS_FUNC_NOT_SUPPORTED; 312 } 313 cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n", 314 bus->number, devfn, where, size, *val); 315 316 /* Check if the PHB got frozen due to an error (no response) */ 317 pnv_pci_config_check_eeh(phb, bus, bdfn); 318 319 return PCIBIOS_SUCCESSFUL; 320 } 321 322 static int pnv_pci_write_config(struct pci_bus *bus, 323 unsigned int devfn, 324 int where, int size, u32 val) 325 { 326 struct pci_controller *hose = pci_bus_to_host(bus); 327 struct pnv_phb *phb = hose->private_data; 328 u32 bdfn = (((uint64_t)bus->number) << 8) | devfn; 329 330 if (hose == NULL) 331 return PCIBIOS_DEVICE_NOT_FOUND; 332 333 cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n", 334 bus->number, devfn, where, size, val); 335 switch (size) { 336 case 1: 337 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); 338 break; 339 case 2: 340 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); 341 break; 342 case 4: 343 opal_pci_config_write_word(phb->opal_id, bdfn, where, val); 344 break; 345 default: 346 return PCIBIOS_FUNC_NOT_SUPPORTED; 347 } 348 /* Check if the PHB got frozen due to an error (no response) */ 349 pnv_pci_config_check_eeh(phb, bus, bdfn); 350 351 return PCIBIOS_SUCCESSFUL; 352 } 353 354 struct pci_ops pnv_pci_ops = { 355 .read = pnv_pci_read_config, 356 .write = pnv_pci_write_config, 357 }; 358 359 360 static void pnv_tce_invalidate(struct iommu_table *tbl, 361 u64 *startp, u64 *endp) 362 { 363 u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index; 364 unsigned long start, end, inc; 365 366 start = __pa(startp); 367 end = __pa(endp); 368 369 370 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ 371 if (tbl->it_busno) { 372 start <<= 12; 373 end <<= 12; 374 inc = 128 << 12; 375 start |= tbl->it_busno; 376 end |= tbl->it_busno; 377 } 378 /* p7ioc-style invalidation, 2 TCEs per write */ 379 else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { 380 start |= (1ull << 63); 381 end |= (1ull << 63); 382 inc = 16; 383 } 384 /* Default (older HW) */ 385 else 386 inc = 128; 387 388 end |= inc - 1; /* round up end to be different than start */ 389 390 mb(); /* Ensure above stores are visible */ 391 while (start <= end) { 392 __raw_writeq(start, invalidate); 393 start += inc; 394 } 395 /* The iommu layer will do another mb() for us on build() and 396 * we don't care on free() 397 */ 398 } 399 400 401 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 402 unsigned long uaddr, enum dma_data_direction direction, 403 struct dma_attrs *attrs) 404 { 405 u64 proto_tce; 406 u64 *tcep, *tces; 407 u64 rpn; 408 409 proto_tce = TCE_PCI_READ; // Read allowed 410 411 if (direction != DMA_TO_DEVICE) 412 proto_tce |= TCE_PCI_WRITE; 413 414 tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset; 415 rpn = __pa(uaddr) >> TCE_SHIFT; 416 417 while (npages--) 418 *(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT); 419 420 /* Some implementations won't cache invalid TCEs and thus may not 421 * need that flush. We'll probably turn it_type into a bit mask 422 * of flags if that becomes the case 423 */ 424 if (tbl->it_type & TCE_PCI_SWINV_CREATE) 425 pnv_tce_invalidate(tbl, tces, tcep - 1); 426 427 return 0; 428 } 429 430 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages) 431 { 432 u64 *tcep, *tces; 433 434 tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset; 435 436 while (npages--) 437 *(tcep++) = 0; 438 439 if (tbl->it_type & TCE_PCI_SWINV_FREE) 440 pnv_tce_invalidate(tbl, tces, tcep - 1); 441 } 442 443 void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 444 void *tce_mem, u64 tce_size, 445 u64 dma_offset) 446 { 447 tbl->it_blocksize = 16; 448 tbl->it_base = (unsigned long)tce_mem; 449 tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT; 450 tbl->it_index = 0; 451 tbl->it_size = tce_size >> 3; 452 tbl->it_busno = 0; 453 tbl->it_type = TCE_PCI; 454 } 455 456 static struct iommu_table * __devinit 457 pnv_pci_setup_bml_iommu(struct pci_controller *hose) 458 { 459 struct iommu_table *tbl; 460 const __be64 *basep, *swinvp; 461 const __be32 *sizep; 462 463 basep = of_get_property(hose->dn, "linux,tce-base", NULL); 464 sizep = of_get_property(hose->dn, "linux,tce-size", NULL); 465 if (basep == NULL || sizep == NULL) { 466 pr_err("PCI: %s has missing tce entries !\n", 467 hose->dn->full_name); 468 return NULL; 469 } 470 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node); 471 if (WARN_ON(!tbl)) 472 return NULL; 473 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)), 474 be32_to_cpup(sizep), 0); 475 iommu_init_table(tbl, hose->node); 476 477 /* Deal with SW invalidated TCEs when needed (BML way) */ 478 swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info", 479 NULL); 480 if (swinvp) { 481 tbl->it_busno = swinvp[1]; 482 tbl->it_index = (unsigned long)ioremap(swinvp[0], 8); 483 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; 484 } 485 return tbl; 486 } 487 488 static void __devinit pnv_pci_dma_fallback_setup(struct pci_controller *hose, 489 struct pci_dev *pdev) 490 { 491 struct device_node *np = pci_bus_to_OF_node(hose->bus); 492 struct pci_dn *pdn; 493 494 if (np == NULL) 495 return; 496 pdn = PCI_DN(np); 497 if (!pdn->iommu_table) 498 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose); 499 if (!pdn->iommu_table) 500 return; 501 set_iommu_table_base(&pdev->dev, pdn->iommu_table); 502 } 503 504 static void __devinit pnv_pci_dma_dev_setup(struct pci_dev *pdev) 505 { 506 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 507 struct pnv_phb *phb = hose->private_data; 508 509 /* If we have no phb structure, try to setup a fallback based on 510 * the device-tree (RTAS PCI for example) 511 */ 512 if (phb && phb->dma_dev_setup) 513 phb->dma_dev_setup(phb, pdev); 514 else 515 pnv_pci_dma_fallback_setup(hose, pdev); 516 } 517 518 /* Fixup wrong class code in p7ioc root complex */ 519 static void __devinit pnv_p7ioc_rc_quirk(struct pci_dev *dev) 520 { 521 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 522 } 523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); 524 525 static int pnv_pci_probe_mode(struct pci_bus *bus) 526 { 527 struct pci_controller *hose = pci_bus_to_host(bus); 528 const __be64 *tstamp; 529 u64 now, target; 530 531 532 /* We hijack this as a way to ensure we have waited long 533 * enough since the reset was lifted on the PCI bus 534 */ 535 if (bus != hose->bus) 536 return PCI_PROBE_NORMAL; 537 tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL); 538 if (!tstamp || !*tstamp) 539 return PCI_PROBE_NORMAL; 540 541 now = mftb() / tb_ticks_per_usec; 542 target = (be64_to_cpup(tstamp) / tb_ticks_per_usec) 543 + PCI_RESET_DELAY_US; 544 545 pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n", 546 hose->global_number, target, now); 547 548 if (now < target) 549 msleep((target - now + 999) / 1000); 550 551 return PCI_PROBE_NORMAL; 552 } 553 554 void __init pnv_pci_init(void) 555 { 556 struct device_node *np; 557 558 pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN); 559 560 /* OPAL absent, try POPAL first then RTAS detection of PHBs */ 561 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 562 #ifdef CONFIG_PPC_POWERNV_RTAS 563 init_pci_config_tokens(); 564 find_and_init_phbs(); 565 #endif /* CONFIG_PPC_POWERNV_RTAS */ 566 } 567 /* OPAL is here, do our normal stuff */ 568 else { 569 int found_ioda = 0; 570 571 /* Look for IODA IO-Hubs. We don't support mixing IODA 572 * and p5ioc2 due to the need to change some global 573 * probing flags 574 */ 575 for_each_compatible_node(np, NULL, "ibm,ioda-hub") { 576 pnv_pci_init_ioda_hub(np); 577 found_ioda = 1; 578 } 579 580 /* Look for p5ioc2 IO-Hubs */ 581 if (!found_ioda) 582 for_each_compatible_node(np, NULL, "ibm,p5ioc2") 583 pnv_pci_init_p5ioc2_hub(np); 584 } 585 586 /* Setup the linkage between OF nodes and PHBs */ 587 pci_devs_phb_init(); 588 589 /* Configure IOMMU DMA hooks */ 590 ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup; 591 ppc_md.tce_build = pnv_tce_build; 592 ppc_md.tce_free = pnv_tce_free; 593 ppc_md.pci_probe_mode = pnv_pci_probe_mode; 594 set_pci_dma_ops(&dma_iommu_ops); 595 596 /* Configure MSIs */ 597 #ifdef CONFIG_PCI_MSI 598 ppc_md.msi_check_device = pnv_msi_check_device; 599 ppc_md.setup_msi_irqs = pnv_setup_msi_irqs; 600 ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs; 601 #endif 602 } 603