1 /*
2  * Support PCI/PCIe on PowerNV platforms
3  *
4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11 
12 #include <linux/kernel.h>
13 #include <linux/pci.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/io.h>
19 #include <linux/msi.h>
20 #include <linux/iommu.h>
21 
22 #include <asm/sections.h>
23 #include <asm/io.h>
24 #include <asm/prom.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <asm/msi_bitmap.h>
28 #include <asm/ppc-pci.h>
29 #include <asm/pnv-pci.h>
30 #include <asm/opal.h>
31 #include <asm/iommu.h>
32 #include <asm/tce.h>
33 #include <asm/firmware.h>
34 #include <asm/eeh_event.h>
35 #include <asm/eeh.h>
36 
37 #include "powernv.h"
38 #include "pci.h"
39 
40 int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id)
41 {
42 	struct device_node *parent = np;
43 	u32 bdfn;
44 	u64 phbid;
45 	int ret;
46 
47 	ret = of_property_read_u32(np, "reg", &bdfn);
48 	if (ret)
49 		return -ENXIO;
50 
51 	bdfn = ((bdfn & 0x00ffff00) >> 8);
52 	while ((parent = of_get_parent(parent))) {
53 		if (!PCI_DN(parent)) {
54 			of_node_put(parent);
55 			break;
56 		}
57 
58 		if (!of_device_is_compatible(parent, "ibm,ioda2-phb")) {
59 			of_node_put(parent);
60 			continue;
61 		}
62 
63 		ret = of_property_read_u64(parent, "ibm,opal-phbid", &phbid);
64 		if (ret) {
65 			of_node_put(parent);
66 			return -ENXIO;
67 		}
68 
69 		*id = PCI_SLOT_ID(phbid, bdfn);
70 		return 0;
71 	}
72 
73 	return -ENODEV;
74 }
75 EXPORT_SYMBOL_GPL(pnv_pci_get_slot_id);
76 
77 int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len)
78 {
79 	int64_t rc;
80 
81 	if (!opal_check_token(OPAL_GET_DEVICE_TREE))
82 		return -ENXIO;
83 
84 	rc = opal_get_device_tree(phandle, (uint64_t)buf, len);
85 	if (rc < OPAL_SUCCESS)
86 		return -EIO;
87 
88 	return rc;
89 }
90 EXPORT_SYMBOL_GPL(pnv_pci_get_device_tree);
91 
92 int pnv_pci_get_presence_state(uint64_t id, uint8_t *state)
93 {
94 	int64_t rc;
95 
96 	if (!opal_check_token(OPAL_PCI_GET_PRESENCE_STATE))
97 		return -ENXIO;
98 
99 	rc = opal_pci_get_presence_state(id, (uint64_t)state);
100 	if (rc != OPAL_SUCCESS)
101 		return -EIO;
102 
103 	return 0;
104 }
105 EXPORT_SYMBOL_GPL(pnv_pci_get_presence_state);
106 
107 int pnv_pci_get_power_state(uint64_t id, uint8_t *state)
108 {
109 	int64_t rc;
110 
111 	if (!opal_check_token(OPAL_PCI_GET_POWER_STATE))
112 		return -ENXIO;
113 
114 	rc = opal_pci_get_power_state(id, (uint64_t)state);
115 	if (rc != OPAL_SUCCESS)
116 		return -EIO;
117 
118 	return 0;
119 }
120 EXPORT_SYMBOL_GPL(pnv_pci_get_power_state);
121 
122 int pnv_pci_set_power_state(uint64_t id, uint8_t state, struct opal_msg *msg)
123 {
124 	struct opal_msg m;
125 	int token, ret;
126 	int64_t rc;
127 
128 	if (!opal_check_token(OPAL_PCI_SET_POWER_STATE))
129 		return -ENXIO;
130 
131 	token = opal_async_get_token_interruptible();
132 	if (unlikely(token < 0))
133 		return token;
134 
135 	rc = opal_pci_set_power_state(token, id, (uint64_t)&state);
136 	if (rc == OPAL_SUCCESS) {
137 		ret = 0;
138 		goto exit;
139 	} else if (rc != OPAL_ASYNC_COMPLETION) {
140 		ret = -EIO;
141 		goto exit;
142 	}
143 
144 	ret = opal_async_wait_response(token, &m);
145 	if (ret < 0)
146 		goto exit;
147 
148 	if (msg) {
149 		ret = 1;
150 		memcpy(msg, &m, sizeof(m));
151 	}
152 
153 exit:
154 	opal_async_release_token(token);
155 	return ret;
156 }
157 EXPORT_SYMBOL_GPL(pnv_pci_set_power_state);
158 
159 #ifdef CONFIG_PCI_MSI
160 int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
161 {
162 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
163 	struct pnv_phb *phb = hose->private_data;
164 	struct msi_desc *entry;
165 	struct msi_msg msg;
166 	int hwirq;
167 	unsigned int virq;
168 	int rc;
169 
170 	if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
171 		return -ENODEV;
172 
173 	if (pdev->no_64bit_msi && !phb->msi32_support)
174 		return -ENODEV;
175 
176 	for_each_pci_msi_entry(entry, pdev) {
177 		if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
178 			pr_warn("%s: Supports only 64-bit MSIs\n",
179 				pci_name(pdev));
180 			return -ENXIO;
181 		}
182 		hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
183 		if (hwirq < 0) {
184 			pr_warn("%s: Failed to find a free MSI\n",
185 				pci_name(pdev));
186 			return -ENOSPC;
187 		}
188 		virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
189 		if (!virq) {
190 			pr_warn("%s: Failed to map MSI to linux irq\n",
191 				pci_name(pdev));
192 			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
193 			return -ENOMEM;
194 		}
195 		rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
196 				    virq, entry->msi_attrib.is_64, &msg);
197 		if (rc) {
198 			pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
199 			irq_dispose_mapping(virq);
200 			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
201 			return rc;
202 		}
203 		irq_set_msi_desc(virq, entry);
204 		pci_write_msi_msg(virq, &msg);
205 	}
206 	return 0;
207 }
208 
209 void pnv_teardown_msi_irqs(struct pci_dev *pdev)
210 {
211 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
212 	struct pnv_phb *phb = hose->private_data;
213 	struct msi_desc *entry;
214 	irq_hw_number_t hwirq;
215 
216 	if (WARN_ON(!phb))
217 		return;
218 
219 	for_each_pci_msi_entry(entry, pdev) {
220 		if (!entry->irq)
221 			continue;
222 		hwirq = virq_to_hw(entry->irq);
223 		irq_set_msi_desc(entry->irq, NULL);
224 		irq_dispose_mapping(entry->irq);
225 		msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1);
226 	}
227 }
228 #endif /* CONFIG_PCI_MSI */
229 
230 /* Nicely print the contents of the PE State Tables (PEST). */
231 static void pnv_pci_dump_pest(__be64 pestA[], __be64 pestB[], int pest_size)
232 {
233 	__be64 prevA = ULONG_MAX, prevB = ULONG_MAX;
234 	bool dup = false;
235 	int i;
236 
237 	for (i = 0; i < pest_size; i++) {
238 		__be64 peA = be64_to_cpu(pestA[i]);
239 		__be64 peB = be64_to_cpu(pestB[i]);
240 
241 		if (peA != prevA || peB != prevB) {
242 			if (dup) {
243 				pr_info("PE[..%03x] A/B: as above\n", i-1);
244 				dup = false;
245 			}
246 			prevA = peA;
247 			prevB = peB;
248 			if (peA & PNV_IODA_STOPPED_STATE ||
249 			    peB & PNV_IODA_STOPPED_STATE)
250 				pr_info("PE[%03x] A/B: %016llx %016llx\n",
251 					i, peA, peB);
252 		} else if (!dup && (peA & PNV_IODA_STOPPED_STATE ||
253 				    peB & PNV_IODA_STOPPED_STATE)) {
254 			dup = true;
255 		}
256 	}
257 }
258 
259 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
260 					 struct OpalIoPhbErrorCommon *common)
261 {
262 	struct OpalIoP7IOCPhbErrorData *data;
263 
264 	data = (struct OpalIoP7IOCPhbErrorData *)common;
265 	pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n",
266 		hose->global_number, be32_to_cpu(common->version));
267 
268 	if (data->brdgCtl)
269 		pr_info("brdgCtl:     %08x\n",
270 			be32_to_cpu(data->brdgCtl));
271 	if (data->portStatusReg || data->rootCmplxStatus ||
272 	    data->busAgentStatus)
273 		pr_info("UtlSts:      %08x %08x %08x\n",
274 			be32_to_cpu(data->portStatusReg),
275 			be32_to_cpu(data->rootCmplxStatus),
276 			be32_to_cpu(data->busAgentStatus));
277 	if (data->deviceStatus || data->slotStatus   ||
278 	    data->linkStatus   || data->devCmdStatus ||
279 	    data->devSecStatus)
280 		pr_info("RootSts:     %08x %08x %08x %08x %08x\n",
281 			be32_to_cpu(data->deviceStatus),
282 			be32_to_cpu(data->slotStatus),
283 			be32_to_cpu(data->linkStatus),
284 			be32_to_cpu(data->devCmdStatus),
285 			be32_to_cpu(data->devSecStatus));
286 	if (data->rootErrorStatus   || data->uncorrErrorStatus ||
287 	    data->corrErrorStatus)
288 		pr_info("RootErrSts:  %08x %08x %08x\n",
289 			be32_to_cpu(data->rootErrorStatus),
290 			be32_to_cpu(data->uncorrErrorStatus),
291 			be32_to_cpu(data->corrErrorStatus));
292 	if (data->tlpHdr1 || data->tlpHdr2 ||
293 	    data->tlpHdr3 || data->tlpHdr4)
294 		pr_info("RootErrLog:  %08x %08x %08x %08x\n",
295 			be32_to_cpu(data->tlpHdr1),
296 			be32_to_cpu(data->tlpHdr2),
297 			be32_to_cpu(data->tlpHdr3),
298 			be32_to_cpu(data->tlpHdr4));
299 	if (data->sourceId || data->errorClass ||
300 	    data->correlator)
301 		pr_info("RootErrLog1: %08x %016llx %016llx\n",
302 			be32_to_cpu(data->sourceId),
303 			be64_to_cpu(data->errorClass),
304 			be64_to_cpu(data->correlator));
305 	if (data->p7iocPlssr || data->p7iocCsr)
306 		pr_info("PhbSts:      %016llx %016llx\n",
307 			be64_to_cpu(data->p7iocPlssr),
308 			be64_to_cpu(data->p7iocCsr));
309 	if (data->lemFir)
310 		pr_info("Lem:         %016llx %016llx %016llx\n",
311 			be64_to_cpu(data->lemFir),
312 			be64_to_cpu(data->lemErrorMask),
313 			be64_to_cpu(data->lemWOF));
314 	if (data->phbErrorStatus)
315 		pr_info("PhbErr:      %016llx %016llx %016llx %016llx\n",
316 			be64_to_cpu(data->phbErrorStatus),
317 			be64_to_cpu(data->phbFirstErrorStatus),
318 			be64_to_cpu(data->phbErrorLog0),
319 			be64_to_cpu(data->phbErrorLog1));
320 	if (data->mmioErrorStatus)
321 		pr_info("OutErr:      %016llx %016llx %016llx %016llx\n",
322 			be64_to_cpu(data->mmioErrorStatus),
323 			be64_to_cpu(data->mmioFirstErrorStatus),
324 			be64_to_cpu(data->mmioErrorLog0),
325 			be64_to_cpu(data->mmioErrorLog1));
326 	if (data->dma0ErrorStatus)
327 		pr_info("InAErr:      %016llx %016llx %016llx %016llx\n",
328 			be64_to_cpu(data->dma0ErrorStatus),
329 			be64_to_cpu(data->dma0FirstErrorStatus),
330 			be64_to_cpu(data->dma0ErrorLog0),
331 			be64_to_cpu(data->dma0ErrorLog1));
332 	if (data->dma1ErrorStatus)
333 		pr_info("InBErr:      %016llx %016llx %016llx %016llx\n",
334 			be64_to_cpu(data->dma1ErrorStatus),
335 			be64_to_cpu(data->dma1FirstErrorStatus),
336 			be64_to_cpu(data->dma1ErrorLog0),
337 			be64_to_cpu(data->dma1ErrorLog1));
338 
339 	pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_P7IOC_NUM_PEST_REGS);
340 }
341 
342 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
343 					struct OpalIoPhbErrorCommon *common)
344 {
345 	struct OpalIoPhb3ErrorData *data;
346 
347 	data = (struct OpalIoPhb3ErrorData*)common;
348 	pr_info("PHB3 PHB#%x Diag-data (Version: %d)\n",
349 		hose->global_number, be32_to_cpu(common->version));
350 	if (data->brdgCtl)
351 		pr_info("brdgCtl:     %08x\n",
352 			be32_to_cpu(data->brdgCtl));
353 	if (data->portStatusReg || data->rootCmplxStatus ||
354 	    data->busAgentStatus)
355 		pr_info("UtlSts:      %08x %08x %08x\n",
356 			be32_to_cpu(data->portStatusReg),
357 			be32_to_cpu(data->rootCmplxStatus),
358 			be32_to_cpu(data->busAgentStatus));
359 	if (data->deviceStatus || data->slotStatus   ||
360 	    data->linkStatus   || data->devCmdStatus ||
361 	    data->devSecStatus)
362 		pr_info("RootSts:     %08x %08x %08x %08x %08x\n",
363 			be32_to_cpu(data->deviceStatus),
364 			be32_to_cpu(data->slotStatus),
365 			be32_to_cpu(data->linkStatus),
366 			be32_to_cpu(data->devCmdStatus),
367 			be32_to_cpu(data->devSecStatus));
368 	if (data->rootErrorStatus || data->uncorrErrorStatus ||
369 	    data->corrErrorStatus)
370 		pr_info("RootErrSts:  %08x %08x %08x\n",
371 			be32_to_cpu(data->rootErrorStatus),
372 			be32_to_cpu(data->uncorrErrorStatus),
373 			be32_to_cpu(data->corrErrorStatus));
374 	if (data->tlpHdr1 || data->tlpHdr2 ||
375 	    data->tlpHdr3 || data->tlpHdr4)
376 		pr_info("RootErrLog:  %08x %08x %08x %08x\n",
377 			be32_to_cpu(data->tlpHdr1),
378 			be32_to_cpu(data->tlpHdr2),
379 			be32_to_cpu(data->tlpHdr3),
380 			be32_to_cpu(data->tlpHdr4));
381 	if (data->sourceId || data->errorClass ||
382 	    data->correlator)
383 		pr_info("RootErrLog1: %08x %016llx %016llx\n",
384 			be32_to_cpu(data->sourceId),
385 			be64_to_cpu(data->errorClass),
386 			be64_to_cpu(data->correlator));
387 	if (data->nFir)
388 		pr_info("nFir:        %016llx %016llx %016llx\n",
389 			be64_to_cpu(data->nFir),
390 			be64_to_cpu(data->nFirMask),
391 			be64_to_cpu(data->nFirWOF));
392 	if (data->phbPlssr || data->phbCsr)
393 		pr_info("PhbSts:      %016llx %016llx\n",
394 			be64_to_cpu(data->phbPlssr),
395 			be64_to_cpu(data->phbCsr));
396 	if (data->lemFir)
397 		pr_info("Lem:         %016llx %016llx %016llx\n",
398 			be64_to_cpu(data->lemFir),
399 			be64_to_cpu(data->lemErrorMask),
400 			be64_to_cpu(data->lemWOF));
401 	if (data->phbErrorStatus)
402 		pr_info("PhbErr:      %016llx %016llx %016llx %016llx\n",
403 			be64_to_cpu(data->phbErrorStatus),
404 			be64_to_cpu(data->phbFirstErrorStatus),
405 			be64_to_cpu(data->phbErrorLog0),
406 			be64_to_cpu(data->phbErrorLog1));
407 	if (data->mmioErrorStatus)
408 		pr_info("OutErr:      %016llx %016llx %016llx %016llx\n",
409 			be64_to_cpu(data->mmioErrorStatus),
410 			be64_to_cpu(data->mmioFirstErrorStatus),
411 			be64_to_cpu(data->mmioErrorLog0),
412 			be64_to_cpu(data->mmioErrorLog1));
413 	if (data->dma0ErrorStatus)
414 		pr_info("InAErr:      %016llx %016llx %016llx %016llx\n",
415 			be64_to_cpu(data->dma0ErrorStatus),
416 			be64_to_cpu(data->dma0FirstErrorStatus),
417 			be64_to_cpu(data->dma0ErrorLog0),
418 			be64_to_cpu(data->dma0ErrorLog1));
419 	if (data->dma1ErrorStatus)
420 		pr_info("InBErr:      %016llx %016llx %016llx %016llx\n",
421 			be64_to_cpu(data->dma1ErrorStatus),
422 			be64_to_cpu(data->dma1FirstErrorStatus),
423 			be64_to_cpu(data->dma1ErrorLog0),
424 			be64_to_cpu(data->dma1ErrorLog1));
425 
426 	pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_PHB3_NUM_PEST_REGS);
427 }
428 
429 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
430 				unsigned char *log_buff)
431 {
432 	struct OpalIoPhbErrorCommon *common;
433 
434 	if (!hose || !log_buff)
435 		return;
436 
437 	common = (struct OpalIoPhbErrorCommon *)log_buff;
438 	switch (be32_to_cpu(common->ioType)) {
439 	case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
440 		pnv_pci_dump_p7ioc_diag_data(hose, common);
441 		break;
442 	case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
443 		pnv_pci_dump_phb3_diag_data(hose, common);
444 		break;
445 	default:
446 		pr_warn("%s: Unrecognized ioType %d\n",
447 			__func__, be32_to_cpu(common->ioType));
448 	}
449 }
450 
451 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
452 {
453 	unsigned long flags, rc;
454 	int has_diag, ret = 0;
455 
456 	spin_lock_irqsave(&phb->lock, flags);
457 
458 	/* Fetch PHB diag-data */
459 	rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
460 					 PNV_PCI_DIAG_BUF_SIZE);
461 	has_diag = (rc == OPAL_SUCCESS);
462 
463 	/* If PHB supports compound PE, to handle it */
464 	if (phb->unfreeze_pe) {
465 		ret = phb->unfreeze_pe(phb,
466 				       pe_no,
467 				       OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
468 	} else {
469 		rc = opal_pci_eeh_freeze_clear(phb->opal_id,
470 					     pe_no,
471 					     OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
472 		if (rc) {
473 			pr_warn("%s: Failure %ld clearing frozen "
474 				"PHB#%x-PE#%x\n",
475 				__func__, rc, phb->hose->global_number,
476 				pe_no);
477 			ret = -EIO;
478 		}
479 	}
480 
481 	/*
482 	 * For now, let's only display the diag buffer when we fail to clear
483 	 * the EEH status. We'll do more sensible things later when we have
484 	 * proper EEH support. We need to make sure we don't pollute ourselves
485 	 * with the normal errors generated when probing empty slots
486 	 */
487 	if (has_diag && ret)
488 		pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
489 
490 	spin_unlock_irqrestore(&phb->lock, flags);
491 }
492 
493 static void pnv_pci_config_check_eeh(struct pci_dn *pdn)
494 {
495 	struct pnv_phb *phb = pdn->phb->private_data;
496 	u8	fstate;
497 	__be16	pcierr;
498 	unsigned int pe_no;
499 	s64	rc;
500 
501 	/*
502 	 * Get the PE#. During the PCI probe stage, we might not
503 	 * setup that yet. So all ER errors should be mapped to
504 	 * reserved PE.
505 	 */
506 	pe_no = pdn->pe_number;
507 	if (pe_no == IODA_INVALID_PE) {
508 		pe_no = phb->ioda.reserved_pe_idx;
509 	}
510 
511 	/*
512 	 * Fetch frozen state. If the PHB support compound PE,
513 	 * we need handle that case.
514 	 */
515 	if (phb->get_pe_state) {
516 		fstate = phb->get_pe_state(phb, pe_no);
517 	} else {
518 		rc = opal_pci_eeh_freeze_status(phb->opal_id,
519 						pe_no,
520 						&fstate,
521 						&pcierr,
522 						NULL);
523 		if (rc) {
524 			pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n",
525 				__func__, rc, phb->hose->global_number, pe_no);
526 			return;
527 		}
528 	}
529 
530 	pr_devel(" -> EEH check, bdfn=%04x PE#%x fstate=%x\n",
531 		 (pdn->busno << 8) | (pdn->devfn), pe_no, fstate);
532 
533 	/* Clear the frozen state if applicable */
534 	if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE ||
535 	    fstate == OPAL_EEH_STOPPED_DMA_FREEZE  ||
536 	    fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) {
537 		/*
538 		 * If PHB supports compound PE, freeze it for
539 		 * consistency.
540 		 */
541 		if (phb->freeze_pe)
542 			phb->freeze_pe(phb, pe_no);
543 
544 		pnv_pci_handle_eeh_config(phb, pe_no);
545 	}
546 }
547 
548 int pnv_pci_cfg_read(struct pci_dn *pdn,
549 		     int where, int size, u32 *val)
550 {
551 	struct pnv_phb *phb = pdn->phb->private_data;
552 	u32 bdfn = (pdn->busno << 8) | pdn->devfn;
553 	s64 rc;
554 
555 	switch (size) {
556 	case 1: {
557 		u8 v8;
558 		rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
559 		*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
560 		break;
561 	}
562 	case 2: {
563 		__be16 v16;
564 		rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
565 						   &v16);
566 		*val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
567 		break;
568 	}
569 	case 4: {
570 		__be32 v32;
571 		rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
572 		*val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
573 		break;
574 	}
575 	default:
576 		return PCIBIOS_FUNC_NOT_SUPPORTED;
577 	}
578 
579 	pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
580 		 __func__, pdn->busno, pdn->devfn, where, size, *val);
581 	return PCIBIOS_SUCCESSFUL;
582 }
583 
584 int pnv_pci_cfg_write(struct pci_dn *pdn,
585 		      int where, int size, u32 val)
586 {
587 	struct pnv_phb *phb = pdn->phb->private_data;
588 	u32 bdfn = (pdn->busno << 8) | pdn->devfn;
589 
590 	pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
591 		 __func__, pdn->busno, pdn->devfn, where, size, val);
592 	switch (size) {
593 	case 1:
594 		opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
595 		break;
596 	case 2:
597 		opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
598 		break;
599 	case 4:
600 		opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
601 		break;
602 	default:
603 		return PCIBIOS_FUNC_NOT_SUPPORTED;
604 	}
605 
606 	return PCIBIOS_SUCCESSFUL;
607 }
608 
609 #if CONFIG_EEH
610 static bool pnv_pci_cfg_check(struct pci_dn *pdn)
611 {
612 	struct eeh_dev *edev = NULL;
613 	struct pnv_phb *phb = pdn->phb->private_data;
614 
615 	/* EEH not enabled ? */
616 	if (!(phb->flags & PNV_PHB_FLAG_EEH))
617 		return true;
618 
619 	/* PE reset or device removed ? */
620 	edev = pdn->edev;
621 	if (edev) {
622 		if (edev->pe &&
623 		    (edev->pe->state & EEH_PE_CFG_BLOCKED))
624 			return false;
625 
626 		if (edev->mode & EEH_DEV_REMOVED)
627 			return false;
628 	}
629 
630 	return true;
631 }
632 #else
633 static inline pnv_pci_cfg_check(struct pci_dn *pdn)
634 {
635 	return true;
636 }
637 #endif /* CONFIG_EEH */
638 
639 static int pnv_pci_read_config(struct pci_bus *bus,
640 			       unsigned int devfn,
641 			       int where, int size, u32 *val)
642 {
643 	struct pci_dn *pdn;
644 	struct pnv_phb *phb;
645 	int ret;
646 
647 	*val = 0xFFFFFFFF;
648 	pdn = pci_get_pdn_by_devfn(bus, devfn);
649 	if (!pdn)
650 		return PCIBIOS_DEVICE_NOT_FOUND;
651 
652 	if (!pnv_pci_cfg_check(pdn))
653 		return PCIBIOS_DEVICE_NOT_FOUND;
654 
655 	ret = pnv_pci_cfg_read(pdn, where, size, val);
656 	phb = pdn->phb->private_data;
657 	if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) {
658 		if (*val == EEH_IO_ERROR_VALUE(size) &&
659 		    eeh_dev_check_failure(pdn->edev))
660                         return PCIBIOS_DEVICE_NOT_FOUND;
661 	} else {
662 		pnv_pci_config_check_eeh(pdn);
663 	}
664 
665 	return ret;
666 }
667 
668 static int pnv_pci_write_config(struct pci_bus *bus,
669 				unsigned int devfn,
670 				int where, int size, u32 val)
671 {
672 	struct pci_dn *pdn;
673 	struct pnv_phb *phb;
674 	int ret;
675 
676 	pdn = pci_get_pdn_by_devfn(bus, devfn);
677 	if (!pdn)
678 		return PCIBIOS_DEVICE_NOT_FOUND;
679 
680 	if (!pnv_pci_cfg_check(pdn))
681 		return PCIBIOS_DEVICE_NOT_FOUND;
682 
683 	ret = pnv_pci_cfg_write(pdn, where, size, val);
684 	phb = pdn->phb->private_data;
685 	if (!(phb->flags & PNV_PHB_FLAG_EEH))
686 		pnv_pci_config_check_eeh(pdn);
687 
688 	return ret;
689 }
690 
691 struct pci_ops pnv_pci_ops = {
692 	.read  = pnv_pci_read_config,
693 	.write = pnv_pci_write_config,
694 };
695 
696 static __be64 *pnv_tce(struct iommu_table *tbl, long idx)
697 {
698 	__be64 *tmp = ((__be64 *)tbl->it_base);
699 	int  level = tbl->it_indirect_levels;
700 	const long shift = ilog2(tbl->it_level_size);
701 	unsigned long mask = (tbl->it_level_size - 1) << (level * shift);
702 
703 	while (level) {
704 		int n = (idx & mask) >> (level * shift);
705 		unsigned long tce = be64_to_cpu(tmp[n]);
706 
707 		tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE));
708 		idx &= ~mask;
709 		mask >>= shift;
710 		--level;
711 	}
712 
713 	return tmp + idx;
714 }
715 
716 int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
717 		unsigned long uaddr, enum dma_data_direction direction,
718 		unsigned long attrs)
719 {
720 	u64 proto_tce = iommu_direction_to_tce_perm(direction);
721 	u64 rpn = __pa(uaddr) >> tbl->it_page_shift;
722 	long i;
723 
724 	if (proto_tce & TCE_PCI_WRITE)
725 		proto_tce |= TCE_PCI_READ;
726 
727 	for (i = 0; i < npages; i++) {
728 		unsigned long newtce = proto_tce |
729 			((rpn + i) << tbl->it_page_shift);
730 		unsigned long idx = index - tbl->it_offset + i;
731 
732 		*(pnv_tce(tbl, idx)) = cpu_to_be64(newtce);
733 	}
734 
735 	return 0;
736 }
737 
738 #ifdef CONFIG_IOMMU_API
739 int pnv_tce_xchg(struct iommu_table *tbl, long index,
740 		unsigned long *hpa, enum dma_data_direction *direction)
741 {
742 	u64 proto_tce = iommu_direction_to_tce_perm(*direction);
743 	unsigned long newtce = *hpa | proto_tce, oldtce;
744 	unsigned long idx = index - tbl->it_offset;
745 
746 	BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl));
747 
748 	if (newtce & TCE_PCI_WRITE)
749 		newtce |= TCE_PCI_READ;
750 
751 	oldtce = be64_to_cpu(xchg(pnv_tce(tbl, idx), cpu_to_be64(newtce)));
752 	*hpa = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE);
753 	*direction = iommu_tce_direction(oldtce);
754 
755 	return 0;
756 }
757 #endif
758 
759 void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
760 {
761 	long i;
762 
763 	for (i = 0; i < npages; i++) {
764 		unsigned long idx = index - tbl->it_offset + i;
765 
766 		*(pnv_tce(tbl, idx)) = cpu_to_be64(0);
767 	}
768 }
769 
770 unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
771 {
772 	return be64_to_cpu(*(pnv_tce(tbl, index - tbl->it_offset)));
773 }
774 
775 struct iommu_table *pnv_pci_table_alloc(int nid)
776 {
777 	struct iommu_table *tbl;
778 
779 	tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, nid);
780 	if (!tbl)
781 		return NULL;
782 
783 	INIT_LIST_HEAD_RCU(&tbl->it_group_list);
784 	kref_init(&tbl->it_kref);
785 
786 	return tbl;
787 }
788 
789 long pnv_pci_link_table_and_group(int node, int num,
790 		struct iommu_table *tbl,
791 		struct iommu_table_group *table_group)
792 {
793 	struct iommu_table_group_link *tgl = NULL;
794 
795 	if (WARN_ON(!tbl || !table_group))
796 		return -EINVAL;
797 
798 	tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
799 			node);
800 	if (!tgl)
801 		return -ENOMEM;
802 
803 	tgl->table_group = table_group;
804 	list_add_rcu(&tgl->next, &tbl->it_group_list);
805 
806 	table_group->tables[num] = tbl;
807 
808 	return 0;
809 }
810 
811 static void pnv_iommu_table_group_link_free(struct rcu_head *head)
812 {
813 	struct iommu_table_group_link *tgl = container_of(head,
814 			struct iommu_table_group_link, rcu);
815 
816 	kfree(tgl);
817 }
818 
819 void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
820 		struct iommu_table_group *table_group)
821 {
822 	long i;
823 	bool found;
824 	struct iommu_table_group_link *tgl;
825 
826 	if (!tbl || !table_group)
827 		return;
828 
829 	/* Remove link to a group from table's list of attached groups */
830 	found = false;
831 	list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
832 		if (tgl->table_group == table_group) {
833 			list_del_rcu(&tgl->next);
834 			call_rcu(&tgl->rcu, pnv_iommu_table_group_link_free);
835 			found = true;
836 			break;
837 		}
838 	}
839 	if (WARN_ON(!found))
840 		return;
841 
842 	/* Clean a pointer to iommu_table in iommu_table_group::tables[] */
843 	found = false;
844 	for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
845 		if (table_group->tables[i] == tbl) {
846 			table_group->tables[i] = NULL;
847 			found = true;
848 			break;
849 		}
850 	}
851 	WARN_ON(!found);
852 }
853 
854 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
855 			       void *tce_mem, u64 tce_size,
856 			       u64 dma_offset, unsigned page_shift)
857 {
858 	tbl->it_blocksize = 16;
859 	tbl->it_base = (unsigned long)tce_mem;
860 	tbl->it_page_shift = page_shift;
861 	tbl->it_offset = dma_offset >> tbl->it_page_shift;
862 	tbl->it_index = 0;
863 	tbl->it_size = tce_size >> 3;
864 	tbl->it_busno = 0;
865 	tbl->it_type = TCE_PCI;
866 }
867 
868 void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
869 {
870 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
871 	struct pnv_phb *phb = hose->private_data;
872 #ifdef CONFIG_PCI_IOV
873 	struct pnv_ioda_pe *pe;
874 	struct pci_dn *pdn;
875 
876 	/* Fix the VF pdn PE number */
877 	if (pdev->is_virtfn) {
878 		pdn = pci_get_pdn(pdev);
879 		WARN_ON(pdn->pe_number != IODA_INVALID_PE);
880 		list_for_each_entry(pe, &phb->ioda.pe_list, list) {
881 			if (pe->rid == ((pdev->bus->number << 8) |
882 			    (pdev->devfn & 0xff))) {
883 				pdn->pe_number = pe->pe_number;
884 				pe->pdev = pdev;
885 				break;
886 			}
887 		}
888 	}
889 #endif /* CONFIG_PCI_IOV */
890 
891 	if (phb && phb->dma_dev_setup)
892 		phb->dma_dev_setup(phb, pdev);
893 }
894 
895 void pnv_pci_dma_bus_setup(struct pci_bus *bus)
896 {
897 	struct pci_controller *hose = bus->sysdata;
898 	struct pnv_phb *phb = hose->private_data;
899 	struct pnv_ioda_pe *pe;
900 
901 	list_for_each_entry(pe, &phb->ioda.pe_list, list) {
902 		if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
903 			continue;
904 
905 		if (!pe->pbus)
906 			continue;
907 
908 		if (bus->number == ((pe->rid >> 8) & 0xFF)) {
909 			pe->pbus = bus;
910 			break;
911 		}
912 	}
913 }
914 
915 void pnv_pci_shutdown(void)
916 {
917 	struct pci_controller *hose;
918 
919 	list_for_each_entry(hose, &hose_list, list_node)
920 		if (hose->controller_ops.shutdown)
921 			hose->controller_ops.shutdown(hose);
922 }
923 
924 /* Fixup wrong class code in p7ioc and p8 root complex */
925 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
926 {
927 	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
928 }
929 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
930 
931 void __init pnv_pci_init(void)
932 {
933 	struct device_node *np;
934 
935 	pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
936 
937 	/* If we don't have OPAL, eg. in sim, just skip PCI probe */
938 	if (!firmware_has_feature(FW_FEATURE_OPAL))
939 		return;
940 
941 	/* Look for IODA IO-Hubs. */
942 	for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
943 		pnv_pci_init_ioda_hub(np);
944 	}
945 
946 	/* Look for ioda2 built-in PHB3's */
947 	for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
948 		pnv_pci_init_ioda2_phb(np);
949 
950 	/* Look for ioda3 built-in PHB4's, we treat them as IODA2 */
951 	for_each_compatible_node(np, NULL, "ibm,ioda3-phb")
952 		pnv_pci_init_ioda2_phb(np);
953 
954 	/* Look for NPU PHBs */
955 	for_each_compatible_node(np, NULL, "ibm,ioda2-npu-phb")
956 		pnv_pci_init_npu_phb(np);
957 
958 	/*
959 	 * Look for NPU2 PHBs which we treat mostly as NPU PHBs with
960 	 * the exception of TCE kill which requires an OPAL call.
961 	 */
962 	for_each_compatible_node(np, NULL, "ibm,ioda2-npu2-phb")
963 		pnv_pci_init_npu_phb(np);
964 
965 	/* Configure IOMMU DMA hooks */
966 	set_pci_dma_ops(&dma_iommu_ops);
967 }
968 
969 machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init);
970