1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/kernel.h> 4 #include <linux/ioport.h> 5 #include <linux/bitmap.h> 6 #include <linux/pci.h> 7 8 #include <asm/opal.h> 9 10 #include "pci.h" 11 12 /* for pci_dev_is_added() */ 13 #include "../../../../drivers/pci/pci.h" 14 15 /* 16 * The majority of the complexity in supporting SR-IOV on PowerNV comes from 17 * the need to put the MMIO space for each VF into a separate PE. Internally 18 * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table". 19 * The MBT historically only applied to the 64bit MMIO window of the PHB 20 * so it's common to see it referred to as the "M64BT". 21 * 22 * An MBT entry stores the mapped range as an <base>,<mask> pair. This forces 23 * the address range that we want to map to be power-of-two sized and aligned. 24 * For conventional PCI devices this isn't really an issue since PCI device BARs 25 * have the same requirement. 26 * 27 * For a SR-IOV BAR things are a little more awkward since size and alignment 28 * are not coupled. The alignment is set based on the the per-VF BAR size, but 29 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs 30 * isn't necessarily a power of two, so neither is the total size. To fix that 31 * we need to finesse (read: hack) the Linux BAR allocator so that it will 32 * allocate the SR-IOV BARs in a way that lets us map them using the MBT. 33 * 34 * The changes to size and alignment that we need to do depend on the "mode" 35 * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above, 36 * so as a baseline we can assume that we have the following BAR modes 37 * available: 38 * 39 * NB: $PE_COUNT is the number of PEs that the PHB supports. 40 * 41 * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized 42 * segments. The n'th segment is mapped to the n'th PE. 43 * b) An un-segmented BAR that maps the whole address range to a specific PE. 44 * 45 * 46 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR 47 * For comparison b) requires one entry per-VF per-BAR, or: 48 * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment 49 * to equal the size of the per-VF BAR area. So: 50 * 51 * new_size = per-vf-size * number-of-PEs 52 * 53 * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size 54 * to "new_size", calculated above. Implementing this is a convoluted process 55 * which requires several hooks in the PCI core: 56 * 57 * 1. In pcibios_add_device() we call pnv_pci_ioda_fixup_iov(). 58 * 59 * At this point the device has been probed and the device's BARs are sized, 60 * but no resource allocations have been done. The SR-IOV BARs are sized 61 * based on the maximum number of VFs supported by the device and we need 62 * to increase that to new_size. 63 * 64 * 2. Later, when Linux actually assigns resources it tries to make the resource 65 * allocations for each PCI bus as compact as possible. As a part of that it 66 * sorts the BARs on a bus by their required alignment, which is calculated 67 * using pci_resource_alignment(). 68 * 69 * For IOV resources this goes: 70 * pci_resource_alignment() 71 * pci_sriov_resource_alignment() 72 * pcibios_sriov_resource_alignment() 73 * pnv_pci_iov_resource_alignment() 74 * 75 * Our hook overrides the default alignment, equal to the per-vf-size, with 76 * new_size computed above. 77 * 78 * 3. When userspace enables VFs for a device: 79 * 80 * sriov_enable() 81 * pcibios_sriov_enable() 82 * pnv_pcibios_sriov_enable() 83 * 84 * This is where we actually allocate PE numbers for each VF and setup the 85 * MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena" 86 * where each MBT segment is equal in size to the VF BAR so we can shift 87 * around the actual SR-IOV BAR location within this arena. We need this 88 * ability because the PE space is shared by all devices on the same PHB. 89 * When using mode a) described above segment 0 in maps to PE#0 which might 90 * be already being used by another device on the PHB. 91 * 92 * As a result we need allocate a contigious range of PE numbers, then shift 93 * the address programmed into the SR-IOV BAR of the PF so that the address 94 * of VF0 matches up with the segment corresponding to the first allocated 95 * PE number. This is handled in pnv_pci_vf_resource_shift(). 96 * 97 * Once all that is done we return to the PCI core which then enables VFs, 98 * scans them and creates pci_devs for each. The init process for a VF is 99 * largely the same as a normal device, but the VF is inserted into the IODA 100 * PE that we allocated for it rather than the PE associated with the bus. 101 * 102 * 4. When userspace disables VFs we unwind the above in 103 * pnv_pcibios_sriov_disable(). Fortunately this is relatively simple since 104 * we don't need to validate anything, just tear down the mappings and 105 * move SR-IOV resource back to its "proper" location. 106 * 107 * That's how mode a) works. In theory mode b) (single PE mapping) is less work 108 * since we can map each individual VF with a separate BAR. However, there's a 109 * few limitations: 110 * 111 * 1) For IODA2 mode b) has a minimum alignment requirement of 32MB. This makes 112 * it only usable for devices with very large per-VF BARs. Such devices are 113 * similar to Big Foot. They definitely exist, but I've never seen one. 114 * 115 * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only 116 * 16 total and some are needed for. Most SR-IOV capable network cards can support 117 * more than 16 VFs on each port. 118 * 119 * We use b) when using a) would use more than 1/4 of the entire 64 bit MMIO 120 * window of the PHB. 121 * 122 * 123 * 124 * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It 125 * allowed the MBT to map 32bit MMIO space in addition to 64bit which allows 126 * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since 127 * the Linux BAR allocation will place any BAR marked as non-prefetchable into 128 * the non-prefetchable bridge window, which is 32bit only. It also added two 129 * new modes: 130 * 131 * c) A segmented BAR similar to a), but each segment can be individually 132 * mapped to any PE. This is matches how the 32bit MMIO window worked on 133 * IODA1&2. 134 * 135 * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a), 136 * but with fewer segments and configurable base PE. 137 * 138 * i.e. The n'th segment maps to the (n + base)'th PE. 139 * 140 * The base PE is also required to be a multiple of the window size. 141 * 142 * Unfortunately, the OPAL API doesn't currently (as of skiboot v6.6) allow us 143 * to exploit any of the IODA3 features. 144 */ 145 146 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 147 { 148 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 149 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 150 struct resource *res; 151 int i; 152 resource_size_t size, total_vf_bar_sz; 153 struct pnv_iov_data *iov; 154 int mul, total_vfs; 155 156 iov = kzalloc(sizeof(*iov), GFP_KERNEL); 157 if (!iov) 158 goto truncate_iov; 159 pdev->dev.archdata.iov_data = iov; 160 161 total_vfs = pci_sriov_get_totalvfs(pdev); 162 mul = phb->ioda.total_pe_num; 163 total_vf_bar_sz = 0; 164 165 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 166 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 167 if (!res->flags || res->parent) 168 continue; 169 if (!pnv_pci_is_m64_flags(res->flags)) { 170 dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n", 171 i, res); 172 goto truncate_iov; 173 } 174 175 total_vf_bar_sz += pci_iov_resource_size(pdev, 176 i + PCI_IOV_RESOURCES); 177 178 /* 179 * If bigger than quarter of M64 segment size, just round up 180 * power of two. 181 * 182 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 183 * with other devices, IOV BAR size is expanded to be 184 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 185 * segment size , the expanded size would equal to half of the 186 * whole M64 space size, which will exhaust the M64 Space and 187 * limit the system flexibility. This is a design decision to 188 * set the boundary to quarter of the M64 segment size. 189 */ 190 if (total_vf_bar_sz > gate) { 191 mul = roundup_pow_of_two(total_vfs); 192 dev_info(&pdev->dev, 193 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 194 total_vf_bar_sz, gate, mul); 195 iov->m64_single_mode = true; 196 break; 197 } 198 } 199 200 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 201 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 202 if (!res->flags || res->parent) 203 continue; 204 205 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 206 /* 207 * On PHB3, the minimum size alignment of M64 BAR in single 208 * mode is 32MB. 209 */ 210 if (iov->m64_single_mode && (size < SZ_32M)) 211 goto truncate_iov; 212 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 213 res->end = res->start + size * mul - 1; 214 dev_dbg(&pdev->dev, " %pR\n", res); 215 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 216 i, res, mul); 217 } 218 iov->vfs_expanded = mul; 219 220 return; 221 222 truncate_iov: 223 /* To save MMIO space, IOV BAR is truncated. */ 224 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 225 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 226 res->flags = 0; 227 res->end = res->start - 1; 228 } 229 230 pdev->dev.archdata.iov_data = NULL; 231 kfree(iov); 232 } 233 234 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) 235 { 236 if (WARN_ON(pci_dev_is_added(pdev))) 237 return; 238 239 if (pdev->is_virtfn) { 240 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev); 241 242 /* 243 * VF PEs are single-device PEs so their pdev pointer needs to 244 * be set. The pdev doesn't exist when the PE is allocated (in 245 * (pcibios_sriov_enable()) so we fix it up here. 246 */ 247 pe->pdev = pdev; 248 WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); 249 } else if (pdev->is_physfn) { 250 /* 251 * For PFs adjust their allocated IOV resources to match what 252 * the PHB can support using it's M64 BAR table. 253 */ 254 pnv_pci_ioda_fixup_iov_resources(pdev); 255 } 256 } 257 258 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 259 int resno) 260 { 261 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 262 struct pnv_iov_data *iov = pnv_iov_get(pdev); 263 resource_size_t align; 264 265 /* 266 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 267 * SR-IOV. While from hardware perspective, the range mapped by M64 268 * BAR should be size aligned. 269 * 270 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 271 * powernv-specific hardware restriction is gone. But if just use the 272 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 273 * in one segment of M64 #15, which introduces the PE conflict between 274 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 275 * m64_segsize. 276 * 277 * This function returns the total IOV BAR size if M64 BAR is in 278 * Shared PE mode or just VF BAR size if not. 279 * If the M64 BAR is in Single PE mode, return the VF BAR size or 280 * M64 segment size if IOV BAR size is less. 281 */ 282 align = pci_iov_resource_size(pdev, resno); 283 284 /* 285 * iov can be null if we have an SR-IOV device with IOV BAR that can't 286 * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch). 287 * In that case we don't allow VFs to be enabled so just return the 288 * default alignment. 289 */ 290 if (!iov) 291 return align; 292 if (!iov->vfs_expanded) 293 return align; 294 if (iov->m64_single_mode) 295 return max(align, (resource_size_t)phb->ioda.m64_segsize); 296 297 return iov->vfs_expanded * align; 298 } 299 300 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 301 { 302 struct pnv_iov_data *iov; 303 struct pnv_phb *phb; 304 int i, j; 305 int m64_bars; 306 307 phb = pci_bus_to_pnvhb(pdev->bus); 308 iov = pnv_iov_get(pdev); 309 310 if (iov->m64_single_mode) 311 m64_bars = num_vfs; 312 else 313 m64_bars = 1; 314 315 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 316 for (j = 0; j < m64_bars; j++) { 317 if (iov->m64_map[j][i] == IODA_INVALID_M64) 318 continue; 319 opal_pci_phb_mmio_enable(phb->opal_id, 320 OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 0); 321 clear_bit(iov->m64_map[j][i], &phb->ioda.m64_bar_alloc); 322 iov->m64_map[j][i] = IODA_INVALID_M64; 323 } 324 325 kfree(iov->m64_map); 326 return 0; 327 } 328 329 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 330 { 331 struct pnv_iov_data *iov; 332 struct pnv_phb *phb; 333 unsigned int win; 334 struct resource *res; 335 int i, j; 336 int64_t rc; 337 int total_vfs; 338 resource_size_t size, start; 339 int pe_num; 340 int m64_bars; 341 342 phb = pci_bus_to_pnvhb(pdev->bus); 343 iov = pnv_iov_get(pdev); 344 total_vfs = pci_sriov_get_totalvfs(pdev); 345 346 if (iov->m64_single_mode) 347 m64_bars = num_vfs; 348 else 349 m64_bars = 1; 350 351 iov->m64_map = kmalloc_array(m64_bars, 352 sizeof(*iov->m64_map), 353 GFP_KERNEL); 354 if (!iov->m64_map) 355 return -ENOMEM; 356 /* Initialize the m64_map to IODA_INVALID_M64 */ 357 for (i = 0; i < m64_bars ; i++) 358 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 359 iov->m64_map[i][j] = IODA_INVALID_M64; 360 361 362 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 363 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 364 if (!res->flags || !res->parent) 365 continue; 366 367 for (j = 0; j < m64_bars; j++) { 368 do { 369 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 370 phb->ioda.m64_bar_idx + 1, 0); 371 372 if (win >= phb->ioda.m64_bar_idx + 1) 373 goto m64_failed; 374 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 375 376 iov->m64_map[j][i] = win; 377 378 if (iov->m64_single_mode) { 379 size = pci_iov_resource_size(pdev, 380 PCI_IOV_RESOURCES + i); 381 start = res->start + size * j; 382 } else { 383 size = resource_size(res); 384 start = res->start; 385 } 386 387 /* Map the M64 here */ 388 if (iov->m64_single_mode) { 389 pe_num = iov->pe_num_map[j]; 390 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 391 pe_num, OPAL_M64_WINDOW_TYPE, 392 iov->m64_map[j][i], 0); 393 } 394 395 rc = opal_pci_set_phb_mem_window(phb->opal_id, 396 OPAL_M64_WINDOW_TYPE, 397 iov->m64_map[j][i], 398 start, 399 0, /* unused */ 400 size); 401 402 403 if (rc != OPAL_SUCCESS) { 404 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 405 win, rc); 406 goto m64_failed; 407 } 408 409 if (iov->m64_single_mode) 410 rc = opal_pci_phb_mmio_enable(phb->opal_id, 411 OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 2); 412 else 413 rc = opal_pci_phb_mmio_enable(phb->opal_id, 414 OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 1); 415 416 if (rc != OPAL_SUCCESS) { 417 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 418 win, rc); 419 goto m64_failed; 420 } 421 } 422 } 423 return 0; 424 425 m64_failed: 426 pnv_pci_vf_release_m64(pdev, num_vfs); 427 return -EBUSY; 428 } 429 430 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 431 { 432 struct pnv_phb *phb; 433 struct pnv_ioda_pe *pe, *pe_n; 434 435 phb = pci_bus_to_pnvhb(pdev->bus); 436 437 if (!pdev->is_physfn) 438 return; 439 440 /* FIXME: Use pnv_ioda_release_pe()? */ 441 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 442 if (pe->parent_dev != pdev) 443 continue; 444 445 pnv_pci_ioda2_release_pe_dma(pe); 446 447 /* Remove from list */ 448 mutex_lock(&phb->ioda.pe_list_mutex); 449 list_del(&pe->list); 450 mutex_unlock(&phb->ioda.pe_list_mutex); 451 452 pnv_ioda_deconfigure_pe(phb, pe); 453 454 pnv_ioda_free_pe(pe); 455 } 456 } 457 458 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 459 { 460 struct resource *res, res2; 461 struct pnv_iov_data *iov; 462 resource_size_t size; 463 u16 num_vfs; 464 int i; 465 466 if (!dev->is_physfn) 467 return -EINVAL; 468 iov = pnv_iov_get(dev); 469 470 /* 471 * "offset" is in VFs. The M64 windows are sized so that when they 472 * are segmented, each segment is the same size as the IOV BAR. 473 * Each segment is in a separate PE, and the high order bits of the 474 * address are the PE number. Therefore, each VF's BAR is in a 475 * separate PE, and changing the IOV BAR start address changes the 476 * range of PEs the VFs are in. 477 */ 478 num_vfs = iov->num_vfs; 479 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 480 res = &dev->resource[i + PCI_IOV_RESOURCES]; 481 if (!res->flags || !res->parent) 482 continue; 483 484 /* 485 * The actual IOV BAR range is determined by the start address 486 * and the actual size for num_vfs VFs BAR. This check is to 487 * make sure that after shifting, the range will not overlap 488 * with another device. 489 */ 490 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 491 res2.flags = res->flags; 492 res2.start = res->start + (size * offset); 493 res2.end = res2.start + (size * num_vfs) - 1; 494 495 if (res2.end > res->end) { 496 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 497 i, &res2, res, num_vfs, offset); 498 return -EBUSY; 499 } 500 } 501 502 /* 503 * Since M64 BAR shares segments among all possible 256 PEs, 504 * we have to shift the beginning of PF IOV BAR to make it start from 505 * the segment which belongs to the PE number assigned to the first VF. 506 * This creates a "hole" in the /proc/iomem which could be used for 507 * allocating other resources so we reserve this area below and 508 * release when IOV is released. 509 */ 510 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 511 res = &dev->resource[i + PCI_IOV_RESOURCES]; 512 if (!res->flags || !res->parent) 513 continue; 514 515 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 516 res2 = *res; 517 res->start += size * offset; 518 519 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 520 i, &res2, res, (offset > 0) ? "En" : "Dis", 521 num_vfs, offset); 522 523 if (offset < 0) { 524 devm_release_resource(&dev->dev, &iov->holes[i]); 525 memset(&iov->holes[i], 0, sizeof(iov->holes[i])); 526 } 527 528 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 529 530 if (offset > 0) { 531 iov->holes[i].start = res2.start; 532 iov->holes[i].end = res2.start + size * offset - 1; 533 iov->holes[i].flags = IORESOURCE_BUS; 534 iov->holes[i].name = "pnv_iov_reserved"; 535 devm_request_resource(&dev->dev, res->parent, 536 &iov->holes[i]); 537 } 538 } 539 return 0; 540 } 541 542 static void pnv_pci_sriov_disable(struct pci_dev *pdev) 543 { 544 struct pnv_phb *phb; 545 struct pnv_ioda_pe *pe; 546 struct pnv_iov_data *iov; 547 u16 num_vfs, i; 548 549 phb = pci_bus_to_pnvhb(pdev->bus); 550 iov = pnv_iov_get(pdev); 551 num_vfs = iov->num_vfs; 552 553 /* Release VF PEs */ 554 pnv_ioda_release_vf_PE(pdev); 555 556 if (phb->type == PNV_PHB_IODA2) { 557 if (!iov->m64_single_mode) 558 pnv_pci_vf_resource_shift(pdev, -*iov->pe_num_map); 559 560 /* Release M64 windows */ 561 pnv_pci_vf_release_m64(pdev, num_vfs); 562 563 /* Release PE numbers */ 564 if (iov->m64_single_mode) { 565 for (i = 0; i < num_vfs; i++) { 566 if (iov->pe_num_map[i] == IODA_INVALID_PE) 567 continue; 568 569 pe = &phb->ioda.pe_array[iov->pe_num_map[i]]; 570 pnv_ioda_free_pe(pe); 571 } 572 } else 573 bitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 574 /* Releasing pe_num_map */ 575 kfree(iov->pe_num_map); 576 } 577 } 578 579 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 580 { 581 struct pnv_phb *phb; 582 struct pnv_ioda_pe *pe; 583 int pe_num; 584 u16 vf_index; 585 struct pnv_iov_data *iov; 586 struct pci_dn *pdn; 587 588 if (!pdev->is_physfn) 589 return; 590 591 phb = pci_bus_to_pnvhb(pdev->bus); 592 pdn = pci_get_pdn(pdev); 593 iov = pnv_iov_get(pdev); 594 595 /* Reserve PE for each VF */ 596 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 597 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 598 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 599 struct pci_dn *vf_pdn; 600 601 if (iov->m64_single_mode) 602 pe_num = iov->pe_num_map[vf_index]; 603 else 604 pe_num = *iov->pe_num_map + vf_index; 605 606 pe = &phb->ioda.pe_array[pe_num]; 607 pe->pe_number = pe_num; 608 pe->phb = phb; 609 pe->flags = PNV_IODA_PE_VF; 610 pe->pbus = NULL; 611 pe->parent_dev = pdev; 612 pe->mve_number = -1; 613 pe->rid = (vf_bus << 8) | vf_devfn; 614 615 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 616 pci_domain_nr(pdev->bus), pdev->bus->number, 617 PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 618 619 if (pnv_ioda_configure_pe(phb, pe)) { 620 /* XXX What do we do here ? */ 621 pnv_ioda_free_pe(pe); 622 pe->pdev = NULL; 623 continue; 624 } 625 626 /* Put PE to the list */ 627 mutex_lock(&phb->ioda.pe_list_mutex); 628 list_add_tail(&pe->list, &phb->ioda.pe_list); 629 mutex_unlock(&phb->ioda.pe_list_mutex); 630 631 /* associate this pe to it's pdn */ 632 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 633 if (vf_pdn->busno == vf_bus && 634 vf_pdn->devfn == vf_devfn) { 635 vf_pdn->pe_number = pe_num; 636 break; 637 } 638 } 639 640 pnv_pci_ioda2_setup_dma_pe(phb, pe); 641 } 642 } 643 644 static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 645 { 646 struct pnv_iov_data *iov; 647 struct pnv_phb *phb; 648 struct pnv_ioda_pe *pe; 649 int ret; 650 u16 i; 651 652 phb = pci_bus_to_pnvhb(pdev->bus); 653 iov = pnv_iov_get(pdev); 654 655 if (phb->type == PNV_PHB_IODA2) { 656 if (!iov->vfs_expanded) { 657 dev_info(&pdev->dev, 658 "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n"); 659 return -ENOSPC; 660 } 661 662 /* 663 * When M64 BARs functions in Single PE mode, the number of VFs 664 * could be enabled must be less than the number of M64 BARs. 665 */ 666 if (iov->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 667 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 668 return -EBUSY; 669 } 670 671 /* Allocating pe_num_map */ 672 if (iov->m64_single_mode) 673 iov->pe_num_map = kmalloc_array(num_vfs, 674 sizeof(*iov->pe_num_map), 675 GFP_KERNEL); 676 else 677 iov->pe_num_map = kmalloc(sizeof(*iov->pe_num_map), GFP_KERNEL); 678 679 if (!iov->pe_num_map) 680 return -ENOMEM; 681 682 if (iov->m64_single_mode) 683 for (i = 0; i < num_vfs; i++) 684 iov->pe_num_map[i] = IODA_INVALID_PE; 685 686 /* Calculate available PE for required VFs */ 687 if (iov->m64_single_mode) { 688 for (i = 0; i < num_vfs; i++) { 689 pe = pnv_ioda_alloc_pe(phb); 690 if (!pe) { 691 ret = -EBUSY; 692 goto m64_failed; 693 } 694 695 iov->pe_num_map[i] = pe->pe_number; 696 } 697 } else { 698 mutex_lock(&phb->ioda.pe_alloc_mutex); 699 *iov->pe_num_map = bitmap_find_next_zero_area( 700 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 701 0, num_vfs, 0); 702 if (*iov->pe_num_map >= phb->ioda.total_pe_num) { 703 mutex_unlock(&phb->ioda.pe_alloc_mutex); 704 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 705 kfree(iov->pe_num_map); 706 return -EBUSY; 707 } 708 bitmap_set(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 709 mutex_unlock(&phb->ioda.pe_alloc_mutex); 710 } 711 iov->num_vfs = num_vfs; 712 713 /* Assign M64 window accordingly */ 714 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 715 if (ret) { 716 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 717 goto m64_failed; 718 } 719 720 /* 721 * When using one M64 BAR to map one IOV BAR, we need to shift 722 * the IOV BAR according to the PE# allocated to the VFs. 723 * Otherwise, the PE# for the VF will conflict with others. 724 */ 725 if (!iov->m64_single_mode) { 726 ret = pnv_pci_vf_resource_shift(pdev, *iov->pe_num_map); 727 if (ret) 728 goto m64_failed; 729 } 730 } 731 732 /* Setup VF PEs */ 733 pnv_ioda_setup_vf_PE(pdev, num_vfs); 734 735 return 0; 736 737 m64_failed: 738 if (iov->m64_single_mode) { 739 for (i = 0; i < num_vfs; i++) { 740 if (iov->pe_num_map[i] == IODA_INVALID_PE) 741 continue; 742 743 pe = &phb->ioda.pe_array[iov->pe_num_map[i]]; 744 pnv_ioda_free_pe(pe); 745 } 746 } else 747 bitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 748 749 /* Releasing pe_num_map */ 750 kfree(iov->pe_num_map); 751 752 return ret; 753 } 754 755 int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 756 { 757 pnv_pci_sriov_disable(pdev); 758 759 /* Release PCI data */ 760 remove_sriov_vf_pdns(pdev); 761 return 0; 762 } 763 764 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 765 { 766 /* Allocate PCI data */ 767 add_sriov_vf_pdns(pdev); 768 769 return pnv_pci_sriov_enable(pdev, num_vfs); 770 } 771