1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/kernel.h> 4 #include <linux/ioport.h> 5 #include <linux/bitmap.h> 6 #include <linux/pci.h> 7 8 #include <asm/opal.h> 9 10 #include "pci.h" 11 12 /* for pci_dev_is_added() */ 13 #include "../../../../drivers/pci/pci.h" 14 15 /* 16 * The majority of the complexity in supporting SR-IOV on PowerNV comes from 17 * the need to put the MMIO space for each VF into a separate PE. Internally 18 * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table". 19 * The MBT historically only applied to the 64bit MMIO window of the PHB 20 * so it's common to see it referred to as the "M64BT". 21 * 22 * An MBT entry stores the mapped range as an <base>,<mask> pair. This forces 23 * the address range that we want to map to be power-of-two sized and aligned. 24 * For conventional PCI devices this isn't really an issue since PCI device BARs 25 * have the same requirement. 26 * 27 * For a SR-IOV BAR things are a little more awkward since size and alignment 28 * are not coupled. The alignment is set based on the the per-VF BAR size, but 29 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs 30 * isn't necessarily a power of two, so neither is the total size. To fix that 31 * we need to finesse (read: hack) the Linux BAR allocator so that it will 32 * allocate the SR-IOV BARs in a way that lets us map them using the MBT. 33 * 34 * The changes to size and alignment that we need to do depend on the "mode" 35 * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above, 36 * so as a baseline we can assume that we have the following BAR modes 37 * available: 38 * 39 * NB: $PE_COUNT is the number of PEs that the PHB supports. 40 * 41 * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized 42 * segments. The n'th segment is mapped to the n'th PE. 43 * b) An un-segmented BAR that maps the whole address range to a specific PE. 44 * 45 * 46 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR 47 * For comparison b) requires one entry per-VF per-BAR, or: 48 * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment 49 * to equal the size of the per-VF BAR area. So: 50 * 51 * new_size = per-vf-size * number-of-PEs 52 * 53 * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size 54 * to "new_size", calculated above. Implementing this is a convoluted process 55 * which requires several hooks in the PCI core: 56 * 57 * 1. In pcibios_add_device() we call pnv_pci_ioda_fixup_iov(). 58 * 59 * At this point the device has been probed and the device's BARs are sized, 60 * but no resource allocations have been done. The SR-IOV BARs are sized 61 * based on the maximum number of VFs supported by the device and we need 62 * to increase that to new_size. 63 * 64 * 2. Later, when Linux actually assigns resources it tries to make the resource 65 * allocations for each PCI bus as compact as possible. As a part of that it 66 * sorts the BARs on a bus by their required alignment, which is calculated 67 * using pci_resource_alignment(). 68 * 69 * For IOV resources this goes: 70 * pci_resource_alignment() 71 * pci_sriov_resource_alignment() 72 * pcibios_sriov_resource_alignment() 73 * pnv_pci_iov_resource_alignment() 74 * 75 * Our hook overrides the default alignment, equal to the per-vf-size, with 76 * new_size computed above. 77 * 78 * 3. When userspace enables VFs for a device: 79 * 80 * sriov_enable() 81 * pcibios_sriov_enable() 82 * pnv_pcibios_sriov_enable() 83 * 84 * This is where we actually allocate PE numbers for each VF and setup the 85 * MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena" 86 * where each MBT segment is equal in size to the VF BAR so we can shift 87 * around the actual SR-IOV BAR location within this arena. We need this 88 * ability because the PE space is shared by all devices on the same PHB. 89 * When using mode a) described above segment 0 in maps to PE#0 which might 90 * be already being used by another device on the PHB. 91 * 92 * As a result we need allocate a contigious range of PE numbers, then shift 93 * the address programmed into the SR-IOV BAR of the PF so that the address 94 * of VF0 matches up with the segment corresponding to the first allocated 95 * PE number. This is handled in pnv_pci_vf_resource_shift(). 96 * 97 * Once all that is done we return to the PCI core which then enables VFs, 98 * scans them and creates pci_devs for each. The init process for a VF is 99 * largely the same as a normal device, but the VF is inserted into the IODA 100 * PE that we allocated for it rather than the PE associated with the bus. 101 * 102 * 4. When userspace disables VFs we unwind the above in 103 * pnv_pcibios_sriov_disable(). Fortunately this is relatively simple since 104 * we don't need to validate anything, just tear down the mappings and 105 * move SR-IOV resource back to its "proper" location. 106 * 107 * That's how mode a) works. In theory mode b) (single PE mapping) is less work 108 * since we can map each individual VF with a separate BAR. However, there's a 109 * few limitations: 110 * 111 * 1) For IODA2 mode b) has a minimum alignment requirement of 32MB. This makes 112 * it only usable for devices with very large per-VF BARs. Such devices are 113 * similar to Big Foot. They definitely exist, but I've never seen one. 114 * 115 * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only 116 * 16 total and some are needed for. Most SR-IOV capable network cards can support 117 * more than 16 VFs on each port. 118 * 119 * We use b) when using a) would use more than 1/4 of the entire 64 bit MMIO 120 * window of the PHB. 121 * 122 * 123 * 124 * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It 125 * allowed the MBT to map 32bit MMIO space in addition to 64bit which allows 126 * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since 127 * the Linux BAR allocation will place any BAR marked as non-prefetchable into 128 * the non-prefetchable bridge window, which is 32bit only. It also added two 129 * new modes: 130 * 131 * c) A segmented BAR similar to a), but each segment can be individually 132 * mapped to any PE. This is matches how the 32bit MMIO window worked on 133 * IODA1&2. 134 * 135 * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a), 136 * but with fewer segments and configurable base PE. 137 * 138 * i.e. The n'th segment maps to the (n + base)'th PE. 139 * 140 * The base PE is also required to be a multiple of the window size. 141 * 142 * Unfortunately, the OPAL API doesn't currently (as of skiboot v6.6) allow us 143 * to exploit any of the IODA3 features. 144 */ 145 146 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 147 { 148 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 149 const resource_size_t gate = phb->ioda.m64_segsize >> 2; 150 struct resource *res; 151 int i; 152 resource_size_t size, total_vf_bar_sz; 153 struct pnv_iov_data *iov; 154 int mul, total_vfs; 155 156 iov = kzalloc(sizeof(*iov), GFP_KERNEL); 157 if (!iov) 158 goto disable_iov; 159 pdev->dev.archdata.iov_data = iov; 160 161 total_vfs = pci_sriov_get_totalvfs(pdev); 162 mul = phb->ioda.total_pe_num; 163 total_vf_bar_sz = 0; 164 165 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 166 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 167 if (!res->flags || res->parent) 168 continue; 169 if (!pnv_pci_is_m64_flags(res->flags)) { 170 dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n", 171 i, res); 172 goto disable_iov; 173 } 174 175 total_vf_bar_sz += pci_iov_resource_size(pdev, 176 i + PCI_IOV_RESOURCES); 177 178 /* 179 * If bigger than quarter of M64 segment size, just round up 180 * power of two. 181 * 182 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 183 * with other devices, IOV BAR size is expanded to be 184 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 185 * segment size , the expanded size would equal to half of the 186 * whole M64 space size, which will exhaust the M64 Space and 187 * limit the system flexibility. This is a design decision to 188 * set the boundary to quarter of the M64 segment size. 189 */ 190 if (total_vf_bar_sz > gate) { 191 mul = roundup_pow_of_two(total_vfs); 192 dev_info(&pdev->dev, 193 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 194 total_vf_bar_sz, gate, mul); 195 iov->m64_single_mode = true; 196 break; 197 } 198 } 199 200 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 201 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 202 if (!res->flags || res->parent) 203 continue; 204 205 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 206 /* 207 * On PHB3, the minimum size alignment of M64 BAR in single 208 * mode is 32MB. 209 */ 210 if (iov->m64_single_mode && (size < SZ_32M)) 211 goto disable_iov; 212 213 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 214 res->end = res->start + size * mul - 1; 215 dev_dbg(&pdev->dev, " %pR\n", res); 216 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 217 i, res, mul); 218 } 219 iov->vfs_expanded = mul; 220 221 return; 222 223 disable_iov: 224 /* Save ourselves some MMIO space by disabling the unusable BARs */ 225 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 226 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 227 res->flags = 0; 228 res->end = res->start - 1; 229 } 230 231 pdev->dev.archdata.iov_data = NULL; 232 kfree(iov); 233 } 234 235 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) 236 { 237 if (WARN_ON(pci_dev_is_added(pdev))) 238 return; 239 240 if (pdev->is_virtfn) { 241 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev); 242 243 /* 244 * VF PEs are single-device PEs so their pdev pointer needs to 245 * be set. The pdev doesn't exist when the PE is allocated (in 246 * (pcibios_sriov_enable()) so we fix it up here. 247 */ 248 pe->pdev = pdev; 249 WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); 250 } else if (pdev->is_physfn) { 251 /* 252 * For PFs adjust their allocated IOV resources to match what 253 * the PHB can support using it's M64 BAR table. 254 */ 255 pnv_pci_ioda_fixup_iov_resources(pdev); 256 } 257 } 258 259 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 260 int resno) 261 { 262 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 263 struct pnv_iov_data *iov = pnv_iov_get(pdev); 264 resource_size_t align; 265 266 /* 267 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 268 * SR-IOV. While from hardware perspective, the range mapped by M64 269 * BAR should be size aligned. 270 * 271 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 272 * powernv-specific hardware restriction is gone. But if just use the 273 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 274 * in one segment of M64 #15, which introduces the PE conflict between 275 * PF and VF. Based on this, the minimum alignment of an IOV BAR is 276 * m64_segsize. 277 * 278 * This function returns the total IOV BAR size if M64 BAR is in 279 * Shared PE mode or just VF BAR size if not. 280 * If the M64 BAR is in Single PE mode, return the VF BAR size or 281 * M64 segment size if IOV BAR size is less. 282 */ 283 align = pci_iov_resource_size(pdev, resno); 284 285 /* 286 * iov can be null if we have an SR-IOV device with IOV BAR that can't 287 * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch). 288 * In that case we don't allow VFs to be enabled so just return the 289 * default alignment. 290 */ 291 if (!iov) 292 return align; 293 if (!iov->vfs_expanded) 294 return align; 295 if (iov->m64_single_mode) 296 return max(align, (resource_size_t)phb->ioda.m64_segsize); 297 298 return iov->vfs_expanded * align; 299 } 300 301 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 302 { 303 struct pnv_iov_data *iov; 304 struct pnv_phb *phb; 305 int i, j; 306 int m64_bars; 307 308 phb = pci_bus_to_pnvhb(pdev->bus); 309 iov = pnv_iov_get(pdev); 310 311 if (iov->m64_single_mode) 312 m64_bars = num_vfs; 313 else 314 m64_bars = 1; 315 316 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 317 for (j = 0; j < m64_bars; j++) { 318 if (iov->m64_map[j][i] == IODA_INVALID_M64) 319 continue; 320 opal_pci_phb_mmio_enable(phb->opal_id, 321 OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 0); 322 clear_bit(iov->m64_map[j][i], &phb->ioda.m64_bar_alloc); 323 iov->m64_map[j][i] = IODA_INVALID_M64; 324 } 325 326 kfree(iov->m64_map); 327 return 0; 328 } 329 330 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 331 { 332 struct pnv_iov_data *iov; 333 struct pnv_phb *phb; 334 unsigned int win; 335 struct resource *res; 336 int i, j; 337 int64_t rc; 338 int total_vfs; 339 resource_size_t size, start; 340 int pe_num; 341 int m64_bars; 342 343 phb = pci_bus_to_pnvhb(pdev->bus); 344 iov = pnv_iov_get(pdev); 345 total_vfs = pci_sriov_get_totalvfs(pdev); 346 347 if (iov->m64_single_mode) 348 m64_bars = num_vfs; 349 else 350 m64_bars = 1; 351 352 iov->m64_map = kmalloc_array(m64_bars, 353 sizeof(*iov->m64_map), 354 GFP_KERNEL); 355 if (!iov->m64_map) 356 return -ENOMEM; 357 /* Initialize the m64_map to IODA_INVALID_M64 */ 358 for (i = 0; i < m64_bars ; i++) 359 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 360 iov->m64_map[i][j] = IODA_INVALID_M64; 361 362 363 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 364 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 365 if (!res->flags || !res->parent) 366 continue; 367 368 for (j = 0; j < m64_bars; j++) { 369 do { 370 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 371 phb->ioda.m64_bar_idx + 1, 0); 372 373 if (win >= phb->ioda.m64_bar_idx + 1) 374 goto m64_failed; 375 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 376 377 iov->m64_map[j][i] = win; 378 379 if (iov->m64_single_mode) { 380 size = pci_iov_resource_size(pdev, 381 PCI_IOV_RESOURCES + i); 382 start = res->start + size * j; 383 } else { 384 size = resource_size(res); 385 start = res->start; 386 } 387 388 /* Map the M64 here */ 389 if (iov->m64_single_mode) { 390 pe_num = iov->pe_num_map[j]; 391 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 392 pe_num, OPAL_M64_WINDOW_TYPE, 393 iov->m64_map[j][i], 0); 394 } 395 396 rc = opal_pci_set_phb_mem_window(phb->opal_id, 397 OPAL_M64_WINDOW_TYPE, 398 iov->m64_map[j][i], 399 start, 400 0, /* unused */ 401 size); 402 403 404 if (rc != OPAL_SUCCESS) { 405 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 406 win, rc); 407 goto m64_failed; 408 } 409 410 if (iov->m64_single_mode) 411 rc = opal_pci_phb_mmio_enable(phb->opal_id, 412 OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 2); 413 else 414 rc = opal_pci_phb_mmio_enable(phb->opal_id, 415 OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 1); 416 417 if (rc != OPAL_SUCCESS) { 418 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 419 win, rc); 420 goto m64_failed; 421 } 422 } 423 } 424 return 0; 425 426 m64_failed: 427 pnv_pci_vf_release_m64(pdev, num_vfs); 428 return -EBUSY; 429 } 430 431 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 432 { 433 struct pnv_phb *phb; 434 struct pnv_ioda_pe *pe, *pe_n; 435 436 phb = pci_bus_to_pnvhb(pdev->bus); 437 438 if (!pdev->is_physfn) 439 return; 440 441 /* FIXME: Use pnv_ioda_release_pe()? */ 442 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 443 if (pe->parent_dev != pdev) 444 continue; 445 446 pnv_pci_ioda2_release_pe_dma(pe); 447 448 /* Remove from list */ 449 mutex_lock(&phb->ioda.pe_list_mutex); 450 list_del(&pe->list); 451 mutex_unlock(&phb->ioda.pe_list_mutex); 452 453 pnv_ioda_deconfigure_pe(phb, pe); 454 455 pnv_ioda_free_pe(pe); 456 } 457 } 458 459 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 460 { 461 struct resource *res, res2; 462 struct pnv_iov_data *iov; 463 resource_size_t size; 464 u16 num_vfs; 465 int i; 466 467 if (!dev->is_physfn) 468 return -EINVAL; 469 iov = pnv_iov_get(dev); 470 471 /* 472 * "offset" is in VFs. The M64 windows are sized so that when they 473 * are segmented, each segment is the same size as the IOV BAR. 474 * Each segment is in a separate PE, and the high order bits of the 475 * address are the PE number. Therefore, each VF's BAR is in a 476 * separate PE, and changing the IOV BAR start address changes the 477 * range of PEs the VFs are in. 478 */ 479 num_vfs = iov->num_vfs; 480 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 481 res = &dev->resource[i + PCI_IOV_RESOURCES]; 482 if (!res->flags || !res->parent) 483 continue; 484 485 /* 486 * The actual IOV BAR range is determined by the start address 487 * and the actual size for num_vfs VFs BAR. This check is to 488 * make sure that after shifting, the range will not overlap 489 * with another device. 490 */ 491 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 492 res2.flags = res->flags; 493 res2.start = res->start + (size * offset); 494 res2.end = res2.start + (size * num_vfs) - 1; 495 496 if (res2.end > res->end) { 497 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 498 i, &res2, res, num_vfs, offset); 499 return -EBUSY; 500 } 501 } 502 503 /* 504 * Since M64 BAR shares segments among all possible 256 PEs, 505 * we have to shift the beginning of PF IOV BAR to make it start from 506 * the segment which belongs to the PE number assigned to the first VF. 507 * This creates a "hole" in the /proc/iomem which could be used for 508 * allocating other resources so we reserve this area below and 509 * release when IOV is released. 510 */ 511 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 512 res = &dev->resource[i + PCI_IOV_RESOURCES]; 513 if (!res->flags || !res->parent) 514 continue; 515 516 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 517 res2 = *res; 518 res->start += size * offset; 519 520 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 521 i, &res2, res, (offset > 0) ? "En" : "Dis", 522 num_vfs, offset); 523 524 if (offset < 0) { 525 devm_release_resource(&dev->dev, &iov->holes[i]); 526 memset(&iov->holes[i], 0, sizeof(iov->holes[i])); 527 } 528 529 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 530 531 if (offset > 0) { 532 iov->holes[i].start = res2.start; 533 iov->holes[i].end = res2.start + size * offset - 1; 534 iov->holes[i].flags = IORESOURCE_BUS; 535 iov->holes[i].name = "pnv_iov_reserved"; 536 devm_request_resource(&dev->dev, res->parent, 537 &iov->holes[i]); 538 } 539 } 540 return 0; 541 } 542 543 static void pnv_pci_sriov_disable(struct pci_dev *pdev) 544 { 545 struct pnv_phb *phb; 546 struct pnv_ioda_pe *pe; 547 struct pnv_iov_data *iov; 548 u16 num_vfs, i; 549 550 phb = pci_bus_to_pnvhb(pdev->bus); 551 iov = pnv_iov_get(pdev); 552 num_vfs = iov->num_vfs; 553 554 /* Release VF PEs */ 555 pnv_ioda_release_vf_PE(pdev); 556 557 if (phb->type == PNV_PHB_IODA2) { 558 if (!iov->m64_single_mode) 559 pnv_pci_vf_resource_shift(pdev, -*iov->pe_num_map); 560 561 /* Release M64 windows */ 562 pnv_pci_vf_release_m64(pdev, num_vfs); 563 564 /* Release PE numbers */ 565 if (iov->m64_single_mode) { 566 for (i = 0; i < num_vfs; i++) { 567 if (iov->pe_num_map[i] == IODA_INVALID_PE) 568 continue; 569 570 pe = &phb->ioda.pe_array[iov->pe_num_map[i]]; 571 pnv_ioda_free_pe(pe); 572 } 573 } else 574 bitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 575 /* Releasing pe_num_map */ 576 kfree(iov->pe_num_map); 577 } 578 } 579 580 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 581 { 582 struct pnv_phb *phb; 583 struct pnv_ioda_pe *pe; 584 int pe_num; 585 u16 vf_index; 586 struct pnv_iov_data *iov; 587 struct pci_dn *pdn; 588 589 if (!pdev->is_physfn) 590 return; 591 592 phb = pci_bus_to_pnvhb(pdev->bus); 593 pdn = pci_get_pdn(pdev); 594 iov = pnv_iov_get(pdev); 595 596 /* Reserve PE for each VF */ 597 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 598 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 599 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 600 struct pci_dn *vf_pdn; 601 602 if (iov->m64_single_mode) 603 pe_num = iov->pe_num_map[vf_index]; 604 else 605 pe_num = *iov->pe_num_map + vf_index; 606 607 pe = &phb->ioda.pe_array[pe_num]; 608 pe->pe_number = pe_num; 609 pe->phb = phb; 610 pe->flags = PNV_IODA_PE_VF; 611 pe->pbus = NULL; 612 pe->parent_dev = pdev; 613 pe->mve_number = -1; 614 pe->rid = (vf_bus << 8) | vf_devfn; 615 616 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 617 pci_domain_nr(pdev->bus), pdev->bus->number, 618 PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 619 620 if (pnv_ioda_configure_pe(phb, pe)) { 621 /* XXX What do we do here ? */ 622 pnv_ioda_free_pe(pe); 623 pe->pdev = NULL; 624 continue; 625 } 626 627 /* Put PE to the list */ 628 mutex_lock(&phb->ioda.pe_list_mutex); 629 list_add_tail(&pe->list, &phb->ioda.pe_list); 630 mutex_unlock(&phb->ioda.pe_list_mutex); 631 632 /* associate this pe to it's pdn */ 633 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 634 if (vf_pdn->busno == vf_bus && 635 vf_pdn->devfn == vf_devfn) { 636 vf_pdn->pe_number = pe_num; 637 break; 638 } 639 } 640 641 pnv_pci_ioda2_setup_dma_pe(phb, pe); 642 } 643 } 644 645 static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 646 { 647 struct pnv_iov_data *iov; 648 struct pnv_phb *phb; 649 struct pnv_ioda_pe *pe; 650 int ret; 651 u16 i; 652 653 phb = pci_bus_to_pnvhb(pdev->bus); 654 iov = pnv_iov_get(pdev); 655 656 if (phb->type == PNV_PHB_IODA2) { 657 if (!iov->vfs_expanded) { 658 dev_info(&pdev->dev, 659 "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n"); 660 return -ENOSPC; 661 } 662 663 /* 664 * When M64 BARs functions in Single PE mode, the number of VFs 665 * could be enabled must be less than the number of M64 BARs. 666 */ 667 if (iov->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 668 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 669 return -EBUSY; 670 } 671 672 /* Allocating pe_num_map */ 673 if (iov->m64_single_mode) 674 iov->pe_num_map = kmalloc_array(num_vfs, 675 sizeof(*iov->pe_num_map), 676 GFP_KERNEL); 677 else 678 iov->pe_num_map = kmalloc(sizeof(*iov->pe_num_map), GFP_KERNEL); 679 680 if (!iov->pe_num_map) 681 return -ENOMEM; 682 683 if (iov->m64_single_mode) 684 for (i = 0; i < num_vfs; i++) 685 iov->pe_num_map[i] = IODA_INVALID_PE; 686 687 /* Calculate available PE for required VFs */ 688 if (iov->m64_single_mode) { 689 for (i = 0; i < num_vfs; i++) { 690 pe = pnv_ioda_alloc_pe(phb); 691 if (!pe) { 692 ret = -EBUSY; 693 goto m64_failed; 694 } 695 696 iov->pe_num_map[i] = pe->pe_number; 697 } 698 } else { 699 mutex_lock(&phb->ioda.pe_alloc_mutex); 700 *iov->pe_num_map = bitmap_find_next_zero_area( 701 phb->ioda.pe_alloc, phb->ioda.total_pe_num, 702 0, num_vfs, 0); 703 if (*iov->pe_num_map >= phb->ioda.total_pe_num) { 704 mutex_unlock(&phb->ioda.pe_alloc_mutex); 705 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 706 kfree(iov->pe_num_map); 707 return -EBUSY; 708 } 709 bitmap_set(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 710 mutex_unlock(&phb->ioda.pe_alloc_mutex); 711 } 712 iov->num_vfs = num_vfs; 713 714 /* Assign M64 window accordingly */ 715 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 716 if (ret) { 717 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 718 goto m64_failed; 719 } 720 721 /* 722 * When using one M64 BAR to map one IOV BAR, we need to shift 723 * the IOV BAR according to the PE# allocated to the VFs. 724 * Otherwise, the PE# for the VF will conflict with others. 725 */ 726 if (!iov->m64_single_mode) { 727 ret = pnv_pci_vf_resource_shift(pdev, *iov->pe_num_map); 728 if (ret) 729 goto m64_failed; 730 } 731 } 732 733 /* Setup VF PEs */ 734 pnv_ioda_setup_vf_PE(pdev, num_vfs); 735 736 return 0; 737 738 m64_failed: 739 if (iov->m64_single_mode) { 740 for (i = 0; i < num_vfs; i++) { 741 if (iov->pe_num_map[i] == IODA_INVALID_PE) 742 continue; 743 744 pe = &phb->ioda.pe_array[iov->pe_num_map[i]]; 745 pnv_ioda_free_pe(pe); 746 } 747 } else 748 bitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 749 750 /* Releasing pe_num_map */ 751 kfree(iov->pe_num_map); 752 753 return ret; 754 } 755 756 int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 757 { 758 pnv_pci_sriov_disable(pdev); 759 760 /* Release PCI data */ 761 remove_sriov_vf_pdns(pdev); 762 return 0; 763 } 764 765 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 766 { 767 /* Allocate PCI data */ 768 add_sriov_vf_pdns(pdev); 769 770 return pnv_pci_sriov_enable(pdev, num_vfs); 771 } 772