1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 #include <linux/kernel.h> 4 #include <linux/ioport.h> 5 #include <linux/bitmap.h> 6 #include <linux/pci.h> 7 8 #include <asm/opal.h> 9 10 #include "pci.h" 11 12 /* for pci_dev_is_added() */ 13 #include "../../../../drivers/pci/pci.h" 14 15 /* 16 * The majority of the complexity in supporting SR-IOV on PowerNV comes from 17 * the need to put the MMIO space for each VF into a separate PE. Internally 18 * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table". 19 * The MBT historically only applied to the 64bit MMIO window of the PHB 20 * so it's common to see it referred to as the "M64BT". 21 * 22 * An MBT entry stores the mapped range as an <base>,<mask> pair. This forces 23 * the address range that we want to map to be power-of-two sized and aligned. 24 * For conventional PCI devices this isn't really an issue since PCI device BARs 25 * have the same requirement. 26 * 27 * For a SR-IOV BAR things are a little more awkward since size and alignment 28 * are not coupled. The alignment is set based on the the per-VF BAR size, but 29 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs 30 * isn't necessarily a power of two, so neither is the total size. To fix that 31 * we need to finesse (read: hack) the Linux BAR allocator so that it will 32 * allocate the SR-IOV BARs in a way that lets us map them using the MBT. 33 * 34 * The changes to size and alignment that we need to do depend on the "mode" 35 * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above, 36 * so as a baseline we can assume that we have the following BAR modes 37 * available: 38 * 39 * NB: $PE_COUNT is the number of PEs that the PHB supports. 40 * 41 * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized 42 * segments. The n'th segment is mapped to the n'th PE. 43 * b) An un-segmented BAR that maps the whole address range to a specific PE. 44 * 45 * 46 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR 47 * For comparison b) requires one entry per-VF per-BAR, or: 48 * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment 49 * to equal the size of the per-VF BAR area. So: 50 * 51 * new_size = per-vf-size * number-of-PEs 52 * 53 * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size 54 * to "new_size", calculated above. Implementing this is a convoluted process 55 * which requires several hooks in the PCI core: 56 * 57 * 1. In pcibios_add_device() we call pnv_pci_ioda_fixup_iov(). 58 * 59 * At this point the device has been probed and the device's BARs are sized, 60 * but no resource allocations have been done. The SR-IOV BARs are sized 61 * based on the maximum number of VFs supported by the device and we need 62 * to increase that to new_size. 63 * 64 * 2. Later, when Linux actually assigns resources it tries to make the resource 65 * allocations for each PCI bus as compact as possible. As a part of that it 66 * sorts the BARs on a bus by their required alignment, which is calculated 67 * using pci_resource_alignment(). 68 * 69 * For IOV resources this goes: 70 * pci_resource_alignment() 71 * pci_sriov_resource_alignment() 72 * pcibios_sriov_resource_alignment() 73 * pnv_pci_iov_resource_alignment() 74 * 75 * Our hook overrides the default alignment, equal to the per-vf-size, with 76 * new_size computed above. 77 * 78 * 3. When userspace enables VFs for a device: 79 * 80 * sriov_enable() 81 * pcibios_sriov_enable() 82 * pnv_pcibios_sriov_enable() 83 * 84 * This is where we actually allocate PE numbers for each VF and setup the 85 * MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena" 86 * where each MBT segment is equal in size to the VF BAR so we can shift 87 * around the actual SR-IOV BAR location within this arena. We need this 88 * ability because the PE space is shared by all devices on the same PHB. 89 * When using mode a) described above segment 0 in maps to PE#0 which might 90 * be already being used by another device on the PHB. 91 * 92 * As a result we need allocate a contigious range of PE numbers, then shift 93 * the address programmed into the SR-IOV BAR of the PF so that the address 94 * of VF0 matches up with the segment corresponding to the first allocated 95 * PE number. This is handled in pnv_pci_vf_resource_shift(). 96 * 97 * Once all that is done we return to the PCI core which then enables VFs, 98 * scans them and creates pci_devs for each. The init process for a VF is 99 * largely the same as a normal device, but the VF is inserted into the IODA 100 * PE that we allocated for it rather than the PE associated with the bus. 101 * 102 * 4. When userspace disables VFs we unwind the above in 103 * pnv_pcibios_sriov_disable(). Fortunately this is relatively simple since 104 * we don't need to validate anything, just tear down the mappings and 105 * move SR-IOV resource back to its "proper" location. 106 * 107 * That's how mode a) works. In theory mode b) (single PE mapping) is less work 108 * since we can map each individual VF with a separate BAR. However, there's a 109 * few limitations: 110 * 111 * 1) For IODA2 mode b) has a minimum alignment requirement of 32MB. This makes 112 * it only usable for devices with very large per-VF BARs. Such devices are 113 * similar to Big Foot. They definitely exist, but I've never seen one. 114 * 115 * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only 116 * 16 total and some are needed for. Most SR-IOV capable network cards can support 117 * more than 16 VFs on each port. 118 * 119 * We use b) when using a) would use more than 1/4 of the entire 64 bit MMIO 120 * window of the PHB. 121 * 122 * 123 * 124 * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It 125 * allowed the MBT to map 32bit MMIO space in addition to 64bit which allows 126 * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since 127 * the Linux BAR allocation will place any BAR marked as non-prefetchable into 128 * the non-prefetchable bridge window, which is 32bit only. It also added two 129 * new modes: 130 * 131 * c) A segmented BAR similar to a), but each segment can be individually 132 * mapped to any PE. This is matches how the 32bit MMIO window worked on 133 * IODA1&2. 134 * 135 * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a), 136 * but with fewer segments and configurable base PE. 137 * 138 * i.e. The n'th segment maps to the (n + base)'th PE. 139 * 140 * The base PE is also required to be a multiple of the window size. 141 * 142 * Unfortunately, the OPAL API doesn't currently (as of skiboot v6.6) allow us 143 * to exploit any of the IODA3 features. 144 */ 145 146 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 147 { 148 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 149 struct resource *res; 150 int i; 151 resource_size_t vf_bar_sz; 152 struct pnv_iov_data *iov; 153 int mul; 154 155 iov = kzalloc(sizeof(*iov), GFP_KERNEL); 156 if (!iov) 157 goto disable_iov; 158 pdev->dev.archdata.iov_data = iov; 159 mul = phb->ioda.total_pe_num; 160 161 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 162 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 163 if (!res->flags || res->parent) 164 continue; 165 if (!pnv_pci_is_m64_flags(res->flags)) { 166 dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n", 167 i, res); 168 goto disable_iov; 169 } 170 171 vf_bar_sz = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 172 173 /* 174 * Generally, one segmented M64 BAR maps one IOV BAR. However, 175 * if a VF BAR is too large we end up wasting a lot of space. 176 * If each VF needs more than 1/4 of the default m64 segment 177 * then each VF BAR should be mapped in single-PE mode to reduce 178 * the amount of space required. This does however limit the 179 * number of VFs we can support. 180 * 181 * The 1/4 limit is arbitrary and can be tweaked. 182 */ 183 if (vf_bar_sz > (phb->ioda.m64_segsize >> 2)) { 184 /* 185 * On PHB3, the minimum size alignment of M64 BAR in 186 * single mode is 32MB. If this VF BAR is smaller than 187 * 32MB, but still too large for a segmented window 188 * then we can't map it and need to disable SR-IOV for 189 * this device. 190 */ 191 if (vf_bar_sz < SZ_32M) { 192 pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n", 193 i, res); 194 goto disable_iov; 195 } 196 197 iov->m64_single_mode[i] = true; 198 continue; 199 } 200 201 /* 202 * This BAR can be mapped with one segmented window, so adjust 203 * te resource size to accommodate. 204 */ 205 pci_dbg(pdev, " Fixing VF BAR%d: %pR to\n", i, res); 206 res->end = res->start + vf_bar_sz * mul - 1; 207 pci_dbg(pdev, " %pR\n", res); 208 209 pci_info(pdev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 210 i, res, mul); 211 212 iov->need_shift = true; 213 } 214 215 iov->vfs_expanded = mul; 216 217 return; 218 219 disable_iov: 220 /* Save ourselves some MMIO space by disabling the unusable BARs */ 221 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 222 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 223 res->flags = 0; 224 res->end = res->start - 1; 225 } 226 227 pdev->dev.archdata.iov_data = NULL; 228 kfree(iov); 229 } 230 231 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) 232 { 233 if (WARN_ON(pci_dev_is_added(pdev))) 234 return; 235 236 if (pdev->is_virtfn) { 237 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev); 238 239 /* 240 * VF PEs are single-device PEs so their pdev pointer needs to 241 * be set. The pdev doesn't exist when the PE is allocated (in 242 * (pcibios_sriov_enable()) so we fix it up here. 243 */ 244 pe->pdev = pdev; 245 WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); 246 } else if (pdev->is_physfn) { 247 /* 248 * For PFs adjust their allocated IOV resources to match what 249 * the PHB can support using it's M64 BAR table. 250 */ 251 pnv_pci_ioda_fixup_iov_resources(pdev); 252 } 253 } 254 255 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 256 int resno) 257 { 258 struct pnv_iov_data *iov = pnv_iov_get(pdev); 259 resource_size_t align; 260 261 /* 262 * iov can be null if we have an SR-IOV device with IOV BAR that can't 263 * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch). 264 * In that case we don't allow VFs to be enabled since one of their 265 * BARs would not be placed in the correct PE. 266 */ 267 if (!iov) 268 return align; 269 if (!iov->vfs_expanded) 270 return align; 271 272 align = pci_iov_resource_size(pdev, resno); 273 274 /* 275 * If we're using single mode then we can just use the native VF BAR 276 * alignment. We validated that it's possible to use a single PE 277 * window above when we did the fixup. 278 */ 279 if (iov->m64_single_mode[resno - PCI_IOV_RESOURCES]) 280 return align; 281 282 /* 283 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 284 * SR-IOV. While from hardware perspective, the range mapped by M64 285 * BAR should be size aligned. 286 * 287 * This function returns the total IOV BAR size if M64 BAR is in 288 * Shared PE mode or just VF BAR size if not. 289 * If the M64 BAR is in Single PE mode, return the VF BAR size or 290 * M64 segment size if IOV BAR size is less. 291 */ 292 return iov->vfs_expanded * align; 293 } 294 295 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 296 { 297 struct pnv_iov_data *iov; 298 struct pnv_phb *phb; 299 int window_id; 300 301 phb = pci_bus_to_pnvhb(pdev->bus); 302 iov = pnv_iov_get(pdev); 303 304 for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) { 305 opal_pci_phb_mmio_enable(phb->opal_id, 306 OPAL_M64_WINDOW_TYPE, 307 window_id, 308 0); 309 310 clear_bit(window_id, &phb->ioda.m64_bar_alloc); 311 } 312 313 return 0; 314 } 315 316 317 /* 318 * PHB3 and beyond support segmented windows. The window's address range 319 * is subdivided into phb->ioda.total_pe_num segments and there's a 1-1 320 * mapping between PEs and segments. 321 */ 322 static int64_t pnv_ioda_map_m64_segmented(struct pnv_phb *phb, 323 int window_id, 324 resource_size_t start, 325 resource_size_t size) 326 { 327 int64_t rc; 328 329 rc = opal_pci_set_phb_mem_window(phb->opal_id, 330 OPAL_M64_WINDOW_TYPE, 331 window_id, 332 start, 333 0, /* unused */ 334 size); 335 if (rc) 336 goto out; 337 338 rc = opal_pci_phb_mmio_enable(phb->opal_id, 339 OPAL_M64_WINDOW_TYPE, 340 window_id, 341 OPAL_ENABLE_M64_SPLIT); 342 out: 343 if (rc) 344 pr_err("Failed to map M64 window #%d: %lld\n", window_id, rc); 345 346 return rc; 347 } 348 349 static int64_t pnv_ioda_map_m64_single(struct pnv_phb *phb, 350 int pe_num, 351 int window_id, 352 resource_size_t start, 353 resource_size_t size) 354 { 355 int64_t rc; 356 357 /* 358 * The API for setting up m64 mmio windows seems to have been designed 359 * with P7-IOC in mind. For that chip each M64 BAR (window) had a fixed 360 * split of 8 equally sized segments each of which could individually 361 * assigned to a PE. 362 * 363 * The problem with this is that the API doesn't have any way to 364 * communicate the number of segments we want on a BAR. This wasn't 365 * a problem for p7-ioc since you didn't have a choice, but the 366 * single PE windows added in PHB3 don't map cleanly to this API. 367 * 368 * As a result we've got this slightly awkward process where we 369 * call opal_pci_map_pe_mmio_window() to put the single in single 370 * PE mode, and set the PE for the window before setting the address 371 * bounds. We need to do it this way because the single PE windows 372 * for PHB3 have different alignment requirements on PHB3. 373 */ 374 rc = opal_pci_map_pe_mmio_window(phb->opal_id, 375 pe_num, 376 OPAL_M64_WINDOW_TYPE, 377 window_id, 378 0); 379 if (rc) 380 goto out; 381 382 /* 383 * NB: In single PE mode the window needs to be aligned to 32MB 384 */ 385 rc = opal_pci_set_phb_mem_window(phb->opal_id, 386 OPAL_M64_WINDOW_TYPE, 387 window_id, 388 start, 389 0, /* ignored by FW, m64 is 1-1 */ 390 size); 391 if (rc) 392 goto out; 393 394 /* 395 * Now actually enable it. We specified the BAR should be in "non-split" 396 * mode so FW will validate that the BAR is in single PE mode. 397 */ 398 rc = opal_pci_phb_mmio_enable(phb->opal_id, 399 OPAL_M64_WINDOW_TYPE, 400 window_id, 401 OPAL_ENABLE_M64_NON_SPLIT); 402 out: 403 if (rc) 404 pr_err("Error mapping single PE BAR\n"); 405 406 return rc; 407 } 408 409 static int pnv_pci_alloc_m64_bar(struct pnv_phb *phb, struct pnv_iov_data *iov) 410 { 411 int win; 412 413 do { 414 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 415 phb->ioda.m64_bar_idx + 1, 0); 416 417 if (win >= phb->ioda.m64_bar_idx + 1) 418 return -1; 419 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 420 421 set_bit(win, iov->used_m64_bar_mask); 422 423 return win; 424 } 425 426 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 427 { 428 struct pnv_iov_data *iov; 429 struct pnv_phb *phb; 430 unsigned int win; 431 struct resource *res; 432 int i, j; 433 int64_t rc; 434 resource_size_t size, start; 435 int base_pe_num; 436 437 phb = pci_bus_to_pnvhb(pdev->bus); 438 iov = pnv_iov_get(pdev); 439 440 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 441 res = &pdev->resource[i + PCI_IOV_RESOURCES]; 442 if (!res->flags || !res->parent) 443 continue; 444 445 /* don't need single mode? map everything in one go! */ 446 if (!iov->m64_single_mode[i]) { 447 win = pnv_pci_alloc_m64_bar(phb, iov); 448 if (win < 0) 449 goto m64_failed; 450 451 size = resource_size(res); 452 start = res->start; 453 454 rc = pnv_ioda_map_m64_segmented(phb, win, start, size); 455 if (rc) 456 goto m64_failed; 457 458 continue; 459 } 460 461 /* otherwise map each VF with single PE BARs */ 462 size = pci_iov_resource_size(pdev, PCI_IOV_RESOURCES + i); 463 base_pe_num = iov->vf_pe_arr[0].pe_number; 464 465 for (j = 0; j < num_vfs; j++) { 466 win = pnv_pci_alloc_m64_bar(phb, iov); 467 if (win < 0) 468 goto m64_failed; 469 470 start = res->start + size * j; 471 rc = pnv_ioda_map_m64_single(phb, win, 472 base_pe_num + j, 473 start, 474 size); 475 if (rc) 476 goto m64_failed; 477 } 478 } 479 return 0; 480 481 m64_failed: 482 pnv_pci_vf_release_m64(pdev, num_vfs); 483 return -EBUSY; 484 } 485 486 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 487 { 488 struct pnv_phb *phb; 489 struct pnv_ioda_pe *pe, *pe_n; 490 491 phb = pci_bus_to_pnvhb(pdev->bus); 492 493 if (!pdev->is_physfn) 494 return; 495 496 /* FIXME: Use pnv_ioda_release_pe()? */ 497 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 498 if (pe->parent_dev != pdev) 499 continue; 500 501 pnv_pci_ioda2_release_pe_dma(pe); 502 503 /* Remove from list */ 504 mutex_lock(&phb->ioda.pe_list_mutex); 505 list_del(&pe->list); 506 mutex_unlock(&phb->ioda.pe_list_mutex); 507 508 pnv_ioda_deconfigure_pe(phb, pe); 509 510 pnv_ioda_free_pe(pe); 511 } 512 } 513 514 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 515 { 516 struct resource *res, res2; 517 struct pnv_iov_data *iov; 518 resource_size_t size; 519 u16 num_vfs; 520 int i; 521 522 if (!dev->is_physfn) 523 return -EINVAL; 524 iov = pnv_iov_get(dev); 525 526 /* 527 * "offset" is in VFs. The M64 windows are sized so that when they 528 * are segmented, each segment is the same size as the IOV BAR. 529 * Each segment is in a separate PE, and the high order bits of the 530 * address are the PE number. Therefore, each VF's BAR is in a 531 * separate PE, and changing the IOV BAR start address changes the 532 * range of PEs the VFs are in. 533 */ 534 num_vfs = iov->num_vfs; 535 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 536 res = &dev->resource[i + PCI_IOV_RESOURCES]; 537 if (!res->flags || !res->parent) 538 continue; 539 if (iov->m64_single_mode[i]) 540 continue; 541 542 /* 543 * The actual IOV BAR range is determined by the start address 544 * and the actual size for num_vfs VFs BAR. This check is to 545 * make sure that after shifting, the range will not overlap 546 * with another device. 547 */ 548 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 549 res2.flags = res->flags; 550 res2.start = res->start + (size * offset); 551 res2.end = res2.start + (size * num_vfs) - 1; 552 553 if (res2.end > res->end) { 554 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 555 i, &res2, res, num_vfs, offset); 556 return -EBUSY; 557 } 558 } 559 560 /* 561 * Since M64 BAR shares segments among all possible 256 PEs, 562 * we have to shift the beginning of PF IOV BAR to make it start from 563 * the segment which belongs to the PE number assigned to the first VF. 564 * This creates a "hole" in the /proc/iomem which could be used for 565 * allocating other resources so we reserve this area below and 566 * release when IOV is released. 567 */ 568 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 569 res = &dev->resource[i + PCI_IOV_RESOURCES]; 570 if (!res->flags || !res->parent) 571 continue; 572 if (iov->m64_single_mode[i]) 573 continue; 574 575 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 576 res2 = *res; 577 res->start += size * offset; 578 579 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 580 i, &res2, res, (offset > 0) ? "En" : "Dis", 581 num_vfs, offset); 582 583 if (offset < 0) { 584 devm_release_resource(&dev->dev, &iov->holes[i]); 585 memset(&iov->holes[i], 0, sizeof(iov->holes[i])); 586 } 587 588 pci_update_resource(dev, i + PCI_IOV_RESOURCES); 589 590 if (offset > 0) { 591 iov->holes[i].start = res2.start; 592 iov->holes[i].end = res2.start + size * offset - 1; 593 iov->holes[i].flags = IORESOURCE_BUS; 594 iov->holes[i].name = "pnv_iov_reserved"; 595 devm_request_resource(&dev->dev, res->parent, 596 &iov->holes[i]); 597 } 598 } 599 return 0; 600 } 601 602 static void pnv_pci_sriov_disable(struct pci_dev *pdev) 603 { 604 u16 num_vfs, base_pe; 605 struct pnv_phb *phb; 606 struct pnv_iov_data *iov; 607 608 phb = pci_bus_to_pnvhb(pdev->bus); 609 iov = pnv_iov_get(pdev); 610 num_vfs = iov->num_vfs; 611 base_pe = iov->vf_pe_arr[0].pe_number; 612 613 if (WARN_ON(!iov)) 614 return; 615 616 /* Release VF PEs */ 617 pnv_ioda_release_vf_PE(pdev); 618 619 /* Un-shift the IOV BARs if we need to */ 620 if (iov->need_shift) 621 pnv_pci_vf_resource_shift(pdev, -base_pe); 622 623 /* Release M64 windows */ 624 pnv_pci_vf_release_m64(pdev, num_vfs); 625 } 626 627 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 628 { 629 struct pnv_phb *phb; 630 struct pnv_ioda_pe *pe; 631 int pe_num; 632 u16 vf_index; 633 struct pnv_iov_data *iov; 634 struct pci_dn *pdn; 635 636 if (!pdev->is_physfn) 637 return; 638 639 phb = pci_bus_to_pnvhb(pdev->bus); 640 pdn = pci_get_pdn(pdev); 641 iov = pnv_iov_get(pdev); 642 643 /* Reserve PE for each VF */ 644 for (vf_index = 0; vf_index < num_vfs; vf_index++) { 645 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 646 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 647 struct pci_dn *vf_pdn; 648 649 pe = &iov->vf_pe_arr[vf_index]; 650 pe->phb = phb; 651 pe->flags = PNV_IODA_PE_VF; 652 pe->pbus = NULL; 653 pe->parent_dev = pdev; 654 pe->mve_number = -1; 655 pe->rid = (vf_bus << 8) | vf_devfn; 656 657 pe_num = pe->pe_number; 658 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 659 pci_domain_nr(pdev->bus), pdev->bus->number, 660 PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 661 662 if (pnv_ioda_configure_pe(phb, pe)) { 663 /* XXX What do we do here ? */ 664 pnv_ioda_free_pe(pe); 665 pe->pdev = NULL; 666 continue; 667 } 668 669 /* Put PE to the list */ 670 mutex_lock(&phb->ioda.pe_list_mutex); 671 list_add_tail(&pe->list, &phb->ioda.pe_list); 672 mutex_unlock(&phb->ioda.pe_list_mutex); 673 674 /* associate this pe to it's pdn */ 675 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 676 if (vf_pdn->busno == vf_bus && 677 vf_pdn->devfn == vf_devfn) { 678 vf_pdn->pe_number = pe_num; 679 break; 680 } 681 } 682 683 pnv_pci_ioda2_setup_dma_pe(phb, pe); 684 } 685 } 686 687 static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 688 { 689 struct pnv_ioda_pe *base_pe; 690 struct pnv_iov_data *iov; 691 struct pnv_phb *phb; 692 int ret; 693 u16 i; 694 695 phb = pci_bus_to_pnvhb(pdev->bus); 696 iov = pnv_iov_get(pdev); 697 698 /* 699 * There's a calls to IODA2 PE setup code littered throughout. We could 700 * probably fix that, but we'd still have problems due to the 701 * restriction inherent on IODA1 PHBs. 702 * 703 * NB: We class IODA3 as IODA2 since they're very similar. 704 */ 705 if (phb->type != PNV_PHB_IODA2) { 706 pci_err(pdev, "SR-IOV is not supported on this PHB\n"); 707 return -ENXIO; 708 } 709 710 if (!iov->vfs_expanded) { 711 dev_info(&pdev->dev, "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n"); 712 return -ENOSPC; 713 } 714 715 /* allocate a contigious block of PEs for our VFs */ 716 base_pe = pnv_ioda_alloc_pe(phb, num_vfs); 717 if (!base_pe) { 718 pci_err(pdev, "Unable to allocate PEs for %d VFs\n", num_vfs); 719 return -EBUSY; 720 } 721 722 iov->vf_pe_arr = base_pe; 723 iov->num_vfs = num_vfs; 724 725 /* Assign M64 window accordingly */ 726 ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 727 if (ret) { 728 dev_info(&pdev->dev, "Not enough M64 window resources\n"); 729 goto m64_failed; 730 } 731 732 /* 733 * When using one M64 BAR to map one IOV BAR, we need to shift 734 * the IOV BAR according to the PE# allocated to the VFs. 735 * Otherwise, the PE# for the VF will conflict with others. 736 */ 737 if (iov->need_shift) { 738 ret = pnv_pci_vf_resource_shift(pdev, base_pe->pe_number); 739 if (ret) 740 goto shift_failed; 741 } 742 743 /* Setup VF PEs */ 744 pnv_ioda_setup_vf_PE(pdev, num_vfs); 745 746 return 0; 747 748 shift_failed: 749 pnv_pci_vf_release_m64(pdev, num_vfs); 750 751 m64_failed: 752 for (i = 0; i < num_vfs; i++) 753 pnv_ioda_free_pe(&iov->vf_pe_arr[i]); 754 755 return ret; 756 } 757 758 int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 759 { 760 pnv_pci_sriov_disable(pdev); 761 762 /* Release PCI data */ 763 remove_sriov_vf_pdns(pdev); 764 return 0; 765 } 766 767 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 768 { 769 /* Allocate PCI data */ 770 add_sriov_vf_pdns(pdev); 771 772 return pnv_pci_sriov_enable(pdev, num_vfs); 773 } 774