1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 #include <linux/kernel.h>
4 #include <linux/ioport.h>
5 #include <linux/bitmap.h>
6 #include <linux/pci.h>
7 
8 #include <asm/opal.h>
9 
10 #include "pci.h"
11 
12 /* for pci_dev_is_added() */
13 #include "../../../../drivers/pci/pci.h"
14 
15 /*
16  * The majority of the complexity in supporting SR-IOV on PowerNV comes from
17  * the need to put the MMIO space for each VF into a separate PE. Internally
18  * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table".
19  * The MBT historically only applied to the 64bit MMIO window of the PHB
20  * so it's common to see it referred to as the "M64BT".
21  *
22  * An MBT entry stores the mapped range as an <base>,<mask> pair. This forces
23  * the address range that we want to map to be power-of-two sized and aligned.
24  * For conventional PCI devices this isn't really an issue since PCI device BARs
25  * have the same requirement.
26  *
27  * For a SR-IOV BAR things are a little more awkward since size and alignment
28  * are not coupled. The alignment is set based on the the per-VF BAR size, but
29  * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs
30  * isn't necessarily a power of two, so neither is the total size. To fix that
31  * we need to finesse (read: hack) the Linux BAR allocator so that it will
32  * allocate the SR-IOV BARs in a way that lets us map them using the MBT.
33  *
34  * The changes to size and alignment that we need to do depend on the "mode"
35  * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above,
36  * so as a baseline we can assume that we have the following BAR modes
37  * available:
38  *
39  *   NB: $PE_COUNT is the number of PEs that the PHB supports.
40  *
41  * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized
42  *    segments. The n'th segment is mapped to the n'th PE.
43  * b) An un-segmented BAR that maps the whole address range to a specific PE.
44  *
45  *
46  * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR
47  * For comparison b) requires one entry per-VF per-BAR, or:
48  * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment
49  * to equal the size of the per-VF BAR area. So:
50  *
51  *	new_size = per-vf-size * number-of-PEs
52  *
53  * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size
54  * to "new_size", calculated above. Implementing this is a convoluted process
55  * which requires several hooks in the PCI core:
56  *
57  * 1. In pcibios_add_device() we call pnv_pci_ioda_fixup_iov().
58  *
59  *    At this point the device has been probed and the device's BARs are sized,
60  *    but no resource allocations have been done. The SR-IOV BARs are sized
61  *    based on the maximum number of VFs supported by the device and we need
62  *    to increase that to new_size.
63  *
64  * 2. Later, when Linux actually assigns resources it tries to make the resource
65  *    allocations for each PCI bus as compact as possible. As a part of that it
66  *    sorts the BARs on a bus by their required alignment, which is calculated
67  *    using pci_resource_alignment().
68  *
69  *    For IOV resources this goes:
70  *    pci_resource_alignment()
71  *        pci_sriov_resource_alignment()
72  *            pcibios_sriov_resource_alignment()
73  *                pnv_pci_iov_resource_alignment()
74  *
75  *    Our hook overrides the default alignment, equal to the per-vf-size, with
76  *    new_size computed above.
77  *
78  * 3. When userspace enables VFs for a device:
79  *
80  *    sriov_enable()
81  *       pcibios_sriov_enable()
82  *           pnv_pcibios_sriov_enable()
83  *
84  *    This is where we actually allocate PE numbers for each VF and setup the
85  *    MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena"
86  *    where each MBT segment is equal in size to the VF BAR so we can shift
87  *    around the actual SR-IOV BAR location within this arena. We need this
88  *    ability because the PE space is shared by all devices on the same PHB.
89  *    When using mode a) described above segment 0 in maps to PE#0 which might
90  *    be already being used by another device on the PHB.
91  *
92  *    As a result we need allocate a contigious range of PE numbers, then shift
93  *    the address programmed into the SR-IOV BAR of the PF so that the address
94  *    of VF0 matches up with the segment corresponding to the first allocated
95  *    PE number. This is handled in pnv_pci_vf_resource_shift().
96  *
97  *    Once all that is done we return to the PCI core which then enables VFs,
98  *    scans them and creates pci_devs for each. The init process for a VF is
99  *    largely the same as a normal device, but the VF is inserted into the IODA
100  *    PE that we allocated for it rather than the PE associated with the bus.
101  *
102  * 4. When userspace disables VFs we unwind the above in
103  *    pnv_pcibios_sriov_disable(). Fortunately this is relatively simple since
104  *    we don't need to validate anything, just tear down the mappings and
105  *    move SR-IOV resource back to its "proper" location.
106  *
107  * That's how mode a) works. In theory mode b) (single PE mapping) is less work
108  * since we can map each individual VF with a separate BAR. However, there's a
109  * few limitations:
110  *
111  * 1) For IODA2 mode b) has a minimum alignment requirement of 32MB. This makes
112  *    it only usable for devices with very large per-VF BARs. Such devices are
113  *    similar to Big Foot. They definitely exist, but I've never seen one.
114  *
115  * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only
116  *    16 total and some are needed for. Most SR-IOV capable network cards can support
117  *    more than 16 VFs on each port.
118  *
119  * We use b) when using a) would use more than 1/4 of the entire 64 bit MMIO
120  * window of the PHB.
121  *
122  *
123  *
124  * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It
125  * allowed the MBT to map 32bit MMIO space in addition to 64bit which allows
126  * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since
127  * the Linux BAR allocation will place any BAR marked as non-prefetchable into
128  * the non-prefetchable bridge window, which is 32bit only. It also added two
129  * new modes:
130  *
131  * c) A segmented BAR similar to a), but each segment can be individually
132  *    mapped to any PE. This is matches how the 32bit MMIO window worked on
133  *    IODA1&2.
134  *
135  * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a),
136  *    but with fewer segments and configurable base PE.
137  *
138  *    i.e. The n'th segment maps to the (n + base)'th PE.
139  *
140  *    The base PE is also required to be a multiple of the window size.
141  *
142  * Unfortunately, the OPAL API doesn't currently (as of skiboot v6.6) allow us
143  * to exploit any of the IODA3 features.
144  */
145 
146 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
147 {
148 	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
149 	struct resource *res;
150 	int i;
151 	resource_size_t vf_bar_sz;
152 	struct pnv_iov_data *iov;
153 	int mul;
154 
155 	iov = kzalloc(sizeof(*iov), GFP_KERNEL);
156 	if (!iov)
157 		goto disable_iov;
158 	pdev->dev.archdata.iov_data = iov;
159 	mul = phb->ioda.total_pe_num;
160 
161 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
162 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
163 		if (!res->flags || res->parent)
164 			continue;
165 		if (!pnv_pci_is_m64_flags(res->flags)) {
166 			dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n",
167 				 i, res);
168 			goto disable_iov;
169 		}
170 
171 		vf_bar_sz = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
172 
173 		/*
174 		 * Generally, one segmented M64 BAR maps one IOV BAR. However,
175 		 * if a VF BAR is too large we end up wasting a lot of space.
176 		 * If each VF needs more than 1/4 of the default m64 segment
177 		 * then each VF BAR should be mapped in single-PE mode to reduce
178 		 * the amount of space required. This does however limit the
179 		 * number of VFs we can support.
180 		 *
181 		 * The 1/4 limit is arbitrary and can be tweaked.
182 		 */
183 		if (vf_bar_sz > (phb->ioda.m64_segsize >> 2)) {
184 			/*
185 			 * On PHB3, the minimum size alignment of M64 BAR in
186 			 * single mode is 32MB. If this VF BAR is smaller than
187 			 * 32MB, but still too large for a segmented window
188 			 * then we can't map it and need to disable SR-IOV for
189 			 * this device.
190 			 */
191 			if (vf_bar_sz < SZ_32M) {
192 				pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n",
193 					i, res);
194 				goto disable_iov;
195 			}
196 
197 			iov->m64_single_mode[i] = true;
198 			continue;
199 		}
200 
201 		/*
202 		 * This BAR can be mapped with one segmented window, so adjust
203 		 * te resource size to accommodate.
204 		 */
205 		pci_dbg(pdev, " Fixing VF BAR%d: %pR to\n", i, res);
206 		res->end = res->start + vf_bar_sz * mul - 1;
207 		pci_dbg(pdev, "                       %pR\n", res);
208 
209 		pci_info(pdev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
210 			 i, res, mul);
211 
212 		iov->need_shift = true;
213 	}
214 
215 	return;
216 
217 disable_iov:
218 	/* Save ourselves some MMIO space by disabling the unusable BARs */
219 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
220 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
221 		res->flags = 0;
222 		res->end = res->start - 1;
223 	}
224 
225 	pdev->dev.archdata.iov_data = NULL;
226 	kfree(iov);
227 }
228 
229 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
230 {
231 	if (WARN_ON(pci_dev_is_added(pdev)))
232 		return;
233 
234 	if (pdev->is_virtfn) {
235 		struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
236 
237 		/*
238 		 * VF PEs are single-device PEs so their pdev pointer needs to
239 		 * be set. The pdev doesn't exist when the PE is allocated (in
240 		 * (pcibios_sriov_enable()) so we fix it up here.
241 		 */
242 		pe->pdev = pdev;
243 		WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
244 	} else if (pdev->is_physfn) {
245 		/*
246 		 * For PFs adjust their allocated IOV resources to match what
247 		 * the PHB can support using it's M64 BAR table.
248 		 */
249 		pnv_pci_ioda_fixup_iov_resources(pdev);
250 	}
251 }
252 
253 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
254 						      int resno)
255 {
256 	resource_size_t align = pci_iov_resource_size(pdev, resno);
257 	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
258 	struct pnv_iov_data *iov = pnv_iov_get(pdev);
259 
260 	/*
261 	 * iov can be null if we have an SR-IOV device with IOV BAR that can't
262 	 * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch).
263 	 * In that case we don't allow VFs to be enabled since one of their
264 	 * BARs would not be placed in the correct PE.
265 	 */
266 	if (!iov)
267 		return align;
268 
269 	/*
270 	 * If we're using single mode then we can just use the native VF BAR
271 	 * alignment. We validated that it's possible to use a single PE
272 	 * window above when we did the fixup.
273 	 */
274 	if (iov->m64_single_mode[resno - PCI_IOV_RESOURCES])
275 		return align;
276 
277 	/*
278 	 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
279 	 * SR-IOV. While from hardware perspective, the range mapped by M64
280 	 * BAR should be size aligned.
281 	 *
282 	 * This function returns the total IOV BAR size if M64 BAR is in
283 	 * Shared PE mode or just VF BAR size if not.
284 	 * If the M64 BAR is in Single PE mode, return the VF BAR size or
285 	 * M64 segment size if IOV BAR size is less.
286 	 */
287 	return phb->ioda.total_pe_num * align;
288 }
289 
290 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
291 {
292 	struct pnv_iov_data   *iov;
293 	struct pnv_phb        *phb;
294 	int window_id;
295 
296 	phb = pci_bus_to_pnvhb(pdev->bus);
297 	iov = pnv_iov_get(pdev);
298 
299 	for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) {
300 		opal_pci_phb_mmio_enable(phb->opal_id,
301 					 OPAL_M64_WINDOW_TYPE,
302 					 window_id,
303 					 0);
304 
305 		clear_bit(window_id, &phb->ioda.m64_bar_alloc);
306 	}
307 
308 	return 0;
309 }
310 
311 
312 /*
313  * PHB3 and beyond support segmented windows. The window's address range
314  * is subdivided into phb->ioda.total_pe_num segments and there's a 1-1
315  * mapping between PEs and segments.
316  */
317 static int64_t pnv_ioda_map_m64_segmented(struct pnv_phb *phb,
318 					  int window_id,
319 					  resource_size_t start,
320 					  resource_size_t size)
321 {
322 	int64_t rc;
323 
324 	rc = opal_pci_set_phb_mem_window(phb->opal_id,
325 					 OPAL_M64_WINDOW_TYPE,
326 					 window_id,
327 					 start,
328 					 0, /* unused */
329 					 size);
330 	if (rc)
331 		goto out;
332 
333 	rc = opal_pci_phb_mmio_enable(phb->opal_id,
334 				      OPAL_M64_WINDOW_TYPE,
335 				      window_id,
336 				      OPAL_ENABLE_M64_SPLIT);
337 out:
338 	if (rc)
339 		pr_err("Failed to map M64 window #%d: %lld\n", window_id, rc);
340 
341 	return rc;
342 }
343 
344 static int64_t pnv_ioda_map_m64_single(struct pnv_phb *phb,
345 				       int pe_num,
346 				       int window_id,
347 				       resource_size_t start,
348 				       resource_size_t size)
349 {
350 	int64_t rc;
351 
352 	/*
353 	 * The API for setting up m64 mmio windows seems to have been designed
354 	 * with P7-IOC in mind. For that chip each M64 BAR (window) had a fixed
355 	 * split of 8 equally sized segments each of which could individually
356 	 * assigned to a PE.
357 	 *
358 	 * The problem with this is that the API doesn't have any way to
359 	 * communicate the number of segments we want on a BAR. This wasn't
360 	 * a problem for p7-ioc since you didn't have a choice, but the
361 	 * single PE windows added in PHB3 don't map cleanly to this API.
362 	 *
363 	 * As a result we've got this slightly awkward process where we
364 	 * call opal_pci_map_pe_mmio_window() to put the single in single
365 	 * PE mode, and set the PE for the window before setting the address
366 	 * bounds. We need to do it this way because the single PE windows
367 	 * for PHB3 have different alignment requirements on PHB3.
368 	 */
369 	rc = opal_pci_map_pe_mmio_window(phb->opal_id,
370 					 pe_num,
371 					 OPAL_M64_WINDOW_TYPE,
372 					 window_id,
373 					 0);
374 	if (rc)
375 		goto out;
376 
377 	/*
378 	 * NB: In single PE mode the window needs to be aligned to 32MB
379 	 */
380 	rc = opal_pci_set_phb_mem_window(phb->opal_id,
381 					 OPAL_M64_WINDOW_TYPE,
382 					 window_id,
383 					 start,
384 					 0, /* ignored by FW, m64 is 1-1 */
385 					 size);
386 	if (rc)
387 		goto out;
388 
389 	/*
390 	 * Now actually enable it. We specified the BAR should be in "non-split"
391 	 * mode so FW will validate that the BAR is in single PE mode.
392 	 */
393 	rc = opal_pci_phb_mmio_enable(phb->opal_id,
394 				      OPAL_M64_WINDOW_TYPE,
395 				      window_id,
396 				      OPAL_ENABLE_M64_NON_SPLIT);
397 out:
398 	if (rc)
399 		pr_err("Error mapping single PE BAR\n");
400 
401 	return rc;
402 }
403 
404 static int pnv_pci_alloc_m64_bar(struct pnv_phb *phb, struct pnv_iov_data *iov)
405 {
406 	int win;
407 
408 	do {
409 		win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
410 				phb->ioda.m64_bar_idx + 1, 0);
411 
412 		if (win >= phb->ioda.m64_bar_idx + 1)
413 			return -1;
414 	} while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
415 
416 	set_bit(win, iov->used_m64_bar_mask);
417 
418 	return win;
419 }
420 
421 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
422 {
423 	struct pnv_iov_data   *iov;
424 	struct pnv_phb        *phb;
425 	unsigned int           win;
426 	struct resource       *res;
427 	int                    i, j;
428 	int64_t                rc;
429 	resource_size_t        size, start;
430 	int                    base_pe_num;
431 
432 	phb = pci_bus_to_pnvhb(pdev->bus);
433 	iov = pnv_iov_get(pdev);
434 
435 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
436 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
437 		if (!res->flags || !res->parent)
438 			continue;
439 
440 		/* don't need single mode? map everything in one go! */
441 		if (!iov->m64_single_mode[i]) {
442 			win = pnv_pci_alloc_m64_bar(phb, iov);
443 			if (win < 0)
444 				goto m64_failed;
445 
446 			size = resource_size(res);
447 			start = res->start;
448 
449 			rc = pnv_ioda_map_m64_segmented(phb, win, start, size);
450 			if (rc)
451 				goto m64_failed;
452 
453 			continue;
454 		}
455 
456 		/* otherwise map each VF with single PE BARs */
457 		size = pci_iov_resource_size(pdev, PCI_IOV_RESOURCES + i);
458 		base_pe_num = iov->vf_pe_arr[0].pe_number;
459 
460 		for (j = 0; j < num_vfs; j++) {
461 			win = pnv_pci_alloc_m64_bar(phb, iov);
462 			if (win < 0)
463 				goto m64_failed;
464 
465 			start = res->start + size * j;
466 			rc = pnv_ioda_map_m64_single(phb, win,
467 						     base_pe_num + j,
468 						     start,
469 						     size);
470 			if (rc)
471 				goto m64_failed;
472 		}
473 	}
474 	return 0;
475 
476 m64_failed:
477 	pnv_pci_vf_release_m64(pdev, num_vfs);
478 	return -EBUSY;
479 }
480 
481 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
482 {
483 	struct pnv_phb        *phb;
484 	struct pnv_ioda_pe    *pe, *pe_n;
485 
486 	phb = pci_bus_to_pnvhb(pdev->bus);
487 
488 	if (!pdev->is_physfn)
489 		return;
490 
491 	/* FIXME: Use pnv_ioda_release_pe()? */
492 	list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
493 		if (pe->parent_dev != pdev)
494 			continue;
495 
496 		pnv_pci_ioda2_release_pe_dma(pe);
497 
498 		/* Remove from list */
499 		mutex_lock(&phb->ioda.pe_list_mutex);
500 		list_del(&pe->list);
501 		mutex_unlock(&phb->ioda.pe_list_mutex);
502 
503 		pnv_ioda_deconfigure_pe(phb, pe);
504 
505 		pnv_ioda_free_pe(pe);
506 	}
507 }
508 
509 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
510 {
511 	struct resource *res, res2;
512 	struct pnv_iov_data *iov;
513 	resource_size_t size;
514 	u16 num_vfs;
515 	int i;
516 
517 	if (!dev->is_physfn)
518 		return -EINVAL;
519 	iov = pnv_iov_get(dev);
520 
521 	/*
522 	 * "offset" is in VFs.  The M64 windows are sized so that when they
523 	 * are segmented, each segment is the same size as the IOV BAR.
524 	 * Each segment is in a separate PE, and the high order bits of the
525 	 * address are the PE number.  Therefore, each VF's BAR is in a
526 	 * separate PE, and changing the IOV BAR start address changes the
527 	 * range of PEs the VFs are in.
528 	 */
529 	num_vfs = iov->num_vfs;
530 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
531 		res = &dev->resource[i + PCI_IOV_RESOURCES];
532 		if (!res->flags || !res->parent)
533 			continue;
534 		if (iov->m64_single_mode[i])
535 			continue;
536 
537 		/*
538 		 * The actual IOV BAR range is determined by the start address
539 		 * and the actual size for num_vfs VFs BAR.  This check is to
540 		 * make sure that after shifting, the range will not overlap
541 		 * with another device.
542 		 */
543 		size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
544 		res2.flags = res->flags;
545 		res2.start = res->start + (size * offset);
546 		res2.end = res2.start + (size * num_vfs) - 1;
547 
548 		if (res2.end > res->end) {
549 			dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
550 				i, &res2, res, num_vfs, offset);
551 			return -EBUSY;
552 		}
553 	}
554 
555 	/*
556 	 * Since M64 BAR shares segments among all possible 256 PEs,
557 	 * we have to shift the beginning of PF IOV BAR to make it start from
558 	 * the segment which belongs to the PE number assigned to the first VF.
559 	 * This creates a "hole" in the /proc/iomem which could be used for
560 	 * allocating other resources so we reserve this area below and
561 	 * release when IOV is released.
562 	 */
563 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
564 		res = &dev->resource[i + PCI_IOV_RESOURCES];
565 		if (!res->flags || !res->parent)
566 			continue;
567 		if (iov->m64_single_mode[i])
568 			continue;
569 
570 		size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
571 		res2 = *res;
572 		res->start += size * offset;
573 
574 		dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
575 			 i, &res2, res, (offset > 0) ? "En" : "Dis",
576 			 num_vfs, offset);
577 
578 		if (offset < 0) {
579 			devm_release_resource(&dev->dev, &iov->holes[i]);
580 			memset(&iov->holes[i], 0, sizeof(iov->holes[i]));
581 		}
582 
583 		pci_update_resource(dev, i + PCI_IOV_RESOURCES);
584 
585 		if (offset > 0) {
586 			iov->holes[i].start = res2.start;
587 			iov->holes[i].end = res2.start + size * offset - 1;
588 			iov->holes[i].flags = IORESOURCE_BUS;
589 			iov->holes[i].name = "pnv_iov_reserved";
590 			devm_request_resource(&dev->dev, res->parent,
591 					&iov->holes[i]);
592 		}
593 	}
594 	return 0;
595 }
596 
597 static void pnv_pci_sriov_disable(struct pci_dev *pdev)
598 {
599 	u16                    num_vfs, base_pe;
600 	struct pnv_iov_data   *iov;
601 
602 	iov = pnv_iov_get(pdev);
603 	num_vfs = iov->num_vfs;
604 	base_pe = iov->vf_pe_arr[0].pe_number;
605 
606 	if (WARN_ON(!iov))
607 		return;
608 
609 	/* Release VF PEs */
610 	pnv_ioda_release_vf_PE(pdev);
611 
612 	/* Un-shift the IOV BARs if we need to */
613 	if (iov->need_shift)
614 		pnv_pci_vf_resource_shift(pdev, -base_pe);
615 
616 	/* Release M64 windows */
617 	pnv_pci_vf_release_m64(pdev, num_vfs);
618 }
619 
620 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
621 {
622 	struct pnv_phb        *phb;
623 	struct pnv_ioda_pe    *pe;
624 	int                    pe_num;
625 	u16                    vf_index;
626 	struct pnv_iov_data   *iov;
627 	struct pci_dn         *pdn;
628 
629 	if (!pdev->is_physfn)
630 		return;
631 
632 	phb = pci_bus_to_pnvhb(pdev->bus);
633 	pdn = pci_get_pdn(pdev);
634 	iov = pnv_iov_get(pdev);
635 
636 	/* Reserve PE for each VF */
637 	for (vf_index = 0; vf_index < num_vfs; vf_index++) {
638 		int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
639 		int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
640 		struct pci_dn *vf_pdn;
641 
642 		pe = &iov->vf_pe_arr[vf_index];
643 		pe->phb = phb;
644 		pe->flags = PNV_IODA_PE_VF;
645 		pe->pbus = NULL;
646 		pe->parent_dev = pdev;
647 		pe->mve_number = -1;
648 		pe->rid = (vf_bus << 8) | vf_devfn;
649 
650 		pe_num = pe->pe_number;
651 		pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
652 			pci_domain_nr(pdev->bus), pdev->bus->number,
653 			PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
654 
655 		if (pnv_ioda_configure_pe(phb, pe)) {
656 			/* XXX What do we do here ? */
657 			pnv_ioda_free_pe(pe);
658 			pe->pdev = NULL;
659 			continue;
660 		}
661 
662 		/* Put PE to the list */
663 		mutex_lock(&phb->ioda.pe_list_mutex);
664 		list_add_tail(&pe->list, &phb->ioda.pe_list);
665 		mutex_unlock(&phb->ioda.pe_list_mutex);
666 
667 		/* associate this pe to it's pdn */
668 		list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
669 			if (vf_pdn->busno == vf_bus &&
670 			    vf_pdn->devfn == vf_devfn) {
671 				vf_pdn->pe_number = pe_num;
672 				break;
673 			}
674 		}
675 
676 		pnv_pci_ioda2_setup_dma_pe(phb, pe);
677 	}
678 }
679 
680 static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
681 {
682 	struct pnv_ioda_pe    *base_pe;
683 	struct pnv_iov_data   *iov;
684 	struct pnv_phb        *phb;
685 	int                    ret;
686 	u16                    i;
687 
688 	phb = pci_bus_to_pnvhb(pdev->bus);
689 	iov = pnv_iov_get(pdev);
690 
691 	/*
692 	 * There's a calls to IODA2 PE setup code littered throughout. We could
693 	 * probably fix that, but we'd still have problems due to the
694 	 * restriction inherent on IODA1 PHBs.
695 	 *
696 	 * NB: We class IODA3 as IODA2 since they're very similar.
697 	 */
698 	if (phb->type != PNV_PHB_IODA2) {
699 		pci_err(pdev, "SR-IOV is not supported on this PHB\n");
700 		return -ENXIO;
701 	}
702 
703 	if (!iov) {
704 		dev_info(&pdev->dev, "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n");
705 		return -ENOSPC;
706 	}
707 
708 	/* allocate a contigious block of PEs for our VFs */
709 	base_pe = pnv_ioda_alloc_pe(phb, num_vfs);
710 	if (!base_pe) {
711 		pci_err(pdev, "Unable to allocate PEs for %d VFs\n", num_vfs);
712 		return -EBUSY;
713 	}
714 
715 	iov->vf_pe_arr = base_pe;
716 	iov->num_vfs = num_vfs;
717 
718 	/* Assign M64 window accordingly */
719 	ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
720 	if (ret) {
721 		dev_info(&pdev->dev, "Not enough M64 window resources\n");
722 		goto m64_failed;
723 	}
724 
725 	/*
726 	 * When using one M64 BAR to map one IOV BAR, we need to shift
727 	 * the IOV BAR according to the PE# allocated to the VFs.
728 	 * Otherwise, the PE# for the VF will conflict with others.
729 	 */
730 	if (iov->need_shift) {
731 		ret = pnv_pci_vf_resource_shift(pdev, base_pe->pe_number);
732 		if (ret)
733 			goto shift_failed;
734 	}
735 
736 	/* Setup VF PEs */
737 	pnv_ioda_setup_vf_PE(pdev, num_vfs);
738 
739 	return 0;
740 
741 shift_failed:
742 	pnv_pci_vf_release_m64(pdev, num_vfs);
743 
744 m64_failed:
745 	for (i = 0; i < num_vfs; i++)
746 		pnv_ioda_free_pe(&iov->vf_pe_arr[i]);
747 
748 	return ret;
749 }
750 
751 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
752 {
753 	pnv_pci_sriov_disable(pdev);
754 
755 	/* Release PCI data */
756 	remove_sriov_vf_pdns(pdev);
757 	return 0;
758 }
759 
760 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
761 {
762 	/* Allocate PCI data */
763 	add_sriov_vf_pdns(pdev);
764 
765 	return pnv_pci_sriov_enable(pdev, num_vfs);
766 }
767