137b59ef0SOliver O'Halloran // SPDX-License-Identifier: GPL-2.0 237b59ef0SOliver O'Halloran 337b59ef0SOliver O'Halloran #include <linux/kernel.h> 437b59ef0SOliver O'Halloran #include <linux/ioport.h> 537b59ef0SOliver O'Halloran #include <linux/bitmap.h> 637b59ef0SOliver O'Halloran #include <linux/pci.h> 737b59ef0SOliver O'Halloran 837b59ef0SOliver O'Halloran #include <asm/opal.h> 937b59ef0SOliver O'Halloran 1037b59ef0SOliver O'Halloran #include "pci.h" 1137b59ef0SOliver O'Halloran 1237b59ef0SOliver O'Halloran /* for pci_dev_is_added() */ 1337b59ef0SOliver O'Halloran #include "../../../../drivers/pci/pci.h" 1437b59ef0SOliver O'Halloran 15ff79e11aSOliver O'Halloran /* 16ff79e11aSOliver O'Halloran * The majority of the complexity in supporting SR-IOV on PowerNV comes from 17ff79e11aSOliver O'Halloran * the need to put the MMIO space for each VF into a separate PE. Internally 18ff79e11aSOliver O'Halloran * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table". 19ff79e11aSOliver O'Halloran * The MBT historically only applied to the 64bit MMIO window of the PHB 20ff79e11aSOliver O'Halloran * so it's common to see it referred to as the "M64BT". 21ff79e11aSOliver O'Halloran * 22ff79e11aSOliver O'Halloran * An MBT entry stores the mapped range as an <base>,<mask> pair. This forces 23ff79e11aSOliver O'Halloran * the address range that we want to map to be power-of-two sized and aligned. 24ff79e11aSOliver O'Halloran * For conventional PCI devices this isn't really an issue since PCI device BARs 25ff79e11aSOliver O'Halloran * have the same requirement. 26ff79e11aSOliver O'Halloran * 27ff79e11aSOliver O'Halloran * For a SR-IOV BAR things are a little more awkward since size and alignment 28ff79e11aSOliver O'Halloran * are not coupled. The alignment is set based on the the per-VF BAR size, but 29ff79e11aSOliver O'Halloran * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs 30ff79e11aSOliver O'Halloran * isn't necessarily a power of two, so neither is the total size. To fix that 31ff79e11aSOliver O'Halloran * we need to finesse (read: hack) the Linux BAR allocator so that it will 32ff79e11aSOliver O'Halloran * allocate the SR-IOV BARs in a way that lets us map them using the MBT. 33ff79e11aSOliver O'Halloran * 34ff79e11aSOliver O'Halloran * The changes to size and alignment that we need to do depend on the "mode" 35ff79e11aSOliver O'Halloran * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above, 36ff79e11aSOliver O'Halloran * so as a baseline we can assume that we have the following BAR modes 37ff79e11aSOliver O'Halloran * available: 38ff79e11aSOliver O'Halloran * 39ff79e11aSOliver O'Halloran * NB: $PE_COUNT is the number of PEs that the PHB supports. 40ff79e11aSOliver O'Halloran * 41ff79e11aSOliver O'Halloran * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized 42ff79e11aSOliver O'Halloran * segments. The n'th segment is mapped to the n'th PE. 43ff79e11aSOliver O'Halloran * b) An un-segmented BAR that maps the whole address range to a specific PE. 44ff79e11aSOliver O'Halloran * 45ff79e11aSOliver O'Halloran * 46ff79e11aSOliver O'Halloran * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR 47ff79e11aSOliver O'Halloran * For comparison b) requires one entry per-VF per-BAR, or: 48ff79e11aSOliver O'Halloran * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment 49ff79e11aSOliver O'Halloran * to equal the size of the per-VF BAR area. So: 50ff79e11aSOliver O'Halloran * 51ff79e11aSOliver O'Halloran * new_size = per-vf-size * number-of-PEs 52ff79e11aSOliver O'Halloran * 53ff79e11aSOliver O'Halloran * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size 54ff79e11aSOliver O'Halloran * to "new_size", calculated above. Implementing this is a convoluted process 55ff79e11aSOliver O'Halloran * which requires several hooks in the PCI core: 56ff79e11aSOliver O'Halloran * 57ff79e11aSOliver O'Halloran * 1. In pcibios_add_device() we call pnv_pci_ioda_fixup_iov(). 58ff79e11aSOliver O'Halloran * 59ff79e11aSOliver O'Halloran * At this point the device has been probed and the device's BARs are sized, 60ff79e11aSOliver O'Halloran * but no resource allocations have been done. The SR-IOV BARs are sized 61ff79e11aSOliver O'Halloran * based on the maximum number of VFs supported by the device and we need 62ff79e11aSOliver O'Halloran * to increase that to new_size. 63ff79e11aSOliver O'Halloran * 64ff79e11aSOliver O'Halloran * 2. Later, when Linux actually assigns resources it tries to make the resource 65ff79e11aSOliver O'Halloran * allocations for each PCI bus as compact as possible. As a part of that it 66ff79e11aSOliver O'Halloran * sorts the BARs on a bus by their required alignment, which is calculated 67ff79e11aSOliver O'Halloran * using pci_resource_alignment(). 68ff79e11aSOliver O'Halloran * 69ff79e11aSOliver O'Halloran * For IOV resources this goes: 70ff79e11aSOliver O'Halloran * pci_resource_alignment() 71ff79e11aSOliver O'Halloran * pci_sriov_resource_alignment() 72ff79e11aSOliver O'Halloran * pcibios_sriov_resource_alignment() 73ff79e11aSOliver O'Halloran * pnv_pci_iov_resource_alignment() 74ff79e11aSOliver O'Halloran * 75ff79e11aSOliver O'Halloran * Our hook overrides the default alignment, equal to the per-vf-size, with 76ff79e11aSOliver O'Halloran * new_size computed above. 77ff79e11aSOliver O'Halloran * 78ff79e11aSOliver O'Halloran * 3. When userspace enables VFs for a device: 79ff79e11aSOliver O'Halloran * 80ff79e11aSOliver O'Halloran * sriov_enable() 81ff79e11aSOliver O'Halloran * pcibios_sriov_enable() 82ff79e11aSOliver O'Halloran * pnv_pcibios_sriov_enable() 83ff79e11aSOliver O'Halloran * 84ff79e11aSOliver O'Halloran * This is where we actually allocate PE numbers for each VF and setup the 85ff79e11aSOliver O'Halloran * MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena" 86ff79e11aSOliver O'Halloran * where each MBT segment is equal in size to the VF BAR so we can shift 87ff79e11aSOliver O'Halloran * around the actual SR-IOV BAR location within this arena. We need this 88ff79e11aSOliver O'Halloran * ability because the PE space is shared by all devices on the same PHB. 89ff79e11aSOliver O'Halloran * When using mode a) described above segment 0 in maps to PE#0 which might 90ff79e11aSOliver O'Halloran * be already being used by another device on the PHB. 91ff79e11aSOliver O'Halloran * 92ff79e11aSOliver O'Halloran * As a result we need allocate a contigious range of PE numbers, then shift 93ff79e11aSOliver O'Halloran * the address programmed into the SR-IOV BAR of the PF so that the address 94ff79e11aSOliver O'Halloran * of VF0 matches up with the segment corresponding to the first allocated 95ff79e11aSOliver O'Halloran * PE number. This is handled in pnv_pci_vf_resource_shift(). 96ff79e11aSOliver O'Halloran * 97ff79e11aSOliver O'Halloran * Once all that is done we return to the PCI core which then enables VFs, 98ff79e11aSOliver O'Halloran * scans them and creates pci_devs for each. The init process for a VF is 99ff79e11aSOliver O'Halloran * largely the same as a normal device, but the VF is inserted into the IODA 100ff79e11aSOliver O'Halloran * PE that we allocated for it rather than the PE associated with the bus. 101ff79e11aSOliver O'Halloran * 102ff79e11aSOliver O'Halloran * 4. When userspace disables VFs we unwind the above in 103ff79e11aSOliver O'Halloran * pnv_pcibios_sriov_disable(). Fortunately this is relatively simple since 104ff79e11aSOliver O'Halloran * we don't need to validate anything, just tear down the mappings and 105ff79e11aSOliver O'Halloran * move SR-IOV resource back to its "proper" location. 106ff79e11aSOliver O'Halloran * 107ff79e11aSOliver O'Halloran * That's how mode a) works. In theory mode b) (single PE mapping) is less work 108ff79e11aSOliver O'Halloran * since we can map each individual VF with a separate BAR. However, there's a 109ff79e11aSOliver O'Halloran * few limitations: 110ff79e11aSOliver O'Halloran * 111ff79e11aSOliver O'Halloran * 1) For IODA2 mode b) has a minimum alignment requirement of 32MB. This makes 112ff79e11aSOliver O'Halloran * it only usable for devices with very large per-VF BARs. Such devices are 113ff79e11aSOliver O'Halloran * similar to Big Foot. They definitely exist, but I've never seen one. 114ff79e11aSOliver O'Halloran * 115ff79e11aSOliver O'Halloran * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only 116ff79e11aSOliver O'Halloran * 16 total and some are needed for. Most SR-IOV capable network cards can support 117ff79e11aSOliver O'Halloran * more than 16 VFs on each port. 118ff79e11aSOliver O'Halloran * 119ff79e11aSOliver O'Halloran * We use b) when using a) would use more than 1/4 of the entire 64 bit MMIO 120ff79e11aSOliver O'Halloran * window of the PHB. 121ff79e11aSOliver O'Halloran * 122ff79e11aSOliver O'Halloran * 123ff79e11aSOliver O'Halloran * 124ff79e11aSOliver O'Halloran * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It 125ff79e11aSOliver O'Halloran * allowed the MBT to map 32bit MMIO space in addition to 64bit which allows 126ff79e11aSOliver O'Halloran * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since 127ff79e11aSOliver O'Halloran * the Linux BAR allocation will place any BAR marked as non-prefetchable into 128ff79e11aSOliver O'Halloran * the non-prefetchable bridge window, which is 32bit only. It also added two 129ff79e11aSOliver O'Halloran * new modes: 130ff79e11aSOliver O'Halloran * 131ff79e11aSOliver O'Halloran * c) A segmented BAR similar to a), but each segment can be individually 132ff79e11aSOliver O'Halloran * mapped to any PE. This is matches how the 32bit MMIO window worked on 133ff79e11aSOliver O'Halloran * IODA1&2. 134ff79e11aSOliver O'Halloran * 135ff79e11aSOliver O'Halloran * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a), 136ff79e11aSOliver O'Halloran * but with fewer segments and configurable base PE. 137ff79e11aSOliver O'Halloran * 138ff79e11aSOliver O'Halloran * i.e. The n'th segment maps to the (n + base)'th PE. 139ff79e11aSOliver O'Halloran * 140ff79e11aSOliver O'Halloran * The base PE is also required to be a multiple of the window size. 141ff79e11aSOliver O'Halloran * 142ff79e11aSOliver O'Halloran * Unfortunately, the OPAL API doesn't currently (as of skiboot v6.6) allow us 143ff79e11aSOliver O'Halloran * to exploit any of the IODA3 features. 144ff79e11aSOliver O'Halloran */ 14537b59ef0SOliver O'Halloran 14637b59ef0SOliver O'Halloran static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 14737b59ef0SOliver O'Halloran { 14837b59ef0SOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 14937b59ef0SOliver O'Halloran const resource_size_t gate = phb->ioda.m64_segsize >> 2; 15037b59ef0SOliver O'Halloran struct resource *res; 15137b59ef0SOliver O'Halloran int i; 15237b59ef0SOliver O'Halloran resource_size_t size, total_vf_bar_sz; 15337b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 15437b59ef0SOliver O'Halloran int mul, total_vfs; 15537b59ef0SOliver O'Halloran 15637b59ef0SOliver O'Halloran iov = kzalloc(sizeof(*iov), GFP_KERNEL); 15737b59ef0SOliver O'Halloran if (!iov) 15837b59ef0SOliver O'Halloran goto truncate_iov; 15937b59ef0SOliver O'Halloran pdev->dev.archdata.iov_data = iov; 16037b59ef0SOliver O'Halloran 16137b59ef0SOliver O'Halloran total_vfs = pci_sriov_get_totalvfs(pdev); 16237b59ef0SOliver O'Halloran mul = phb->ioda.total_pe_num; 16337b59ef0SOliver O'Halloran total_vf_bar_sz = 0; 16437b59ef0SOliver O'Halloran 16537b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 16637b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES]; 16737b59ef0SOliver O'Halloran if (!res->flags || res->parent) 16837b59ef0SOliver O'Halloran continue; 16937b59ef0SOliver O'Halloran if (!pnv_pci_is_m64_flags(res->flags)) { 17037b59ef0SOliver O'Halloran dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n", 17137b59ef0SOliver O'Halloran i, res); 17237b59ef0SOliver O'Halloran goto truncate_iov; 17337b59ef0SOliver O'Halloran } 17437b59ef0SOliver O'Halloran 17537b59ef0SOliver O'Halloran total_vf_bar_sz += pci_iov_resource_size(pdev, 17637b59ef0SOliver O'Halloran i + PCI_IOV_RESOURCES); 17737b59ef0SOliver O'Halloran 17837b59ef0SOliver O'Halloran /* 17937b59ef0SOliver O'Halloran * If bigger than quarter of M64 segment size, just round up 18037b59ef0SOliver O'Halloran * power of two. 18137b59ef0SOliver O'Halloran * 18237b59ef0SOliver O'Halloran * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 18337b59ef0SOliver O'Halloran * with other devices, IOV BAR size is expanded to be 18437b59ef0SOliver O'Halloran * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 18537b59ef0SOliver O'Halloran * segment size , the expanded size would equal to half of the 18637b59ef0SOliver O'Halloran * whole M64 space size, which will exhaust the M64 Space and 18737b59ef0SOliver O'Halloran * limit the system flexibility. This is a design decision to 18837b59ef0SOliver O'Halloran * set the boundary to quarter of the M64 segment size. 18937b59ef0SOliver O'Halloran */ 19037b59ef0SOliver O'Halloran if (total_vf_bar_sz > gate) { 19137b59ef0SOliver O'Halloran mul = roundup_pow_of_two(total_vfs); 19237b59ef0SOliver O'Halloran dev_info(&pdev->dev, 19337b59ef0SOliver O'Halloran "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 19437b59ef0SOliver O'Halloran total_vf_bar_sz, gate, mul); 19537b59ef0SOliver O'Halloran iov->m64_single_mode = true; 19637b59ef0SOliver O'Halloran break; 19737b59ef0SOliver O'Halloran } 19837b59ef0SOliver O'Halloran } 19937b59ef0SOliver O'Halloran 20037b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 20137b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES]; 20237b59ef0SOliver O'Halloran if (!res->flags || res->parent) 20337b59ef0SOliver O'Halloran continue; 20437b59ef0SOliver O'Halloran 20537b59ef0SOliver O'Halloran size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 20637b59ef0SOliver O'Halloran /* 20737b59ef0SOliver O'Halloran * On PHB3, the minimum size alignment of M64 BAR in single 20837b59ef0SOliver O'Halloran * mode is 32MB. 20937b59ef0SOliver O'Halloran */ 21037b59ef0SOliver O'Halloran if (iov->m64_single_mode && (size < SZ_32M)) 21137b59ef0SOliver O'Halloran goto truncate_iov; 21237b59ef0SOliver O'Halloran dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 21337b59ef0SOliver O'Halloran res->end = res->start + size * mul - 1; 21437b59ef0SOliver O'Halloran dev_dbg(&pdev->dev, " %pR\n", res); 21537b59ef0SOliver O'Halloran dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 21637b59ef0SOliver O'Halloran i, res, mul); 21737b59ef0SOliver O'Halloran } 21837b59ef0SOliver O'Halloran iov->vfs_expanded = mul; 21937b59ef0SOliver O'Halloran 22037b59ef0SOliver O'Halloran return; 22137b59ef0SOliver O'Halloran 22237b59ef0SOliver O'Halloran truncate_iov: 22337b59ef0SOliver O'Halloran /* To save MMIO space, IOV BAR is truncated. */ 22437b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 22537b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES]; 22637b59ef0SOliver O'Halloran res->flags = 0; 22737b59ef0SOliver O'Halloran res->end = res->start - 1; 22837b59ef0SOliver O'Halloran } 22937b59ef0SOliver O'Halloran 23037b59ef0SOliver O'Halloran pdev->dev.archdata.iov_data = NULL; 23137b59ef0SOliver O'Halloran kfree(iov); 23237b59ef0SOliver O'Halloran } 23337b59ef0SOliver O'Halloran 23437b59ef0SOliver O'Halloran void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) 23537b59ef0SOliver O'Halloran { 23637b59ef0SOliver O'Halloran if (WARN_ON(pci_dev_is_added(pdev))) 23737b59ef0SOliver O'Halloran return; 23837b59ef0SOliver O'Halloran 23937b59ef0SOliver O'Halloran if (pdev->is_virtfn) { 24037b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev); 24137b59ef0SOliver O'Halloran 24237b59ef0SOliver O'Halloran /* 24337b59ef0SOliver O'Halloran * VF PEs are single-device PEs so their pdev pointer needs to 24437b59ef0SOliver O'Halloran * be set. The pdev doesn't exist when the PE is allocated (in 24537b59ef0SOliver O'Halloran * (pcibios_sriov_enable()) so we fix it up here. 24637b59ef0SOliver O'Halloran */ 24737b59ef0SOliver O'Halloran pe->pdev = pdev; 24837b59ef0SOliver O'Halloran WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); 24937b59ef0SOliver O'Halloran } else if (pdev->is_physfn) { 25037b59ef0SOliver O'Halloran /* 25137b59ef0SOliver O'Halloran * For PFs adjust their allocated IOV resources to match what 25237b59ef0SOliver O'Halloran * the PHB can support using it's M64 BAR table. 25337b59ef0SOliver O'Halloran */ 25437b59ef0SOliver O'Halloran pnv_pci_ioda_fixup_iov_resources(pdev); 25537b59ef0SOliver O'Halloran } 25637b59ef0SOliver O'Halloran } 25737b59ef0SOliver O'Halloran 25837b59ef0SOliver O'Halloran resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 25937b59ef0SOliver O'Halloran int resno) 26037b59ef0SOliver O'Halloran { 26137b59ef0SOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 26237b59ef0SOliver O'Halloran struct pnv_iov_data *iov = pnv_iov_get(pdev); 26337b59ef0SOliver O'Halloran resource_size_t align; 26437b59ef0SOliver O'Halloran 26537b59ef0SOliver O'Halloran /* 26637b59ef0SOliver O'Halloran * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 26737b59ef0SOliver O'Halloran * SR-IOV. While from hardware perspective, the range mapped by M64 26837b59ef0SOliver O'Halloran * BAR should be size aligned. 26937b59ef0SOliver O'Halloran * 27037b59ef0SOliver O'Halloran * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 27137b59ef0SOliver O'Halloran * powernv-specific hardware restriction is gone. But if just use the 27237b59ef0SOliver O'Halloran * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 27337b59ef0SOliver O'Halloran * in one segment of M64 #15, which introduces the PE conflict between 27437b59ef0SOliver O'Halloran * PF and VF. Based on this, the minimum alignment of an IOV BAR is 27537b59ef0SOliver O'Halloran * m64_segsize. 27637b59ef0SOliver O'Halloran * 27737b59ef0SOliver O'Halloran * This function returns the total IOV BAR size if M64 BAR is in 27837b59ef0SOliver O'Halloran * Shared PE mode or just VF BAR size if not. 27937b59ef0SOliver O'Halloran * If the M64 BAR is in Single PE mode, return the VF BAR size or 28037b59ef0SOliver O'Halloran * M64 segment size if IOV BAR size is less. 28137b59ef0SOliver O'Halloran */ 28237b59ef0SOliver O'Halloran align = pci_iov_resource_size(pdev, resno); 28337b59ef0SOliver O'Halloran 28437b59ef0SOliver O'Halloran /* 28537b59ef0SOliver O'Halloran * iov can be null if we have an SR-IOV device with IOV BAR that can't 28637b59ef0SOliver O'Halloran * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch). 28737b59ef0SOliver O'Halloran * In that case we don't allow VFs to be enabled so just return the 28837b59ef0SOliver O'Halloran * default alignment. 28937b59ef0SOliver O'Halloran */ 29037b59ef0SOliver O'Halloran if (!iov) 29137b59ef0SOliver O'Halloran return align; 29237b59ef0SOliver O'Halloran if (!iov->vfs_expanded) 29337b59ef0SOliver O'Halloran return align; 29437b59ef0SOliver O'Halloran if (iov->m64_single_mode) 29537b59ef0SOliver O'Halloran return max(align, (resource_size_t)phb->ioda.m64_segsize); 29637b59ef0SOliver O'Halloran 29737b59ef0SOliver O'Halloran return iov->vfs_expanded * align; 29837b59ef0SOliver O'Halloran } 29937b59ef0SOliver O'Halloran 30037b59ef0SOliver O'Halloran static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 30137b59ef0SOliver O'Halloran { 30237b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 30337b59ef0SOliver O'Halloran struct pnv_phb *phb; 30437b59ef0SOliver O'Halloran int i, j; 30537b59ef0SOliver O'Halloran int m64_bars; 30637b59ef0SOliver O'Halloran 30737b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 30837b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 30937b59ef0SOliver O'Halloran 31037b59ef0SOliver O'Halloran if (iov->m64_single_mode) 31137b59ef0SOliver O'Halloran m64_bars = num_vfs; 31237b59ef0SOliver O'Halloran else 31337b59ef0SOliver O'Halloran m64_bars = 1; 31437b59ef0SOliver O'Halloran 31537b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) 31637b59ef0SOliver O'Halloran for (j = 0; j < m64_bars; j++) { 31737b59ef0SOliver O'Halloran if (iov->m64_map[j][i] == IODA_INVALID_M64) 31837b59ef0SOliver O'Halloran continue; 31937b59ef0SOliver O'Halloran opal_pci_phb_mmio_enable(phb->opal_id, 32037b59ef0SOliver O'Halloran OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 0); 32137b59ef0SOliver O'Halloran clear_bit(iov->m64_map[j][i], &phb->ioda.m64_bar_alloc); 32237b59ef0SOliver O'Halloran iov->m64_map[j][i] = IODA_INVALID_M64; 32337b59ef0SOliver O'Halloran } 32437b59ef0SOliver O'Halloran 32537b59ef0SOliver O'Halloran kfree(iov->m64_map); 32637b59ef0SOliver O'Halloran return 0; 32737b59ef0SOliver O'Halloran } 32837b59ef0SOliver O'Halloran 32937b59ef0SOliver O'Halloran static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 33037b59ef0SOliver O'Halloran { 33137b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 33237b59ef0SOliver O'Halloran struct pnv_phb *phb; 33337b59ef0SOliver O'Halloran unsigned int win; 33437b59ef0SOliver O'Halloran struct resource *res; 33537b59ef0SOliver O'Halloran int i, j; 33637b59ef0SOliver O'Halloran int64_t rc; 33737b59ef0SOliver O'Halloran int total_vfs; 33837b59ef0SOliver O'Halloran resource_size_t size, start; 33937b59ef0SOliver O'Halloran int pe_num; 34037b59ef0SOliver O'Halloran int m64_bars; 34137b59ef0SOliver O'Halloran 34237b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 34337b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 34437b59ef0SOliver O'Halloran total_vfs = pci_sriov_get_totalvfs(pdev); 34537b59ef0SOliver O'Halloran 34637b59ef0SOliver O'Halloran if (iov->m64_single_mode) 34737b59ef0SOliver O'Halloran m64_bars = num_vfs; 34837b59ef0SOliver O'Halloran else 34937b59ef0SOliver O'Halloran m64_bars = 1; 35037b59ef0SOliver O'Halloran 35137b59ef0SOliver O'Halloran iov->m64_map = kmalloc_array(m64_bars, 35237b59ef0SOliver O'Halloran sizeof(*iov->m64_map), 35337b59ef0SOliver O'Halloran GFP_KERNEL); 35437b59ef0SOliver O'Halloran if (!iov->m64_map) 35537b59ef0SOliver O'Halloran return -ENOMEM; 35637b59ef0SOliver O'Halloran /* Initialize the m64_map to IODA_INVALID_M64 */ 35737b59ef0SOliver O'Halloran for (i = 0; i < m64_bars ; i++) 35837b59ef0SOliver O'Halloran for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) 35937b59ef0SOliver O'Halloran iov->m64_map[i][j] = IODA_INVALID_M64; 36037b59ef0SOliver O'Halloran 36137b59ef0SOliver O'Halloran 36237b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 36337b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES]; 36437b59ef0SOliver O'Halloran if (!res->flags || !res->parent) 36537b59ef0SOliver O'Halloran continue; 36637b59ef0SOliver O'Halloran 36737b59ef0SOliver O'Halloran for (j = 0; j < m64_bars; j++) { 36837b59ef0SOliver O'Halloran do { 36937b59ef0SOliver O'Halloran win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 37037b59ef0SOliver O'Halloran phb->ioda.m64_bar_idx + 1, 0); 37137b59ef0SOliver O'Halloran 37237b59ef0SOliver O'Halloran if (win >= phb->ioda.m64_bar_idx + 1) 37337b59ef0SOliver O'Halloran goto m64_failed; 37437b59ef0SOliver O'Halloran } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 37537b59ef0SOliver O'Halloran 37637b59ef0SOliver O'Halloran iov->m64_map[j][i] = win; 37737b59ef0SOliver O'Halloran 37837b59ef0SOliver O'Halloran if (iov->m64_single_mode) { 37937b59ef0SOliver O'Halloran size = pci_iov_resource_size(pdev, 38037b59ef0SOliver O'Halloran PCI_IOV_RESOURCES + i); 38137b59ef0SOliver O'Halloran start = res->start + size * j; 38237b59ef0SOliver O'Halloran } else { 38337b59ef0SOliver O'Halloran size = resource_size(res); 38437b59ef0SOliver O'Halloran start = res->start; 38537b59ef0SOliver O'Halloran } 38637b59ef0SOliver O'Halloran 38737b59ef0SOliver O'Halloran /* Map the M64 here */ 38837b59ef0SOliver O'Halloran if (iov->m64_single_mode) { 38937b59ef0SOliver O'Halloran pe_num = iov->pe_num_map[j]; 39037b59ef0SOliver O'Halloran rc = opal_pci_map_pe_mmio_window(phb->opal_id, 39137b59ef0SOliver O'Halloran pe_num, OPAL_M64_WINDOW_TYPE, 39237b59ef0SOliver O'Halloran iov->m64_map[j][i], 0); 39337b59ef0SOliver O'Halloran } 39437b59ef0SOliver O'Halloran 39537b59ef0SOliver O'Halloran rc = opal_pci_set_phb_mem_window(phb->opal_id, 39637b59ef0SOliver O'Halloran OPAL_M64_WINDOW_TYPE, 39737b59ef0SOliver O'Halloran iov->m64_map[j][i], 39837b59ef0SOliver O'Halloran start, 39937b59ef0SOliver O'Halloran 0, /* unused */ 40037b59ef0SOliver O'Halloran size); 40137b59ef0SOliver O'Halloran 40237b59ef0SOliver O'Halloran 40337b59ef0SOliver O'Halloran if (rc != OPAL_SUCCESS) { 40437b59ef0SOliver O'Halloran dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 40537b59ef0SOliver O'Halloran win, rc); 40637b59ef0SOliver O'Halloran goto m64_failed; 40737b59ef0SOliver O'Halloran } 40837b59ef0SOliver O'Halloran 40937b59ef0SOliver O'Halloran if (iov->m64_single_mode) 41037b59ef0SOliver O'Halloran rc = opal_pci_phb_mmio_enable(phb->opal_id, 41137b59ef0SOliver O'Halloran OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 2); 41237b59ef0SOliver O'Halloran else 41337b59ef0SOliver O'Halloran rc = opal_pci_phb_mmio_enable(phb->opal_id, 41437b59ef0SOliver O'Halloran OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 1); 41537b59ef0SOliver O'Halloran 41637b59ef0SOliver O'Halloran if (rc != OPAL_SUCCESS) { 41737b59ef0SOliver O'Halloran dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", 41837b59ef0SOliver O'Halloran win, rc); 41937b59ef0SOliver O'Halloran goto m64_failed; 42037b59ef0SOliver O'Halloran } 42137b59ef0SOliver O'Halloran } 42237b59ef0SOliver O'Halloran } 42337b59ef0SOliver O'Halloran return 0; 42437b59ef0SOliver O'Halloran 42537b59ef0SOliver O'Halloran m64_failed: 42637b59ef0SOliver O'Halloran pnv_pci_vf_release_m64(pdev, num_vfs); 42737b59ef0SOliver O'Halloran return -EBUSY; 42837b59ef0SOliver O'Halloran } 42937b59ef0SOliver O'Halloran 43037b59ef0SOliver O'Halloran static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 43137b59ef0SOliver O'Halloran { 43237b59ef0SOliver O'Halloran struct pnv_phb *phb; 43337b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe, *pe_n; 43437b59ef0SOliver O'Halloran 43537b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 43637b59ef0SOliver O'Halloran 43737b59ef0SOliver O'Halloran if (!pdev->is_physfn) 43837b59ef0SOliver O'Halloran return; 43937b59ef0SOliver O'Halloran 44037b59ef0SOliver O'Halloran /* FIXME: Use pnv_ioda_release_pe()? */ 44137b59ef0SOliver O'Halloran list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 44237b59ef0SOliver O'Halloran if (pe->parent_dev != pdev) 44337b59ef0SOliver O'Halloran continue; 44437b59ef0SOliver O'Halloran 44537b59ef0SOliver O'Halloran pnv_pci_ioda2_release_pe_dma(pe); 44637b59ef0SOliver O'Halloran 44737b59ef0SOliver O'Halloran /* Remove from list */ 44837b59ef0SOliver O'Halloran mutex_lock(&phb->ioda.pe_list_mutex); 44937b59ef0SOliver O'Halloran list_del(&pe->list); 45037b59ef0SOliver O'Halloran mutex_unlock(&phb->ioda.pe_list_mutex); 45137b59ef0SOliver O'Halloran 45237b59ef0SOliver O'Halloran pnv_ioda_deconfigure_pe(phb, pe); 45337b59ef0SOliver O'Halloran 45437b59ef0SOliver O'Halloran pnv_ioda_free_pe(pe); 45537b59ef0SOliver O'Halloran } 45637b59ef0SOliver O'Halloran } 45737b59ef0SOliver O'Halloran 45837b59ef0SOliver O'Halloran static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 45937b59ef0SOliver O'Halloran { 46037b59ef0SOliver O'Halloran struct resource *res, res2; 46137b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 46237b59ef0SOliver O'Halloran resource_size_t size; 46337b59ef0SOliver O'Halloran u16 num_vfs; 46437b59ef0SOliver O'Halloran int i; 46537b59ef0SOliver O'Halloran 46637b59ef0SOliver O'Halloran if (!dev->is_physfn) 46737b59ef0SOliver O'Halloran return -EINVAL; 46837b59ef0SOliver O'Halloran iov = pnv_iov_get(dev); 46937b59ef0SOliver O'Halloran 47037b59ef0SOliver O'Halloran /* 47137b59ef0SOliver O'Halloran * "offset" is in VFs. The M64 windows are sized so that when they 47237b59ef0SOliver O'Halloran * are segmented, each segment is the same size as the IOV BAR. 47337b59ef0SOliver O'Halloran * Each segment is in a separate PE, and the high order bits of the 47437b59ef0SOliver O'Halloran * address are the PE number. Therefore, each VF's BAR is in a 47537b59ef0SOliver O'Halloran * separate PE, and changing the IOV BAR start address changes the 47637b59ef0SOliver O'Halloran * range of PEs the VFs are in. 47737b59ef0SOliver O'Halloran */ 47837b59ef0SOliver O'Halloran num_vfs = iov->num_vfs; 47937b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 48037b59ef0SOliver O'Halloran res = &dev->resource[i + PCI_IOV_RESOURCES]; 48137b59ef0SOliver O'Halloran if (!res->flags || !res->parent) 48237b59ef0SOliver O'Halloran continue; 48337b59ef0SOliver O'Halloran 48437b59ef0SOliver O'Halloran /* 48537b59ef0SOliver O'Halloran * The actual IOV BAR range is determined by the start address 48637b59ef0SOliver O'Halloran * and the actual size for num_vfs VFs BAR. This check is to 48737b59ef0SOliver O'Halloran * make sure that after shifting, the range will not overlap 48837b59ef0SOliver O'Halloran * with another device. 48937b59ef0SOliver O'Halloran */ 49037b59ef0SOliver O'Halloran size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 49137b59ef0SOliver O'Halloran res2.flags = res->flags; 49237b59ef0SOliver O'Halloran res2.start = res->start + (size * offset); 49337b59ef0SOliver O'Halloran res2.end = res2.start + (size * num_vfs) - 1; 49437b59ef0SOliver O'Halloran 49537b59ef0SOliver O'Halloran if (res2.end > res->end) { 49637b59ef0SOliver O'Halloran dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 49737b59ef0SOliver O'Halloran i, &res2, res, num_vfs, offset); 49837b59ef0SOliver O'Halloran return -EBUSY; 49937b59ef0SOliver O'Halloran } 50037b59ef0SOliver O'Halloran } 50137b59ef0SOliver O'Halloran 50237b59ef0SOliver O'Halloran /* 50337b59ef0SOliver O'Halloran * Since M64 BAR shares segments among all possible 256 PEs, 50437b59ef0SOliver O'Halloran * we have to shift the beginning of PF IOV BAR to make it start from 50537b59ef0SOliver O'Halloran * the segment which belongs to the PE number assigned to the first VF. 50637b59ef0SOliver O'Halloran * This creates a "hole" in the /proc/iomem which could be used for 50737b59ef0SOliver O'Halloran * allocating other resources so we reserve this area below and 50837b59ef0SOliver O'Halloran * release when IOV is released. 50937b59ef0SOliver O'Halloran */ 51037b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 51137b59ef0SOliver O'Halloran res = &dev->resource[i + PCI_IOV_RESOURCES]; 51237b59ef0SOliver O'Halloran if (!res->flags || !res->parent) 51337b59ef0SOliver O'Halloran continue; 51437b59ef0SOliver O'Halloran 51537b59ef0SOliver O'Halloran size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 51637b59ef0SOliver O'Halloran res2 = *res; 51737b59ef0SOliver O'Halloran res->start += size * offset; 51837b59ef0SOliver O'Halloran 51937b59ef0SOliver O'Halloran dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 52037b59ef0SOliver O'Halloran i, &res2, res, (offset > 0) ? "En" : "Dis", 52137b59ef0SOliver O'Halloran num_vfs, offset); 52237b59ef0SOliver O'Halloran 52337b59ef0SOliver O'Halloran if (offset < 0) { 52437b59ef0SOliver O'Halloran devm_release_resource(&dev->dev, &iov->holes[i]); 52537b59ef0SOliver O'Halloran memset(&iov->holes[i], 0, sizeof(iov->holes[i])); 52637b59ef0SOliver O'Halloran } 52737b59ef0SOliver O'Halloran 52837b59ef0SOliver O'Halloran pci_update_resource(dev, i + PCI_IOV_RESOURCES); 52937b59ef0SOliver O'Halloran 53037b59ef0SOliver O'Halloran if (offset > 0) { 53137b59ef0SOliver O'Halloran iov->holes[i].start = res2.start; 53237b59ef0SOliver O'Halloran iov->holes[i].end = res2.start + size * offset - 1; 53337b59ef0SOliver O'Halloran iov->holes[i].flags = IORESOURCE_BUS; 53437b59ef0SOliver O'Halloran iov->holes[i].name = "pnv_iov_reserved"; 53537b59ef0SOliver O'Halloran devm_request_resource(&dev->dev, res->parent, 53637b59ef0SOliver O'Halloran &iov->holes[i]); 53737b59ef0SOliver O'Halloran } 53837b59ef0SOliver O'Halloran } 53937b59ef0SOliver O'Halloran return 0; 54037b59ef0SOliver O'Halloran } 54137b59ef0SOliver O'Halloran 54237b59ef0SOliver O'Halloran static void pnv_pci_sriov_disable(struct pci_dev *pdev) 54337b59ef0SOliver O'Halloran { 54437b59ef0SOliver O'Halloran struct pnv_phb *phb; 54537b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe; 54637b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 54737b59ef0SOliver O'Halloran u16 num_vfs, i; 54837b59ef0SOliver O'Halloran 54937b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 55037b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 55137b59ef0SOliver O'Halloran num_vfs = iov->num_vfs; 55237b59ef0SOliver O'Halloran 55337b59ef0SOliver O'Halloran /* Release VF PEs */ 55437b59ef0SOliver O'Halloran pnv_ioda_release_vf_PE(pdev); 55537b59ef0SOliver O'Halloran 55637b59ef0SOliver O'Halloran if (phb->type == PNV_PHB_IODA2) { 55737b59ef0SOliver O'Halloran if (!iov->m64_single_mode) 55837b59ef0SOliver O'Halloran pnv_pci_vf_resource_shift(pdev, -*iov->pe_num_map); 55937b59ef0SOliver O'Halloran 56037b59ef0SOliver O'Halloran /* Release M64 windows */ 56137b59ef0SOliver O'Halloran pnv_pci_vf_release_m64(pdev, num_vfs); 56237b59ef0SOliver O'Halloran 56337b59ef0SOliver O'Halloran /* Release PE numbers */ 56437b59ef0SOliver O'Halloran if (iov->m64_single_mode) { 56537b59ef0SOliver O'Halloran for (i = 0; i < num_vfs; i++) { 56637b59ef0SOliver O'Halloran if (iov->pe_num_map[i] == IODA_INVALID_PE) 56737b59ef0SOliver O'Halloran continue; 56837b59ef0SOliver O'Halloran 56937b59ef0SOliver O'Halloran pe = &phb->ioda.pe_array[iov->pe_num_map[i]]; 57037b59ef0SOliver O'Halloran pnv_ioda_free_pe(pe); 57137b59ef0SOliver O'Halloran } 57237b59ef0SOliver O'Halloran } else 57337b59ef0SOliver O'Halloran bitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 57437b59ef0SOliver O'Halloran /* Releasing pe_num_map */ 57537b59ef0SOliver O'Halloran kfree(iov->pe_num_map); 57637b59ef0SOliver O'Halloran } 57737b59ef0SOliver O'Halloran } 57837b59ef0SOliver O'Halloran 57937b59ef0SOliver O'Halloran static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 58037b59ef0SOliver O'Halloran { 58137b59ef0SOliver O'Halloran struct pnv_phb *phb; 58237b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe; 58337b59ef0SOliver O'Halloran int pe_num; 58437b59ef0SOliver O'Halloran u16 vf_index; 58537b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 58637b59ef0SOliver O'Halloran struct pci_dn *pdn; 58737b59ef0SOliver O'Halloran 58837b59ef0SOliver O'Halloran if (!pdev->is_physfn) 58937b59ef0SOliver O'Halloran return; 59037b59ef0SOliver O'Halloran 59137b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 59237b59ef0SOliver O'Halloran pdn = pci_get_pdn(pdev); 59337b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 59437b59ef0SOliver O'Halloran 59537b59ef0SOliver O'Halloran /* Reserve PE for each VF */ 59637b59ef0SOliver O'Halloran for (vf_index = 0; vf_index < num_vfs; vf_index++) { 59737b59ef0SOliver O'Halloran int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 59837b59ef0SOliver O'Halloran int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 59937b59ef0SOliver O'Halloran struct pci_dn *vf_pdn; 60037b59ef0SOliver O'Halloran 60137b59ef0SOliver O'Halloran if (iov->m64_single_mode) 60237b59ef0SOliver O'Halloran pe_num = iov->pe_num_map[vf_index]; 60337b59ef0SOliver O'Halloran else 60437b59ef0SOliver O'Halloran pe_num = *iov->pe_num_map + vf_index; 60537b59ef0SOliver O'Halloran 60637b59ef0SOliver O'Halloran pe = &phb->ioda.pe_array[pe_num]; 60737b59ef0SOliver O'Halloran pe->pe_number = pe_num; 60837b59ef0SOliver O'Halloran pe->phb = phb; 60937b59ef0SOliver O'Halloran pe->flags = PNV_IODA_PE_VF; 61037b59ef0SOliver O'Halloran pe->pbus = NULL; 61137b59ef0SOliver O'Halloran pe->parent_dev = pdev; 61237b59ef0SOliver O'Halloran pe->mve_number = -1; 61337b59ef0SOliver O'Halloran pe->rid = (vf_bus << 8) | vf_devfn; 61437b59ef0SOliver O'Halloran 61537b59ef0SOliver O'Halloran pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 61637b59ef0SOliver O'Halloran pci_domain_nr(pdev->bus), pdev->bus->number, 61737b59ef0SOliver O'Halloran PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 61837b59ef0SOliver O'Halloran 61937b59ef0SOliver O'Halloran if (pnv_ioda_configure_pe(phb, pe)) { 62037b59ef0SOliver O'Halloran /* XXX What do we do here ? */ 62137b59ef0SOliver O'Halloran pnv_ioda_free_pe(pe); 62237b59ef0SOliver O'Halloran pe->pdev = NULL; 62337b59ef0SOliver O'Halloran continue; 62437b59ef0SOliver O'Halloran } 62537b59ef0SOliver O'Halloran 62637b59ef0SOliver O'Halloran /* Put PE to the list */ 62737b59ef0SOliver O'Halloran mutex_lock(&phb->ioda.pe_list_mutex); 62837b59ef0SOliver O'Halloran list_add_tail(&pe->list, &phb->ioda.pe_list); 62937b59ef0SOliver O'Halloran mutex_unlock(&phb->ioda.pe_list_mutex); 63037b59ef0SOliver O'Halloran 63137b59ef0SOliver O'Halloran /* associate this pe to it's pdn */ 63237b59ef0SOliver O'Halloran list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 63337b59ef0SOliver O'Halloran if (vf_pdn->busno == vf_bus && 63437b59ef0SOliver O'Halloran vf_pdn->devfn == vf_devfn) { 63537b59ef0SOliver O'Halloran vf_pdn->pe_number = pe_num; 63637b59ef0SOliver O'Halloran break; 63737b59ef0SOliver O'Halloran } 63837b59ef0SOliver O'Halloran } 63937b59ef0SOliver O'Halloran 64037b59ef0SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe); 64137b59ef0SOliver O'Halloran } 64237b59ef0SOliver O'Halloran } 64337b59ef0SOliver O'Halloran 64437b59ef0SOliver O'Halloran static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 64537b59ef0SOliver O'Halloran { 64637b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 64737b59ef0SOliver O'Halloran struct pnv_phb *phb; 64837b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe; 64937b59ef0SOliver O'Halloran int ret; 65037b59ef0SOliver O'Halloran u16 i; 65137b59ef0SOliver O'Halloran 65237b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 65337b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 65437b59ef0SOliver O'Halloran 65537b59ef0SOliver O'Halloran if (phb->type == PNV_PHB_IODA2) { 65637b59ef0SOliver O'Halloran if (!iov->vfs_expanded) { 65737b59ef0SOliver O'Halloran dev_info(&pdev->dev, 65837b59ef0SOliver O'Halloran "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n"); 65937b59ef0SOliver O'Halloran return -ENOSPC; 66037b59ef0SOliver O'Halloran } 66137b59ef0SOliver O'Halloran 66237b59ef0SOliver O'Halloran /* 66337b59ef0SOliver O'Halloran * When M64 BARs functions in Single PE mode, the number of VFs 66437b59ef0SOliver O'Halloran * could be enabled must be less than the number of M64 BARs. 66537b59ef0SOliver O'Halloran */ 66637b59ef0SOliver O'Halloran if (iov->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { 66737b59ef0SOliver O'Halloran dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); 66837b59ef0SOliver O'Halloran return -EBUSY; 66937b59ef0SOliver O'Halloran } 67037b59ef0SOliver O'Halloran 67137b59ef0SOliver O'Halloran /* Allocating pe_num_map */ 67237b59ef0SOliver O'Halloran if (iov->m64_single_mode) 67337b59ef0SOliver O'Halloran iov->pe_num_map = kmalloc_array(num_vfs, 67437b59ef0SOliver O'Halloran sizeof(*iov->pe_num_map), 67537b59ef0SOliver O'Halloran GFP_KERNEL); 67637b59ef0SOliver O'Halloran else 67737b59ef0SOliver O'Halloran iov->pe_num_map = kmalloc(sizeof(*iov->pe_num_map), GFP_KERNEL); 67837b59ef0SOliver O'Halloran 67937b59ef0SOliver O'Halloran if (!iov->pe_num_map) 68037b59ef0SOliver O'Halloran return -ENOMEM; 68137b59ef0SOliver O'Halloran 68237b59ef0SOliver O'Halloran if (iov->m64_single_mode) 68337b59ef0SOliver O'Halloran for (i = 0; i < num_vfs; i++) 68437b59ef0SOliver O'Halloran iov->pe_num_map[i] = IODA_INVALID_PE; 68537b59ef0SOliver O'Halloran 68637b59ef0SOliver O'Halloran /* Calculate available PE for required VFs */ 68737b59ef0SOliver O'Halloran if (iov->m64_single_mode) { 68837b59ef0SOliver O'Halloran for (i = 0; i < num_vfs; i++) { 68937b59ef0SOliver O'Halloran pe = pnv_ioda_alloc_pe(phb); 69037b59ef0SOliver O'Halloran if (!pe) { 69137b59ef0SOliver O'Halloran ret = -EBUSY; 69237b59ef0SOliver O'Halloran goto m64_failed; 69337b59ef0SOliver O'Halloran } 69437b59ef0SOliver O'Halloran 69537b59ef0SOliver O'Halloran iov->pe_num_map[i] = pe->pe_number; 69637b59ef0SOliver O'Halloran } 69737b59ef0SOliver O'Halloran } else { 69837b59ef0SOliver O'Halloran mutex_lock(&phb->ioda.pe_alloc_mutex); 69937b59ef0SOliver O'Halloran *iov->pe_num_map = bitmap_find_next_zero_area( 70037b59ef0SOliver O'Halloran phb->ioda.pe_alloc, phb->ioda.total_pe_num, 70137b59ef0SOliver O'Halloran 0, num_vfs, 0); 70237b59ef0SOliver O'Halloran if (*iov->pe_num_map >= phb->ioda.total_pe_num) { 70337b59ef0SOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 70437b59ef0SOliver O'Halloran dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); 70537b59ef0SOliver O'Halloran kfree(iov->pe_num_map); 70637b59ef0SOliver O'Halloran return -EBUSY; 70737b59ef0SOliver O'Halloran } 70837b59ef0SOliver O'Halloran bitmap_set(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 70937b59ef0SOliver O'Halloran mutex_unlock(&phb->ioda.pe_alloc_mutex); 71037b59ef0SOliver O'Halloran } 71137b59ef0SOliver O'Halloran iov->num_vfs = num_vfs; 71237b59ef0SOliver O'Halloran 71337b59ef0SOliver O'Halloran /* Assign M64 window accordingly */ 71437b59ef0SOliver O'Halloran ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 71537b59ef0SOliver O'Halloran if (ret) { 71637b59ef0SOliver O'Halloran dev_info(&pdev->dev, "Not enough M64 window resources\n"); 71737b59ef0SOliver O'Halloran goto m64_failed; 71837b59ef0SOliver O'Halloran } 71937b59ef0SOliver O'Halloran 72037b59ef0SOliver O'Halloran /* 72137b59ef0SOliver O'Halloran * When using one M64 BAR to map one IOV BAR, we need to shift 72237b59ef0SOliver O'Halloran * the IOV BAR according to the PE# allocated to the VFs. 72337b59ef0SOliver O'Halloran * Otherwise, the PE# for the VF will conflict with others. 72437b59ef0SOliver O'Halloran */ 72537b59ef0SOliver O'Halloran if (!iov->m64_single_mode) { 72637b59ef0SOliver O'Halloran ret = pnv_pci_vf_resource_shift(pdev, *iov->pe_num_map); 72737b59ef0SOliver O'Halloran if (ret) 72837b59ef0SOliver O'Halloran goto m64_failed; 72937b59ef0SOliver O'Halloran } 73037b59ef0SOliver O'Halloran } 73137b59ef0SOliver O'Halloran 73237b59ef0SOliver O'Halloran /* Setup VF PEs */ 73337b59ef0SOliver O'Halloran pnv_ioda_setup_vf_PE(pdev, num_vfs); 73437b59ef0SOliver O'Halloran 73537b59ef0SOliver O'Halloran return 0; 73637b59ef0SOliver O'Halloran 73737b59ef0SOliver O'Halloran m64_failed: 73837b59ef0SOliver O'Halloran if (iov->m64_single_mode) { 73937b59ef0SOliver O'Halloran for (i = 0; i < num_vfs; i++) { 74037b59ef0SOliver O'Halloran if (iov->pe_num_map[i] == IODA_INVALID_PE) 74137b59ef0SOliver O'Halloran continue; 74237b59ef0SOliver O'Halloran 74337b59ef0SOliver O'Halloran pe = &phb->ioda.pe_array[iov->pe_num_map[i]]; 74437b59ef0SOliver O'Halloran pnv_ioda_free_pe(pe); 74537b59ef0SOliver O'Halloran } 74637b59ef0SOliver O'Halloran } else 74737b59ef0SOliver O'Halloran bitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs); 74837b59ef0SOliver O'Halloran 74937b59ef0SOliver O'Halloran /* Releasing pe_num_map */ 75037b59ef0SOliver O'Halloran kfree(iov->pe_num_map); 75137b59ef0SOliver O'Halloran 75237b59ef0SOliver O'Halloran return ret; 75337b59ef0SOliver O'Halloran } 75437b59ef0SOliver O'Halloran 75537b59ef0SOliver O'Halloran int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 75637b59ef0SOliver O'Halloran { 75737b59ef0SOliver O'Halloran pnv_pci_sriov_disable(pdev); 75837b59ef0SOliver O'Halloran 75937b59ef0SOliver O'Halloran /* Release PCI data */ 76037b59ef0SOliver O'Halloran remove_sriov_vf_pdns(pdev); 76137b59ef0SOliver O'Halloran return 0; 76237b59ef0SOliver O'Halloran } 76337b59ef0SOliver O'Halloran 76437b59ef0SOliver O'Halloran int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 76537b59ef0SOliver O'Halloran { 76637b59ef0SOliver O'Halloran /* Allocate PCI data */ 76737b59ef0SOliver O'Halloran add_sriov_vf_pdns(pdev); 76837b59ef0SOliver O'Halloran 76937b59ef0SOliver O'Halloran return pnv_pci_sriov_enable(pdev, num_vfs); 77037b59ef0SOliver O'Halloran } 771