1ad9add52SOliver O'Halloran // SPDX-License-Identifier: GPL-2.0-or-later 237b59ef0SOliver O'Halloran 337b59ef0SOliver O'Halloran #include <linux/kernel.h> 437b59ef0SOliver O'Halloran #include <linux/ioport.h> 537b59ef0SOliver O'Halloran #include <linux/bitmap.h> 637b59ef0SOliver O'Halloran #include <linux/pci.h> 737b59ef0SOliver O'Halloran 837b59ef0SOliver O'Halloran #include <asm/opal.h> 937b59ef0SOliver O'Halloran 1037b59ef0SOliver O'Halloran #include "pci.h" 1137b59ef0SOliver O'Halloran 1237b59ef0SOliver O'Halloran /* for pci_dev_is_added() */ 1337b59ef0SOliver O'Halloran #include "../../../../drivers/pci/pci.h" 1437b59ef0SOliver O'Halloran 15ff79e11aSOliver O'Halloran /* 16ff79e11aSOliver O'Halloran * The majority of the complexity in supporting SR-IOV on PowerNV comes from 17ff79e11aSOliver O'Halloran * the need to put the MMIO space for each VF into a separate PE. Internally 18ff79e11aSOliver O'Halloran * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table". 19ff79e11aSOliver O'Halloran * The MBT historically only applied to the 64bit MMIO window of the PHB 20ff79e11aSOliver O'Halloran * so it's common to see it referred to as the "M64BT". 21ff79e11aSOliver O'Halloran * 22ff79e11aSOliver O'Halloran * An MBT entry stores the mapped range as an <base>,<mask> pair. This forces 23ff79e11aSOliver O'Halloran * the address range that we want to map to be power-of-two sized and aligned. 24ff79e11aSOliver O'Halloran * For conventional PCI devices this isn't really an issue since PCI device BARs 25ff79e11aSOliver O'Halloran * have the same requirement. 26ff79e11aSOliver O'Halloran * 27ff79e11aSOliver O'Halloran * For a SR-IOV BAR things are a little more awkward since size and alignment 28ff79e11aSOliver O'Halloran * are not coupled. The alignment is set based on the the per-VF BAR size, but 29ff79e11aSOliver O'Halloran * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs 30ff79e11aSOliver O'Halloran * isn't necessarily a power of two, so neither is the total size. To fix that 31ff79e11aSOliver O'Halloran * we need to finesse (read: hack) the Linux BAR allocator so that it will 32ff79e11aSOliver O'Halloran * allocate the SR-IOV BARs in a way that lets us map them using the MBT. 33ff79e11aSOliver O'Halloran * 34ff79e11aSOliver O'Halloran * The changes to size and alignment that we need to do depend on the "mode" 35ff79e11aSOliver O'Halloran * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above, 36ff79e11aSOliver O'Halloran * so as a baseline we can assume that we have the following BAR modes 37ff79e11aSOliver O'Halloran * available: 38ff79e11aSOliver O'Halloran * 39ff79e11aSOliver O'Halloran * NB: $PE_COUNT is the number of PEs that the PHB supports. 40ff79e11aSOliver O'Halloran * 41ff79e11aSOliver O'Halloran * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized 42ff79e11aSOliver O'Halloran * segments. The n'th segment is mapped to the n'th PE. 43ff79e11aSOliver O'Halloran * b) An un-segmented BAR that maps the whole address range to a specific PE. 44ff79e11aSOliver O'Halloran * 45ff79e11aSOliver O'Halloran * 46ff79e11aSOliver O'Halloran * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR 47ff79e11aSOliver O'Halloran * For comparison b) requires one entry per-VF per-BAR, or: 48ff79e11aSOliver O'Halloran * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment 49ff79e11aSOliver O'Halloran * to equal the size of the per-VF BAR area. So: 50ff79e11aSOliver O'Halloran * 51ff79e11aSOliver O'Halloran * new_size = per-vf-size * number-of-PEs 52ff79e11aSOliver O'Halloran * 53ff79e11aSOliver O'Halloran * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size 54ff79e11aSOliver O'Halloran * to "new_size", calculated above. Implementing this is a convoluted process 55ff79e11aSOliver O'Halloran * which requires several hooks in the PCI core: 56ff79e11aSOliver O'Halloran * 57ff79e11aSOliver O'Halloran * 1. In pcibios_add_device() we call pnv_pci_ioda_fixup_iov(). 58ff79e11aSOliver O'Halloran * 59ff79e11aSOliver O'Halloran * At this point the device has been probed and the device's BARs are sized, 60ff79e11aSOliver O'Halloran * but no resource allocations have been done. The SR-IOV BARs are sized 61ff79e11aSOliver O'Halloran * based on the maximum number of VFs supported by the device and we need 62ff79e11aSOliver O'Halloran * to increase that to new_size. 63ff79e11aSOliver O'Halloran * 64ff79e11aSOliver O'Halloran * 2. Later, when Linux actually assigns resources it tries to make the resource 65ff79e11aSOliver O'Halloran * allocations for each PCI bus as compact as possible. As a part of that it 66ff79e11aSOliver O'Halloran * sorts the BARs on a bus by their required alignment, which is calculated 67ff79e11aSOliver O'Halloran * using pci_resource_alignment(). 68ff79e11aSOliver O'Halloran * 69ff79e11aSOliver O'Halloran * For IOV resources this goes: 70ff79e11aSOliver O'Halloran * pci_resource_alignment() 71ff79e11aSOliver O'Halloran * pci_sriov_resource_alignment() 72ff79e11aSOliver O'Halloran * pcibios_sriov_resource_alignment() 73ff79e11aSOliver O'Halloran * pnv_pci_iov_resource_alignment() 74ff79e11aSOliver O'Halloran * 75ff79e11aSOliver O'Halloran * Our hook overrides the default alignment, equal to the per-vf-size, with 76ff79e11aSOliver O'Halloran * new_size computed above. 77ff79e11aSOliver O'Halloran * 78ff79e11aSOliver O'Halloran * 3. When userspace enables VFs for a device: 79ff79e11aSOliver O'Halloran * 80ff79e11aSOliver O'Halloran * sriov_enable() 81ff79e11aSOliver O'Halloran * pcibios_sriov_enable() 82ff79e11aSOliver O'Halloran * pnv_pcibios_sriov_enable() 83ff79e11aSOliver O'Halloran * 84ff79e11aSOliver O'Halloran * This is where we actually allocate PE numbers for each VF and setup the 85ff79e11aSOliver O'Halloran * MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena" 86ff79e11aSOliver O'Halloran * where each MBT segment is equal in size to the VF BAR so we can shift 87ff79e11aSOliver O'Halloran * around the actual SR-IOV BAR location within this arena. We need this 88ff79e11aSOliver O'Halloran * ability because the PE space is shared by all devices on the same PHB. 89ff79e11aSOliver O'Halloran * When using mode a) described above segment 0 in maps to PE#0 which might 90ff79e11aSOliver O'Halloran * be already being used by another device on the PHB. 91ff79e11aSOliver O'Halloran * 92ff79e11aSOliver O'Halloran * As a result we need allocate a contigious range of PE numbers, then shift 93ff79e11aSOliver O'Halloran * the address programmed into the SR-IOV BAR of the PF so that the address 94ff79e11aSOliver O'Halloran * of VF0 matches up with the segment corresponding to the first allocated 95ff79e11aSOliver O'Halloran * PE number. This is handled in pnv_pci_vf_resource_shift(). 96ff79e11aSOliver O'Halloran * 97ff79e11aSOliver O'Halloran * Once all that is done we return to the PCI core which then enables VFs, 98ff79e11aSOliver O'Halloran * scans them and creates pci_devs for each. The init process for a VF is 99ff79e11aSOliver O'Halloran * largely the same as a normal device, but the VF is inserted into the IODA 100ff79e11aSOliver O'Halloran * PE that we allocated for it rather than the PE associated with the bus. 101ff79e11aSOliver O'Halloran * 102ff79e11aSOliver O'Halloran * 4. When userspace disables VFs we unwind the above in 103ff79e11aSOliver O'Halloran * pnv_pcibios_sriov_disable(). Fortunately this is relatively simple since 104ff79e11aSOliver O'Halloran * we don't need to validate anything, just tear down the mappings and 105ff79e11aSOliver O'Halloran * move SR-IOV resource back to its "proper" location. 106ff79e11aSOliver O'Halloran * 107ff79e11aSOliver O'Halloran * That's how mode a) works. In theory mode b) (single PE mapping) is less work 108ff79e11aSOliver O'Halloran * since we can map each individual VF with a separate BAR. However, there's a 109ff79e11aSOliver O'Halloran * few limitations: 110ff79e11aSOliver O'Halloran * 111ff79e11aSOliver O'Halloran * 1) For IODA2 mode b) has a minimum alignment requirement of 32MB. This makes 112ff79e11aSOliver O'Halloran * it only usable for devices with very large per-VF BARs. Such devices are 113ff79e11aSOliver O'Halloran * similar to Big Foot. They definitely exist, but I've never seen one. 114ff79e11aSOliver O'Halloran * 115ff79e11aSOliver O'Halloran * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only 116ff79e11aSOliver O'Halloran * 16 total and some are needed for. Most SR-IOV capable network cards can support 117ff79e11aSOliver O'Halloran * more than 16 VFs on each port. 118ff79e11aSOliver O'Halloran * 119ff79e11aSOliver O'Halloran * We use b) when using a) would use more than 1/4 of the entire 64 bit MMIO 120ff79e11aSOliver O'Halloran * window of the PHB. 121ff79e11aSOliver O'Halloran * 122ff79e11aSOliver O'Halloran * 123ff79e11aSOliver O'Halloran * 124ff79e11aSOliver O'Halloran * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It 125ff79e11aSOliver O'Halloran * allowed the MBT to map 32bit MMIO space in addition to 64bit which allows 126ff79e11aSOliver O'Halloran * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since 127ff79e11aSOliver O'Halloran * the Linux BAR allocation will place any BAR marked as non-prefetchable into 128ff79e11aSOliver O'Halloran * the non-prefetchable bridge window, which is 32bit only. It also added two 129ff79e11aSOliver O'Halloran * new modes: 130ff79e11aSOliver O'Halloran * 131ff79e11aSOliver O'Halloran * c) A segmented BAR similar to a), but each segment can be individually 132ff79e11aSOliver O'Halloran * mapped to any PE. This is matches how the 32bit MMIO window worked on 133ff79e11aSOliver O'Halloran * IODA1&2. 134ff79e11aSOliver O'Halloran * 135ff79e11aSOliver O'Halloran * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a), 136ff79e11aSOliver O'Halloran * but with fewer segments and configurable base PE. 137ff79e11aSOliver O'Halloran * 138ff79e11aSOliver O'Halloran * i.e. The n'th segment maps to the (n + base)'th PE. 139ff79e11aSOliver O'Halloran * 140ff79e11aSOliver O'Halloran * The base PE is also required to be a multiple of the window size. 141ff79e11aSOliver O'Halloran * 142ff79e11aSOliver O'Halloran * Unfortunately, the OPAL API doesn't currently (as of skiboot v6.6) allow us 143ff79e11aSOliver O'Halloran * to exploit any of the IODA3 features. 144ff79e11aSOliver O'Halloran */ 14537b59ef0SOliver O'Halloran 14637b59ef0SOliver O'Halloran static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) 14737b59ef0SOliver O'Halloran { 14837b59ef0SOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 14937b59ef0SOliver O'Halloran const resource_size_t gate = phb->ioda.m64_segsize >> 2; 15037b59ef0SOliver O'Halloran struct resource *res; 15137b59ef0SOliver O'Halloran int i; 15237b59ef0SOliver O'Halloran resource_size_t size, total_vf_bar_sz; 15337b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 15437b59ef0SOliver O'Halloran int mul, total_vfs; 15537b59ef0SOliver O'Halloran 15637b59ef0SOliver O'Halloran iov = kzalloc(sizeof(*iov), GFP_KERNEL); 15737b59ef0SOliver O'Halloran if (!iov) 158fac248f8SOliver O'Halloran goto disable_iov; 15937b59ef0SOliver O'Halloran pdev->dev.archdata.iov_data = iov; 16037b59ef0SOliver O'Halloran 16137b59ef0SOliver O'Halloran total_vfs = pci_sriov_get_totalvfs(pdev); 16237b59ef0SOliver O'Halloran mul = phb->ioda.total_pe_num; 16337b59ef0SOliver O'Halloran total_vf_bar_sz = 0; 16437b59ef0SOliver O'Halloran 16537b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 16637b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES]; 16737b59ef0SOliver O'Halloran if (!res->flags || res->parent) 16837b59ef0SOliver O'Halloran continue; 16937b59ef0SOliver O'Halloran if (!pnv_pci_is_m64_flags(res->flags)) { 17037b59ef0SOliver O'Halloran dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n", 17137b59ef0SOliver O'Halloran i, res); 172fac248f8SOliver O'Halloran goto disable_iov; 17337b59ef0SOliver O'Halloran } 17437b59ef0SOliver O'Halloran 17537b59ef0SOliver O'Halloran total_vf_bar_sz += pci_iov_resource_size(pdev, 17637b59ef0SOliver O'Halloran i + PCI_IOV_RESOURCES); 17737b59ef0SOliver O'Halloran 17837b59ef0SOliver O'Halloran /* 17937b59ef0SOliver O'Halloran * If bigger than quarter of M64 segment size, just round up 18037b59ef0SOliver O'Halloran * power of two. 18137b59ef0SOliver O'Halloran * 18237b59ef0SOliver O'Halloran * Generally, one M64 BAR maps one IOV BAR. To avoid conflict 18337b59ef0SOliver O'Halloran * with other devices, IOV BAR size is expanded to be 18437b59ef0SOliver O'Halloran * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 18537b59ef0SOliver O'Halloran * segment size , the expanded size would equal to half of the 18637b59ef0SOliver O'Halloran * whole M64 space size, which will exhaust the M64 Space and 18737b59ef0SOliver O'Halloran * limit the system flexibility. This is a design decision to 18837b59ef0SOliver O'Halloran * set the boundary to quarter of the M64 segment size. 18937b59ef0SOliver O'Halloran */ 19037b59ef0SOliver O'Halloran if (total_vf_bar_sz > gate) { 19137b59ef0SOliver O'Halloran mul = roundup_pow_of_two(total_vfs); 19237b59ef0SOliver O'Halloran dev_info(&pdev->dev, 19337b59ef0SOliver O'Halloran "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", 19437b59ef0SOliver O'Halloran total_vf_bar_sz, gate, mul); 19537b59ef0SOliver O'Halloran iov->m64_single_mode = true; 19637b59ef0SOliver O'Halloran break; 19737b59ef0SOliver O'Halloran } 19837b59ef0SOliver O'Halloran } 19937b59ef0SOliver O'Halloran 20037b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 20137b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES]; 20237b59ef0SOliver O'Halloran if (!res->flags || res->parent) 20337b59ef0SOliver O'Halloran continue; 20437b59ef0SOliver O'Halloran 20537b59ef0SOliver O'Halloran size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); 20637b59ef0SOliver O'Halloran /* 20737b59ef0SOliver O'Halloran * On PHB3, the minimum size alignment of M64 BAR in single 20837b59ef0SOliver O'Halloran * mode is 32MB. 20937b59ef0SOliver O'Halloran */ 21037b59ef0SOliver O'Halloran if (iov->m64_single_mode && (size < SZ_32M)) 211fac248f8SOliver O'Halloran goto disable_iov; 212fac248f8SOliver O'Halloran 21337b59ef0SOliver O'Halloran dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); 21437b59ef0SOliver O'Halloran res->end = res->start + size * mul - 1; 21537b59ef0SOliver O'Halloran dev_dbg(&pdev->dev, " %pR\n", res); 21637b59ef0SOliver O'Halloran dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", 21737b59ef0SOliver O'Halloran i, res, mul); 21837b59ef0SOliver O'Halloran } 21937b59ef0SOliver O'Halloran iov->vfs_expanded = mul; 22037b59ef0SOliver O'Halloran 22137b59ef0SOliver O'Halloran return; 22237b59ef0SOliver O'Halloran 223fac248f8SOliver O'Halloran disable_iov: 224fac248f8SOliver O'Halloran /* Save ourselves some MMIO space by disabling the unusable BARs */ 22537b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 22637b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES]; 22737b59ef0SOliver O'Halloran res->flags = 0; 22837b59ef0SOliver O'Halloran res->end = res->start - 1; 22937b59ef0SOliver O'Halloran } 23037b59ef0SOliver O'Halloran 23137b59ef0SOliver O'Halloran pdev->dev.archdata.iov_data = NULL; 23237b59ef0SOliver O'Halloran kfree(iov); 23337b59ef0SOliver O'Halloran } 23437b59ef0SOliver O'Halloran 23537b59ef0SOliver O'Halloran void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev) 23637b59ef0SOliver O'Halloran { 23737b59ef0SOliver O'Halloran if (WARN_ON(pci_dev_is_added(pdev))) 23837b59ef0SOliver O'Halloran return; 23937b59ef0SOliver O'Halloran 24037b59ef0SOliver O'Halloran if (pdev->is_virtfn) { 24137b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev); 24237b59ef0SOliver O'Halloran 24337b59ef0SOliver O'Halloran /* 24437b59ef0SOliver O'Halloran * VF PEs are single-device PEs so their pdev pointer needs to 24537b59ef0SOliver O'Halloran * be set. The pdev doesn't exist when the PE is allocated (in 24637b59ef0SOliver O'Halloran * (pcibios_sriov_enable()) so we fix it up here. 24737b59ef0SOliver O'Halloran */ 24837b59ef0SOliver O'Halloran pe->pdev = pdev; 24937b59ef0SOliver O'Halloran WARN_ON(!(pe->flags & PNV_IODA_PE_VF)); 25037b59ef0SOliver O'Halloran } else if (pdev->is_physfn) { 25137b59ef0SOliver O'Halloran /* 25237b59ef0SOliver O'Halloran * For PFs adjust their allocated IOV resources to match what 25337b59ef0SOliver O'Halloran * the PHB can support using it's M64 BAR table. 25437b59ef0SOliver O'Halloran */ 25537b59ef0SOliver O'Halloran pnv_pci_ioda_fixup_iov_resources(pdev); 25637b59ef0SOliver O'Halloran } 25737b59ef0SOliver O'Halloran } 25837b59ef0SOliver O'Halloran 25937b59ef0SOliver O'Halloran resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, 26037b59ef0SOliver O'Halloran int resno) 26137b59ef0SOliver O'Halloran { 26237b59ef0SOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); 26337b59ef0SOliver O'Halloran struct pnv_iov_data *iov = pnv_iov_get(pdev); 26437b59ef0SOliver O'Halloran resource_size_t align; 26537b59ef0SOliver O'Halloran 26637b59ef0SOliver O'Halloran /* 26737b59ef0SOliver O'Halloran * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the 26837b59ef0SOliver O'Halloran * SR-IOV. While from hardware perspective, the range mapped by M64 26937b59ef0SOliver O'Halloran * BAR should be size aligned. 27037b59ef0SOliver O'Halloran * 27137b59ef0SOliver O'Halloran * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra 27237b59ef0SOliver O'Halloran * powernv-specific hardware restriction is gone. But if just use the 27337b59ef0SOliver O'Halloran * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with 27437b59ef0SOliver O'Halloran * in one segment of M64 #15, which introduces the PE conflict between 27537b59ef0SOliver O'Halloran * PF and VF. Based on this, the minimum alignment of an IOV BAR is 27637b59ef0SOliver O'Halloran * m64_segsize. 27737b59ef0SOliver O'Halloran * 27837b59ef0SOliver O'Halloran * This function returns the total IOV BAR size if M64 BAR is in 27937b59ef0SOliver O'Halloran * Shared PE mode or just VF BAR size if not. 28037b59ef0SOliver O'Halloran * If the M64 BAR is in Single PE mode, return the VF BAR size or 28137b59ef0SOliver O'Halloran * M64 segment size if IOV BAR size is less. 28237b59ef0SOliver O'Halloran */ 28337b59ef0SOliver O'Halloran align = pci_iov_resource_size(pdev, resno); 28437b59ef0SOliver O'Halloran 28537b59ef0SOliver O'Halloran /* 28637b59ef0SOliver O'Halloran * iov can be null if we have an SR-IOV device with IOV BAR that can't 28737b59ef0SOliver O'Halloran * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch). 28837b59ef0SOliver O'Halloran * In that case we don't allow VFs to be enabled so just return the 28937b59ef0SOliver O'Halloran * default alignment. 29037b59ef0SOliver O'Halloran */ 29137b59ef0SOliver O'Halloran if (!iov) 29237b59ef0SOliver O'Halloran return align; 29337b59ef0SOliver O'Halloran if (!iov->vfs_expanded) 29437b59ef0SOliver O'Halloran return align; 29537b59ef0SOliver O'Halloran if (iov->m64_single_mode) 29637b59ef0SOliver O'Halloran return max(align, (resource_size_t)phb->ioda.m64_segsize); 29737b59ef0SOliver O'Halloran 29837b59ef0SOliver O'Halloran return iov->vfs_expanded * align; 29937b59ef0SOliver O'Halloran } 30037b59ef0SOliver O'Halloran 30137b59ef0SOliver O'Halloran static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) 30237b59ef0SOliver O'Halloran { 30337b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 30437b59ef0SOliver O'Halloran struct pnv_phb *phb; 305ad9add52SOliver O'Halloran int window_id; 30637b59ef0SOliver O'Halloran 30737b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 30837b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 30937b59ef0SOliver O'Halloran 310ad9add52SOliver O'Halloran for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) { 31137b59ef0SOliver O'Halloran opal_pci_phb_mmio_enable(phb->opal_id, 312ad9add52SOliver O'Halloran OPAL_M64_WINDOW_TYPE, 313ad9add52SOliver O'Halloran window_id, 314ad9add52SOliver O'Halloran 0); 315ad9add52SOliver O'Halloran 316ad9add52SOliver O'Halloran clear_bit(window_id, &phb->ioda.m64_bar_alloc); 31737b59ef0SOliver O'Halloran } 31837b59ef0SOliver O'Halloran 31937b59ef0SOliver O'Halloran return 0; 32037b59ef0SOliver O'Halloran } 32137b59ef0SOliver O'Halloran 322a610d35cSOliver O'Halloran 323a610d35cSOliver O'Halloran /* 324a610d35cSOliver O'Halloran * PHB3 and beyond support segmented windows. The window's address range 325a610d35cSOliver O'Halloran * is subdivided into phb->ioda.total_pe_num segments and there's a 1-1 326a610d35cSOliver O'Halloran * mapping between PEs and segments. 327a610d35cSOliver O'Halloran */ 328a610d35cSOliver O'Halloran static int64_t pnv_ioda_map_m64_segmented(struct pnv_phb *phb, 329a610d35cSOliver O'Halloran int window_id, 330a610d35cSOliver O'Halloran resource_size_t start, 331a610d35cSOliver O'Halloran resource_size_t size) 332a610d35cSOliver O'Halloran { 333a610d35cSOliver O'Halloran int64_t rc; 334a610d35cSOliver O'Halloran 335a610d35cSOliver O'Halloran rc = opal_pci_set_phb_mem_window(phb->opal_id, 336a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE, 337a610d35cSOliver O'Halloran window_id, 338a610d35cSOliver O'Halloran start, 339a610d35cSOliver O'Halloran 0, /* unused */ 340a610d35cSOliver O'Halloran size); 341a610d35cSOliver O'Halloran if (rc) 342a610d35cSOliver O'Halloran goto out; 343a610d35cSOliver O'Halloran 344a610d35cSOliver O'Halloran rc = opal_pci_phb_mmio_enable(phb->opal_id, 345a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE, 346a610d35cSOliver O'Halloran window_id, 347a610d35cSOliver O'Halloran OPAL_ENABLE_M64_SPLIT); 348a610d35cSOliver O'Halloran out: 349a610d35cSOliver O'Halloran if (rc) 350a610d35cSOliver O'Halloran pr_err("Failed to map M64 window #%d: %lld\n", window_id, rc); 351a610d35cSOliver O'Halloran 352a610d35cSOliver O'Halloran return rc; 353a610d35cSOliver O'Halloran } 354a610d35cSOliver O'Halloran 355a610d35cSOliver O'Halloran static int64_t pnv_ioda_map_m64_single(struct pnv_phb *phb, 356a610d35cSOliver O'Halloran int pe_num, 357a610d35cSOliver O'Halloran int window_id, 358a610d35cSOliver O'Halloran resource_size_t start, 359a610d35cSOliver O'Halloran resource_size_t size) 360a610d35cSOliver O'Halloran { 361a610d35cSOliver O'Halloran int64_t rc; 362a610d35cSOliver O'Halloran 363a610d35cSOliver O'Halloran /* 364a610d35cSOliver O'Halloran * The API for setting up m64 mmio windows seems to have been designed 365a610d35cSOliver O'Halloran * with P7-IOC in mind. For that chip each M64 BAR (window) had a fixed 366a610d35cSOliver O'Halloran * split of 8 equally sized segments each of which could individually 367a610d35cSOliver O'Halloran * assigned to a PE. 368a610d35cSOliver O'Halloran * 369a610d35cSOliver O'Halloran * The problem with this is that the API doesn't have any way to 370a610d35cSOliver O'Halloran * communicate the number of segments we want on a BAR. This wasn't 371a610d35cSOliver O'Halloran * a problem for p7-ioc since you didn't have a choice, but the 372a610d35cSOliver O'Halloran * single PE windows added in PHB3 don't map cleanly to this API. 373a610d35cSOliver O'Halloran * 374a610d35cSOliver O'Halloran * As a result we've got this slightly awkward process where we 375a610d35cSOliver O'Halloran * call opal_pci_map_pe_mmio_window() to put the single in single 376a610d35cSOliver O'Halloran * PE mode, and set the PE for the window before setting the address 377a610d35cSOliver O'Halloran * bounds. We need to do it this way because the single PE windows 378a610d35cSOliver O'Halloran * for PHB3 have different alignment requirements on PHB3. 379a610d35cSOliver O'Halloran */ 380a610d35cSOliver O'Halloran rc = opal_pci_map_pe_mmio_window(phb->opal_id, 381a610d35cSOliver O'Halloran pe_num, 382a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE, 383a610d35cSOliver O'Halloran window_id, 384a610d35cSOliver O'Halloran 0); 385a610d35cSOliver O'Halloran if (rc) 386a610d35cSOliver O'Halloran goto out; 387a610d35cSOliver O'Halloran 388a610d35cSOliver O'Halloran /* 389a610d35cSOliver O'Halloran * NB: In single PE mode the window needs to be aligned to 32MB 390a610d35cSOliver O'Halloran */ 391a610d35cSOliver O'Halloran rc = opal_pci_set_phb_mem_window(phb->opal_id, 392a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE, 393a610d35cSOliver O'Halloran window_id, 394a610d35cSOliver O'Halloran start, 395a610d35cSOliver O'Halloran 0, /* ignored by FW, m64 is 1-1 */ 396a610d35cSOliver O'Halloran size); 397a610d35cSOliver O'Halloran if (rc) 398a610d35cSOliver O'Halloran goto out; 399a610d35cSOliver O'Halloran 400a610d35cSOliver O'Halloran /* 401a610d35cSOliver O'Halloran * Now actually enable it. We specified the BAR should be in "non-split" 402a610d35cSOliver O'Halloran * mode so FW will validate that the BAR is in single PE mode. 403a610d35cSOliver O'Halloran */ 404a610d35cSOliver O'Halloran rc = opal_pci_phb_mmio_enable(phb->opal_id, 405a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE, 406a610d35cSOliver O'Halloran window_id, 407a610d35cSOliver O'Halloran OPAL_ENABLE_M64_NON_SPLIT); 408a610d35cSOliver O'Halloran out: 409a610d35cSOliver O'Halloran if (rc) 410a610d35cSOliver O'Halloran pr_err("Error mapping single PE BAR\n"); 411a610d35cSOliver O'Halloran 412a610d35cSOliver O'Halloran return rc; 413a610d35cSOliver O'Halloran } 414a610d35cSOliver O'Halloran 41537b59ef0SOliver O'Halloran static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) 41637b59ef0SOliver O'Halloran { 41737b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 41837b59ef0SOliver O'Halloran struct pnv_phb *phb; 41937b59ef0SOliver O'Halloran unsigned int win; 42037b59ef0SOliver O'Halloran struct resource *res; 42137b59ef0SOliver O'Halloran int i, j; 42237b59ef0SOliver O'Halloran int64_t rc; 42337b59ef0SOliver O'Halloran int total_vfs; 42437b59ef0SOliver O'Halloran resource_size_t size, start; 42537b59ef0SOliver O'Halloran int m64_bars; 42637b59ef0SOliver O'Halloran 42737b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 42837b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 42937b59ef0SOliver O'Halloran total_vfs = pci_sriov_get_totalvfs(pdev); 43037b59ef0SOliver O'Halloran 43137b59ef0SOliver O'Halloran if (iov->m64_single_mode) 43237b59ef0SOliver O'Halloran m64_bars = num_vfs; 43337b59ef0SOliver O'Halloran else 43437b59ef0SOliver O'Halloran m64_bars = 1; 43537b59ef0SOliver O'Halloran 43637b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 43737b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES]; 43837b59ef0SOliver O'Halloran if (!res->flags || !res->parent) 43937b59ef0SOliver O'Halloran continue; 44037b59ef0SOliver O'Halloran 44137b59ef0SOliver O'Halloran for (j = 0; j < m64_bars; j++) { 442ad9add52SOliver O'Halloran 443ad9add52SOliver O'Halloran /* allocate a window ID for this BAR */ 44437b59ef0SOliver O'Halloran do { 44537b59ef0SOliver O'Halloran win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, 44637b59ef0SOliver O'Halloran phb->ioda.m64_bar_idx + 1, 0); 44737b59ef0SOliver O'Halloran 44837b59ef0SOliver O'Halloran if (win >= phb->ioda.m64_bar_idx + 1) 44937b59ef0SOliver O'Halloran goto m64_failed; 45037b59ef0SOliver O'Halloran } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); 451ad9add52SOliver O'Halloran set_bit(win, iov->used_m64_bar_mask); 45237b59ef0SOliver O'Halloran 453a610d35cSOliver O'Halloran 45437b59ef0SOliver O'Halloran if (iov->m64_single_mode) { 455d29a2488SOliver O'Halloran int pe_num = iov->vf_pe_arr[j].pe_number; 456d29a2488SOliver O'Halloran 45737b59ef0SOliver O'Halloran size = pci_iov_resource_size(pdev, 45837b59ef0SOliver O'Halloran PCI_IOV_RESOURCES + i); 45937b59ef0SOliver O'Halloran start = res->start + size * j; 460a610d35cSOliver O'Halloran rc = pnv_ioda_map_m64_single(phb, win, 461d29a2488SOliver O'Halloran pe_num, 462a610d35cSOliver O'Halloran start, 463a610d35cSOliver O'Halloran size); 46437b59ef0SOliver O'Halloran } else { 46537b59ef0SOliver O'Halloran size = resource_size(res); 46637b59ef0SOliver O'Halloran start = res->start; 46737b59ef0SOliver O'Halloran 468a610d35cSOliver O'Halloran rc = pnv_ioda_map_m64_segmented(phb, win, start, 46937b59ef0SOliver O'Halloran size); 470a610d35cSOliver O'Halloran } 47137b59ef0SOliver O'Halloran 47237b59ef0SOliver O'Halloran if (rc != OPAL_SUCCESS) { 47337b59ef0SOliver O'Halloran dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", 47437b59ef0SOliver O'Halloran win, rc); 47537b59ef0SOliver O'Halloran goto m64_failed; 47637b59ef0SOliver O'Halloran } 47737b59ef0SOliver O'Halloran } 47837b59ef0SOliver O'Halloran } 47937b59ef0SOliver O'Halloran return 0; 48037b59ef0SOliver O'Halloran 48137b59ef0SOliver O'Halloran m64_failed: 48237b59ef0SOliver O'Halloran pnv_pci_vf_release_m64(pdev, num_vfs); 48337b59ef0SOliver O'Halloran return -EBUSY; 48437b59ef0SOliver O'Halloran } 48537b59ef0SOliver O'Halloran 48637b59ef0SOliver O'Halloran static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) 48737b59ef0SOliver O'Halloran { 48837b59ef0SOliver O'Halloran struct pnv_phb *phb; 48937b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe, *pe_n; 49037b59ef0SOliver O'Halloran 49137b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 49237b59ef0SOliver O'Halloran 49337b59ef0SOliver O'Halloran if (!pdev->is_physfn) 49437b59ef0SOliver O'Halloran return; 49537b59ef0SOliver O'Halloran 49637b59ef0SOliver O'Halloran /* FIXME: Use pnv_ioda_release_pe()? */ 49737b59ef0SOliver O'Halloran list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { 49837b59ef0SOliver O'Halloran if (pe->parent_dev != pdev) 49937b59ef0SOliver O'Halloran continue; 50037b59ef0SOliver O'Halloran 50137b59ef0SOliver O'Halloran pnv_pci_ioda2_release_pe_dma(pe); 50237b59ef0SOliver O'Halloran 50337b59ef0SOliver O'Halloran /* Remove from list */ 50437b59ef0SOliver O'Halloran mutex_lock(&phb->ioda.pe_list_mutex); 50537b59ef0SOliver O'Halloran list_del(&pe->list); 50637b59ef0SOliver O'Halloran mutex_unlock(&phb->ioda.pe_list_mutex); 50737b59ef0SOliver O'Halloran 50837b59ef0SOliver O'Halloran pnv_ioda_deconfigure_pe(phb, pe); 50937b59ef0SOliver O'Halloran 51037b59ef0SOliver O'Halloran pnv_ioda_free_pe(pe); 51137b59ef0SOliver O'Halloran } 51237b59ef0SOliver O'Halloran } 51337b59ef0SOliver O'Halloran 51437b59ef0SOliver O'Halloran static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) 51537b59ef0SOliver O'Halloran { 51637b59ef0SOliver O'Halloran struct resource *res, res2; 51737b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 51837b59ef0SOliver O'Halloran resource_size_t size; 51937b59ef0SOliver O'Halloran u16 num_vfs; 52037b59ef0SOliver O'Halloran int i; 52137b59ef0SOliver O'Halloran 52237b59ef0SOliver O'Halloran if (!dev->is_physfn) 52337b59ef0SOliver O'Halloran return -EINVAL; 52437b59ef0SOliver O'Halloran iov = pnv_iov_get(dev); 52537b59ef0SOliver O'Halloran 52637b59ef0SOliver O'Halloran /* 52737b59ef0SOliver O'Halloran * "offset" is in VFs. The M64 windows are sized so that when they 52837b59ef0SOliver O'Halloran * are segmented, each segment is the same size as the IOV BAR. 52937b59ef0SOliver O'Halloran * Each segment is in a separate PE, and the high order bits of the 53037b59ef0SOliver O'Halloran * address are the PE number. Therefore, each VF's BAR is in a 53137b59ef0SOliver O'Halloran * separate PE, and changing the IOV BAR start address changes the 53237b59ef0SOliver O'Halloran * range of PEs the VFs are in. 53337b59ef0SOliver O'Halloran */ 53437b59ef0SOliver O'Halloran num_vfs = iov->num_vfs; 53537b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 53637b59ef0SOliver O'Halloran res = &dev->resource[i + PCI_IOV_RESOURCES]; 53737b59ef0SOliver O'Halloran if (!res->flags || !res->parent) 53837b59ef0SOliver O'Halloran continue; 53937b59ef0SOliver O'Halloran 54037b59ef0SOliver O'Halloran /* 54137b59ef0SOliver O'Halloran * The actual IOV BAR range is determined by the start address 54237b59ef0SOliver O'Halloran * and the actual size for num_vfs VFs BAR. This check is to 54337b59ef0SOliver O'Halloran * make sure that after shifting, the range will not overlap 54437b59ef0SOliver O'Halloran * with another device. 54537b59ef0SOliver O'Halloran */ 54637b59ef0SOliver O'Halloran size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 54737b59ef0SOliver O'Halloran res2.flags = res->flags; 54837b59ef0SOliver O'Halloran res2.start = res->start + (size * offset); 54937b59ef0SOliver O'Halloran res2.end = res2.start + (size * num_vfs) - 1; 55037b59ef0SOliver O'Halloran 55137b59ef0SOliver O'Halloran if (res2.end > res->end) { 55237b59ef0SOliver O'Halloran dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", 55337b59ef0SOliver O'Halloran i, &res2, res, num_vfs, offset); 55437b59ef0SOliver O'Halloran return -EBUSY; 55537b59ef0SOliver O'Halloran } 55637b59ef0SOliver O'Halloran } 55737b59ef0SOliver O'Halloran 55837b59ef0SOliver O'Halloran /* 55937b59ef0SOliver O'Halloran * Since M64 BAR shares segments among all possible 256 PEs, 56037b59ef0SOliver O'Halloran * we have to shift the beginning of PF IOV BAR to make it start from 56137b59ef0SOliver O'Halloran * the segment which belongs to the PE number assigned to the first VF. 56237b59ef0SOliver O'Halloran * This creates a "hole" in the /proc/iomem which could be used for 56337b59ef0SOliver O'Halloran * allocating other resources so we reserve this area below and 56437b59ef0SOliver O'Halloran * release when IOV is released. 56537b59ef0SOliver O'Halloran */ 56637b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 56737b59ef0SOliver O'Halloran res = &dev->resource[i + PCI_IOV_RESOURCES]; 56837b59ef0SOliver O'Halloran if (!res->flags || !res->parent) 56937b59ef0SOliver O'Halloran continue; 57037b59ef0SOliver O'Halloran 57137b59ef0SOliver O'Halloran size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); 57237b59ef0SOliver O'Halloran res2 = *res; 57337b59ef0SOliver O'Halloran res->start += size * offset; 57437b59ef0SOliver O'Halloran 57537b59ef0SOliver O'Halloran dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", 57637b59ef0SOliver O'Halloran i, &res2, res, (offset > 0) ? "En" : "Dis", 57737b59ef0SOliver O'Halloran num_vfs, offset); 57837b59ef0SOliver O'Halloran 57937b59ef0SOliver O'Halloran if (offset < 0) { 58037b59ef0SOliver O'Halloran devm_release_resource(&dev->dev, &iov->holes[i]); 58137b59ef0SOliver O'Halloran memset(&iov->holes[i], 0, sizeof(iov->holes[i])); 58237b59ef0SOliver O'Halloran } 58337b59ef0SOliver O'Halloran 58437b59ef0SOliver O'Halloran pci_update_resource(dev, i + PCI_IOV_RESOURCES); 58537b59ef0SOliver O'Halloran 58637b59ef0SOliver O'Halloran if (offset > 0) { 58737b59ef0SOliver O'Halloran iov->holes[i].start = res2.start; 58837b59ef0SOliver O'Halloran iov->holes[i].end = res2.start + size * offset - 1; 58937b59ef0SOliver O'Halloran iov->holes[i].flags = IORESOURCE_BUS; 59037b59ef0SOliver O'Halloran iov->holes[i].name = "pnv_iov_reserved"; 59137b59ef0SOliver O'Halloran devm_request_resource(&dev->dev, res->parent, 59237b59ef0SOliver O'Halloran &iov->holes[i]); 59337b59ef0SOliver O'Halloran } 59437b59ef0SOliver O'Halloran } 59537b59ef0SOliver O'Halloran return 0; 59637b59ef0SOliver O'Halloran } 59737b59ef0SOliver O'Halloran 59837b59ef0SOliver O'Halloran static void pnv_pci_sriov_disable(struct pci_dev *pdev) 59937b59ef0SOliver O'Halloran { 600d29a2488SOliver O'Halloran u16 num_vfs, base_pe; 60137b59ef0SOliver O'Halloran struct pnv_phb *phb; 60237b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 60337b59ef0SOliver O'Halloran 60437b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 60537b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 60637b59ef0SOliver O'Halloran num_vfs = iov->num_vfs; 607d29a2488SOliver O'Halloran base_pe = iov->vf_pe_arr[0].pe_number; 60837b59ef0SOliver O'Halloran 60937b59ef0SOliver O'Halloran /* Release VF PEs */ 61037b59ef0SOliver O'Halloran pnv_ioda_release_vf_PE(pdev); 61137b59ef0SOliver O'Halloran 61237b59ef0SOliver O'Halloran if (phb->type == PNV_PHB_IODA2) { 61337b59ef0SOliver O'Halloran if (!iov->m64_single_mode) 614d29a2488SOliver O'Halloran pnv_pci_vf_resource_shift(pdev, -base_pe); 61537b59ef0SOliver O'Halloran 61637b59ef0SOliver O'Halloran /* Release M64 windows */ 61737b59ef0SOliver O'Halloran pnv_pci_vf_release_m64(pdev, num_vfs); 61837b59ef0SOliver O'Halloran } 61937b59ef0SOliver O'Halloran } 62037b59ef0SOliver O'Halloran 62137b59ef0SOliver O'Halloran static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) 62237b59ef0SOliver O'Halloran { 62337b59ef0SOliver O'Halloran struct pnv_phb *phb; 62437b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe; 62537b59ef0SOliver O'Halloran int pe_num; 62637b59ef0SOliver O'Halloran u16 vf_index; 62737b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 62837b59ef0SOliver O'Halloran struct pci_dn *pdn; 62937b59ef0SOliver O'Halloran 63037b59ef0SOliver O'Halloran if (!pdev->is_physfn) 63137b59ef0SOliver O'Halloran return; 63237b59ef0SOliver O'Halloran 63337b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 63437b59ef0SOliver O'Halloran pdn = pci_get_pdn(pdev); 63537b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 63637b59ef0SOliver O'Halloran 63737b59ef0SOliver O'Halloran /* Reserve PE for each VF */ 63837b59ef0SOliver O'Halloran for (vf_index = 0; vf_index < num_vfs; vf_index++) { 63937b59ef0SOliver O'Halloran int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); 64037b59ef0SOliver O'Halloran int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); 64137b59ef0SOliver O'Halloran struct pci_dn *vf_pdn; 64237b59ef0SOliver O'Halloran 643d29a2488SOliver O'Halloran pe = &iov->vf_pe_arr[vf_index]; 64437b59ef0SOliver O'Halloran pe->phb = phb; 64537b59ef0SOliver O'Halloran pe->flags = PNV_IODA_PE_VF; 64637b59ef0SOliver O'Halloran pe->pbus = NULL; 64737b59ef0SOliver O'Halloran pe->parent_dev = pdev; 64837b59ef0SOliver O'Halloran pe->mve_number = -1; 64937b59ef0SOliver O'Halloran pe->rid = (vf_bus << 8) | vf_devfn; 65037b59ef0SOliver O'Halloran 651d29a2488SOliver O'Halloran pe_num = pe->pe_number; 65237b59ef0SOliver O'Halloran pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", 65337b59ef0SOliver O'Halloran pci_domain_nr(pdev->bus), pdev->bus->number, 65437b59ef0SOliver O'Halloran PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); 65537b59ef0SOliver O'Halloran 65637b59ef0SOliver O'Halloran if (pnv_ioda_configure_pe(phb, pe)) { 65737b59ef0SOliver O'Halloran /* XXX What do we do here ? */ 65837b59ef0SOliver O'Halloran pnv_ioda_free_pe(pe); 65937b59ef0SOliver O'Halloran pe->pdev = NULL; 66037b59ef0SOliver O'Halloran continue; 66137b59ef0SOliver O'Halloran } 66237b59ef0SOliver O'Halloran 66337b59ef0SOliver O'Halloran /* Put PE to the list */ 66437b59ef0SOliver O'Halloran mutex_lock(&phb->ioda.pe_list_mutex); 66537b59ef0SOliver O'Halloran list_add_tail(&pe->list, &phb->ioda.pe_list); 66637b59ef0SOliver O'Halloran mutex_unlock(&phb->ioda.pe_list_mutex); 66737b59ef0SOliver O'Halloran 66837b59ef0SOliver O'Halloran /* associate this pe to it's pdn */ 66937b59ef0SOliver O'Halloran list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { 67037b59ef0SOliver O'Halloran if (vf_pdn->busno == vf_bus && 67137b59ef0SOliver O'Halloran vf_pdn->devfn == vf_devfn) { 67237b59ef0SOliver O'Halloran vf_pdn->pe_number = pe_num; 67337b59ef0SOliver O'Halloran break; 67437b59ef0SOliver O'Halloran } 67537b59ef0SOliver O'Halloran } 67637b59ef0SOliver O'Halloran 67737b59ef0SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe); 67837b59ef0SOliver O'Halloran } 67937b59ef0SOliver O'Halloran } 68037b59ef0SOliver O'Halloran 68137b59ef0SOliver O'Halloran static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 68237b59ef0SOliver O'Halloran { 683d29a2488SOliver O'Halloran struct pnv_ioda_pe *base_pe; 68437b59ef0SOliver O'Halloran struct pnv_iov_data *iov; 68537b59ef0SOliver O'Halloran struct pnv_phb *phb; 68637b59ef0SOliver O'Halloran int ret; 68737b59ef0SOliver O'Halloran u16 i; 68837b59ef0SOliver O'Halloran 68937b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus); 69037b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev); 69137b59ef0SOliver O'Halloran 69237b59ef0SOliver O'Halloran if (phb->type == PNV_PHB_IODA2) { 69337b59ef0SOliver O'Halloran if (!iov->vfs_expanded) { 69437b59ef0SOliver O'Halloran dev_info(&pdev->dev, 69537b59ef0SOliver O'Halloran "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n"); 69637b59ef0SOliver O'Halloran return -ENOSPC; 69737b59ef0SOliver O'Halloran } 69837b59ef0SOliver O'Halloran 699d29a2488SOliver O'Halloran /* allocate a contigious block of PEs for our VFs */ 700d29a2488SOliver O'Halloran base_pe = pnv_ioda_alloc_pe(phb, num_vfs); 701d29a2488SOliver O'Halloran if (!base_pe) { 702d29a2488SOliver O'Halloran pci_err(pdev, "Unable to allocate PEs for %d VFs\n", num_vfs); 70337b59ef0SOliver O'Halloran return -EBUSY; 70437b59ef0SOliver O'Halloran } 70537b59ef0SOliver O'Halloran 706d29a2488SOliver O'Halloran iov->vf_pe_arr = base_pe; 70737b59ef0SOliver O'Halloran iov->num_vfs = num_vfs; 70837b59ef0SOliver O'Halloran 70937b59ef0SOliver O'Halloran /* Assign M64 window accordingly */ 71037b59ef0SOliver O'Halloran ret = pnv_pci_vf_assign_m64(pdev, num_vfs); 71137b59ef0SOliver O'Halloran if (ret) { 71237b59ef0SOliver O'Halloran dev_info(&pdev->dev, "Not enough M64 window resources\n"); 71337b59ef0SOliver O'Halloran goto m64_failed; 71437b59ef0SOliver O'Halloran } 71537b59ef0SOliver O'Halloran 71637b59ef0SOliver O'Halloran /* 71737b59ef0SOliver O'Halloran * When using one M64 BAR to map one IOV BAR, we need to shift 71837b59ef0SOliver O'Halloran * the IOV BAR according to the PE# allocated to the VFs. 71937b59ef0SOliver O'Halloran * Otherwise, the PE# for the VF will conflict with others. 72037b59ef0SOliver O'Halloran */ 72137b59ef0SOliver O'Halloran if (!iov->m64_single_mode) { 722d29a2488SOliver O'Halloran ret = pnv_pci_vf_resource_shift(pdev, 723d29a2488SOliver O'Halloran base_pe->pe_number); 72437b59ef0SOliver O'Halloran if (ret) 725d29a2488SOliver O'Halloran goto shift_failed; 72637b59ef0SOliver O'Halloran } 72737b59ef0SOliver O'Halloran } 72837b59ef0SOliver O'Halloran 72937b59ef0SOliver O'Halloran /* Setup VF PEs */ 73037b59ef0SOliver O'Halloran pnv_ioda_setup_vf_PE(pdev, num_vfs); 73137b59ef0SOliver O'Halloran 73237b59ef0SOliver O'Halloran return 0; 73337b59ef0SOliver O'Halloran 734d29a2488SOliver O'Halloran shift_failed: 735d29a2488SOliver O'Halloran pnv_pci_vf_release_m64(pdev, num_vfs); 736d29a2488SOliver O'Halloran 73737b59ef0SOliver O'Halloran m64_failed: 738d29a2488SOliver O'Halloran for (i = 0; i < num_vfs; i++) 739d29a2488SOliver O'Halloran pnv_ioda_free_pe(&iov->vf_pe_arr[i]); 74037b59ef0SOliver O'Halloran 74137b59ef0SOliver O'Halloran return ret; 74237b59ef0SOliver O'Halloran } 74337b59ef0SOliver O'Halloran 74437b59ef0SOliver O'Halloran int pnv_pcibios_sriov_disable(struct pci_dev *pdev) 74537b59ef0SOliver O'Halloran { 74637b59ef0SOliver O'Halloran pnv_pci_sriov_disable(pdev); 74737b59ef0SOliver O'Halloran 74837b59ef0SOliver O'Halloran /* Release PCI data */ 74937b59ef0SOliver O'Halloran remove_sriov_vf_pdns(pdev); 75037b59ef0SOliver O'Halloran return 0; 75137b59ef0SOliver O'Halloran } 75237b59ef0SOliver O'Halloran 75337b59ef0SOliver O'Halloran int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 75437b59ef0SOliver O'Halloran { 75537b59ef0SOliver O'Halloran /* Allocate PCI data */ 75637b59ef0SOliver O'Halloran add_sriov_vf_pdns(pdev); 75737b59ef0SOliver O'Halloran 75837b59ef0SOliver O'Halloran return pnv_pci_sriov_enable(pdev, num_vfs); 75937b59ef0SOliver O'Halloran } 760