1ad9add52SOliver O'Halloran // SPDX-License-Identifier: GPL-2.0-or-later
237b59ef0SOliver O'Halloran
337b59ef0SOliver O'Halloran #include <linux/kernel.h>
437b59ef0SOliver O'Halloran #include <linux/ioport.h>
537b59ef0SOliver O'Halloran #include <linux/bitmap.h>
637b59ef0SOliver O'Halloran #include <linux/pci.h>
737b59ef0SOliver O'Halloran
837b59ef0SOliver O'Halloran #include <asm/opal.h>
937b59ef0SOliver O'Halloran
1037b59ef0SOliver O'Halloran #include "pci.h"
1137b59ef0SOliver O'Halloran
12ff79e11aSOliver O'Halloran /*
13ff79e11aSOliver O'Halloran * The majority of the complexity in supporting SR-IOV on PowerNV comes from
14ff79e11aSOliver O'Halloran * the need to put the MMIO space for each VF into a separate PE. Internally
15ff79e11aSOliver O'Halloran * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table".
16ff79e11aSOliver O'Halloran * The MBT historically only applied to the 64bit MMIO window of the PHB
17ff79e11aSOliver O'Halloran * so it's common to see it referred to as the "M64BT".
18ff79e11aSOliver O'Halloran *
19ff79e11aSOliver O'Halloran * An MBT entry stores the mapped range as an <base>,<mask> pair. This forces
20ff79e11aSOliver O'Halloran * the address range that we want to map to be power-of-two sized and aligned.
21ff79e11aSOliver O'Halloran * For conventional PCI devices this isn't really an issue since PCI device BARs
22ff79e11aSOliver O'Halloran * have the same requirement.
23ff79e11aSOliver O'Halloran *
24ff79e11aSOliver O'Halloran * For a SR-IOV BAR things are a little more awkward since size and alignment
2587c78b61SMichael Ellerman * are not coupled. The alignment is set based on the per-VF BAR size, but
26ff79e11aSOliver O'Halloran * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs
27ff79e11aSOliver O'Halloran * isn't necessarily a power of two, so neither is the total size. To fix that
28ff79e11aSOliver O'Halloran * we need to finesse (read: hack) the Linux BAR allocator so that it will
29ff79e11aSOliver O'Halloran * allocate the SR-IOV BARs in a way that lets us map them using the MBT.
30ff79e11aSOliver O'Halloran *
31ff79e11aSOliver O'Halloran * The changes to size and alignment that we need to do depend on the "mode"
32ff79e11aSOliver O'Halloran * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above,
33ff79e11aSOliver O'Halloran * so as a baseline we can assume that we have the following BAR modes
34ff79e11aSOliver O'Halloran * available:
35ff79e11aSOliver O'Halloran *
36ff79e11aSOliver O'Halloran * NB: $PE_COUNT is the number of PEs that the PHB supports.
37ff79e11aSOliver O'Halloran *
38ff79e11aSOliver O'Halloran * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized
39ff79e11aSOliver O'Halloran * segments. The n'th segment is mapped to the n'th PE.
40ff79e11aSOliver O'Halloran * b) An un-segmented BAR that maps the whole address range to a specific PE.
41ff79e11aSOliver O'Halloran *
42ff79e11aSOliver O'Halloran *
43ff79e11aSOliver O'Halloran * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR
44ff79e11aSOliver O'Halloran * For comparison b) requires one entry per-VF per-BAR, or:
45ff79e11aSOliver O'Halloran * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment
46ff79e11aSOliver O'Halloran * to equal the size of the per-VF BAR area. So:
47ff79e11aSOliver O'Halloran *
48ff79e11aSOliver O'Halloran * new_size = per-vf-size * number-of-PEs
49ff79e11aSOliver O'Halloran *
50ff79e11aSOliver O'Halloran * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size
51ff79e11aSOliver O'Halloran * to "new_size", calculated above. Implementing this is a convoluted process
52ff79e11aSOliver O'Halloran * which requires several hooks in the PCI core:
53ff79e11aSOliver O'Halloran *
5406dc660eSOliver O'Halloran * 1. In pcibios_device_add() we call pnv_pci_ioda_fixup_iov().
55ff79e11aSOliver O'Halloran *
56ff79e11aSOliver O'Halloran * At this point the device has been probed and the device's BARs are sized,
57ff79e11aSOliver O'Halloran * but no resource allocations have been done. The SR-IOV BARs are sized
58ff79e11aSOliver O'Halloran * based on the maximum number of VFs supported by the device and we need
59ff79e11aSOliver O'Halloran * to increase that to new_size.
60ff79e11aSOliver O'Halloran *
61ff79e11aSOliver O'Halloran * 2. Later, when Linux actually assigns resources it tries to make the resource
62ff79e11aSOliver O'Halloran * allocations for each PCI bus as compact as possible. As a part of that it
63ff79e11aSOliver O'Halloran * sorts the BARs on a bus by their required alignment, which is calculated
64ff79e11aSOliver O'Halloran * using pci_resource_alignment().
65ff79e11aSOliver O'Halloran *
66ff79e11aSOliver O'Halloran * For IOV resources this goes:
67ff79e11aSOliver O'Halloran * pci_resource_alignment()
68ff79e11aSOliver O'Halloran * pci_sriov_resource_alignment()
69ff79e11aSOliver O'Halloran * pcibios_sriov_resource_alignment()
70ff79e11aSOliver O'Halloran * pnv_pci_iov_resource_alignment()
71ff79e11aSOliver O'Halloran *
72ff79e11aSOliver O'Halloran * Our hook overrides the default alignment, equal to the per-vf-size, with
73ff79e11aSOliver O'Halloran * new_size computed above.
74ff79e11aSOliver O'Halloran *
75ff79e11aSOliver O'Halloran * 3. When userspace enables VFs for a device:
76ff79e11aSOliver O'Halloran *
77ff79e11aSOliver O'Halloran * sriov_enable()
78ff79e11aSOliver O'Halloran * pcibios_sriov_enable()
79ff79e11aSOliver O'Halloran * pnv_pcibios_sriov_enable()
80ff79e11aSOliver O'Halloran *
81ff79e11aSOliver O'Halloran * This is where we actually allocate PE numbers for each VF and setup the
82ff79e11aSOliver O'Halloran * MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena"
83ff79e11aSOliver O'Halloran * where each MBT segment is equal in size to the VF BAR so we can shift
84ff79e11aSOliver O'Halloran * around the actual SR-IOV BAR location within this arena. We need this
85ff79e11aSOliver O'Halloran * ability because the PE space is shared by all devices on the same PHB.
86ff79e11aSOliver O'Halloran * When using mode a) described above segment 0 in maps to PE#0 which might
87ff79e11aSOliver O'Halloran * be already being used by another device on the PHB.
88ff79e11aSOliver O'Halloran *
89ff79e11aSOliver O'Halloran * As a result we need allocate a contigious range of PE numbers, then shift
90ff79e11aSOliver O'Halloran * the address programmed into the SR-IOV BAR of the PF so that the address
91ff79e11aSOliver O'Halloran * of VF0 matches up with the segment corresponding to the first allocated
92ff79e11aSOliver O'Halloran * PE number. This is handled in pnv_pci_vf_resource_shift().
93ff79e11aSOliver O'Halloran *
94ff79e11aSOliver O'Halloran * Once all that is done we return to the PCI core which then enables VFs,
95ff79e11aSOliver O'Halloran * scans them and creates pci_devs for each. The init process for a VF is
96ff79e11aSOliver O'Halloran * largely the same as a normal device, but the VF is inserted into the IODA
97ff79e11aSOliver O'Halloran * PE that we allocated for it rather than the PE associated with the bus.
98ff79e11aSOliver O'Halloran *
99ff79e11aSOliver O'Halloran * 4. When userspace disables VFs we unwind the above in
100ff79e11aSOliver O'Halloran * pnv_pcibios_sriov_disable(). Fortunately this is relatively simple since
101ff79e11aSOliver O'Halloran * we don't need to validate anything, just tear down the mappings and
102ff79e11aSOliver O'Halloran * move SR-IOV resource back to its "proper" location.
103ff79e11aSOliver O'Halloran *
104ff79e11aSOliver O'Halloran * That's how mode a) works. In theory mode b) (single PE mapping) is less work
105ff79e11aSOliver O'Halloran * since we can map each individual VF with a separate BAR. However, there's a
106ff79e11aSOliver O'Halloran * few limitations:
107ff79e11aSOliver O'Halloran *
108ff79e11aSOliver O'Halloran * 1) For IODA2 mode b) has a minimum alignment requirement of 32MB. This makes
109ff79e11aSOliver O'Halloran * it only usable for devices with very large per-VF BARs. Such devices are
110ff79e11aSOliver O'Halloran * similar to Big Foot. They definitely exist, but I've never seen one.
111ff79e11aSOliver O'Halloran *
112ff79e11aSOliver O'Halloran * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only
113ff79e11aSOliver O'Halloran * 16 total and some are needed for. Most SR-IOV capable network cards can support
114ff79e11aSOliver O'Halloran * more than 16 VFs on each port.
115ff79e11aSOliver O'Halloran *
116ff79e11aSOliver O'Halloran * We use b) when using a) would use more than 1/4 of the entire 64 bit MMIO
117ff79e11aSOliver O'Halloran * window of the PHB.
118ff79e11aSOliver O'Halloran *
119ff79e11aSOliver O'Halloran *
120ff79e11aSOliver O'Halloran *
121ff79e11aSOliver O'Halloran * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It
122ff79e11aSOliver O'Halloran * allowed the MBT to map 32bit MMIO space in addition to 64bit which allows
123ff79e11aSOliver O'Halloran * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since
124ff79e11aSOliver O'Halloran * the Linux BAR allocation will place any BAR marked as non-prefetchable into
125ff79e11aSOliver O'Halloran * the non-prefetchable bridge window, which is 32bit only. It also added two
126ff79e11aSOliver O'Halloran * new modes:
127ff79e11aSOliver O'Halloran *
128ff79e11aSOliver O'Halloran * c) A segmented BAR similar to a), but each segment can be individually
129ff79e11aSOliver O'Halloran * mapped to any PE. This is matches how the 32bit MMIO window worked on
130ff79e11aSOliver O'Halloran * IODA1&2.
131ff79e11aSOliver O'Halloran *
132ff79e11aSOliver O'Halloran * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a),
133ff79e11aSOliver O'Halloran * but with fewer segments and configurable base PE.
134ff79e11aSOliver O'Halloran *
135ff79e11aSOliver O'Halloran * i.e. The n'th segment maps to the (n + base)'th PE.
136ff79e11aSOliver O'Halloran *
137ff79e11aSOliver O'Halloran * The base PE is also required to be a multiple of the window size.
138ff79e11aSOliver O'Halloran *
139ff79e11aSOliver O'Halloran * Unfortunately, the OPAL API doesn't currently (as of skiboot v6.6) allow us
140ff79e11aSOliver O'Halloran * to exploit any of the IODA3 features.
141ff79e11aSOliver O'Halloran */
14237b59ef0SOliver O'Halloran
pnv_pci_ioda_fixup_iov_resources(struct pci_dev * pdev)14337b59ef0SOliver O'Halloran static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
14437b59ef0SOliver O'Halloran {
14537b59ef0SOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
14637b59ef0SOliver O'Halloran struct resource *res;
14737b59ef0SOliver O'Halloran int i;
1484c51f3e1SOliver O'Halloran resource_size_t vf_bar_sz;
14937b59ef0SOliver O'Halloran struct pnv_iov_data *iov;
1504c51f3e1SOliver O'Halloran int mul;
15137b59ef0SOliver O'Halloran
15237b59ef0SOliver O'Halloran iov = kzalloc(sizeof(*iov), GFP_KERNEL);
15337b59ef0SOliver O'Halloran if (!iov)
154fac248f8SOliver O'Halloran goto disable_iov;
15537b59ef0SOliver O'Halloran pdev->dev.archdata.iov_data = iov;
15637b59ef0SOliver O'Halloran mul = phb->ioda.total_pe_num;
15737b59ef0SOliver O'Halloran
15837b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
15937b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES];
16037b59ef0SOliver O'Halloran if (!res->flags || res->parent)
16137b59ef0SOliver O'Halloran continue;
16237b59ef0SOliver O'Halloran if (!pnv_pci_is_m64_flags(res->flags)) {
16337b59ef0SOliver O'Halloran dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n",
16437b59ef0SOliver O'Halloran i, res);
165fac248f8SOliver O'Halloran goto disable_iov;
16637b59ef0SOliver O'Halloran }
16737b59ef0SOliver O'Halloran
1684c51f3e1SOliver O'Halloran vf_bar_sz = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
16937b59ef0SOliver O'Halloran
17037b59ef0SOliver O'Halloran /*
1714c51f3e1SOliver O'Halloran * Generally, one segmented M64 BAR maps one IOV BAR. However,
1724c51f3e1SOliver O'Halloran * if a VF BAR is too large we end up wasting a lot of space.
1734c51f3e1SOliver O'Halloran * If each VF needs more than 1/4 of the default m64 segment
1744c51f3e1SOliver O'Halloran * then each VF BAR should be mapped in single-PE mode to reduce
1754c51f3e1SOliver O'Halloran * the amount of space required. This does however limit the
1764c51f3e1SOliver O'Halloran * number of VFs we can support.
17737b59ef0SOliver O'Halloran *
1784c51f3e1SOliver O'Halloran * The 1/4 limit is arbitrary and can be tweaked.
17937b59ef0SOliver O'Halloran */
1804c51f3e1SOliver O'Halloran if (vf_bar_sz > (phb->ioda.m64_segsize >> 2)) {
18137b59ef0SOliver O'Halloran /*
1824c51f3e1SOliver O'Halloran * On PHB3, the minimum size alignment of M64 BAR in
1834c51f3e1SOliver O'Halloran * single mode is 32MB. If this VF BAR is smaller than
1844c51f3e1SOliver O'Halloran * 32MB, but still too large for a segmented window
1854c51f3e1SOliver O'Halloran * then we can't map it and need to disable SR-IOV for
1864c51f3e1SOliver O'Halloran * this device.
18737b59ef0SOliver O'Halloran */
1884c51f3e1SOliver O'Halloran if (vf_bar_sz < SZ_32M) {
1894c51f3e1SOliver O'Halloran pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n",
1904c51f3e1SOliver O'Halloran i, res);
191fac248f8SOliver O'Halloran goto disable_iov;
19237b59ef0SOliver O'Halloran }
1934c51f3e1SOliver O'Halloran
1944c51f3e1SOliver O'Halloran iov->m64_single_mode[i] = true;
1954c51f3e1SOliver O'Halloran continue;
1964c51f3e1SOliver O'Halloran }
1974c51f3e1SOliver O'Halloran
1984c51f3e1SOliver O'Halloran /*
1994c51f3e1SOliver O'Halloran * This BAR can be mapped with one segmented window, so adjust
2004c51f3e1SOliver O'Halloran * te resource size to accommodate.
2014c51f3e1SOliver O'Halloran */
2024c51f3e1SOliver O'Halloran pci_dbg(pdev, " Fixing VF BAR%d: %pR to\n", i, res);
2034c51f3e1SOliver O'Halloran res->end = res->start + vf_bar_sz * mul - 1;
2044c51f3e1SOliver O'Halloran pci_dbg(pdev, " %pR\n", res);
2054c51f3e1SOliver O'Halloran
2064c51f3e1SOliver O'Halloran pci_info(pdev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2074c51f3e1SOliver O'Halloran i, res, mul);
2084c51f3e1SOliver O'Halloran
2094c51f3e1SOliver O'Halloran iov->need_shift = true;
2104c51f3e1SOliver O'Halloran }
2114c51f3e1SOliver O'Halloran
21237b59ef0SOliver O'Halloran return;
21337b59ef0SOliver O'Halloran
214fac248f8SOliver O'Halloran disable_iov:
215fac248f8SOliver O'Halloran /* Save ourselves some MMIO space by disabling the unusable BARs */
21637b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
21737b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES];
21837b59ef0SOliver O'Halloran res->flags = 0;
21937b59ef0SOliver O'Halloran res->end = res->start - 1;
22037b59ef0SOliver O'Halloran }
22137b59ef0SOliver O'Halloran
22237b59ef0SOliver O'Halloran pdev->dev.archdata.iov_data = NULL;
22337b59ef0SOliver O'Halloran kfree(iov);
22437b59ef0SOliver O'Halloran }
22537b59ef0SOliver O'Halloran
pnv_pci_ioda_fixup_iov(struct pci_dev * pdev)22637b59ef0SOliver O'Halloran void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
22737b59ef0SOliver O'Halloran {
22837b59ef0SOliver O'Halloran if (pdev->is_virtfn) {
22937b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
23037b59ef0SOliver O'Halloran
23137b59ef0SOliver O'Halloran /*
23237b59ef0SOliver O'Halloran * VF PEs are single-device PEs so their pdev pointer needs to
23337b59ef0SOliver O'Halloran * be set. The pdev doesn't exist when the PE is allocated (in
23437b59ef0SOliver O'Halloran * (pcibios_sriov_enable()) so we fix it up here.
23537b59ef0SOliver O'Halloran */
23637b59ef0SOliver O'Halloran pe->pdev = pdev;
23737b59ef0SOliver O'Halloran WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
23837b59ef0SOliver O'Halloran } else if (pdev->is_physfn) {
23937b59ef0SOliver O'Halloran /*
24037b59ef0SOliver O'Halloran * For PFs adjust their allocated IOV resources to match what
24137b59ef0SOliver O'Halloran * the PHB can support using it's M64 BAR table.
24237b59ef0SOliver O'Halloran */
24337b59ef0SOliver O'Halloran pnv_pci_ioda_fixup_iov_resources(pdev);
24437b59ef0SOliver O'Halloran }
24537b59ef0SOliver O'Halloran }
24637b59ef0SOliver O'Halloran
pnv_pci_iov_resource_alignment(struct pci_dev * pdev,int resno)24737b59ef0SOliver O'Halloran resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
24837b59ef0SOliver O'Halloran int resno)
24937b59ef0SOliver O'Halloran {
2502075ec98SOliver O'Halloran resource_size_t align = pci_iov_resource_size(pdev, resno);
25184d8505eSOliver O'Halloran struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
25237b59ef0SOliver O'Halloran struct pnv_iov_data *iov = pnv_iov_get(pdev);
25337b59ef0SOliver O'Halloran
25437b59ef0SOliver O'Halloran /*
2554c51f3e1SOliver O'Halloran * iov can be null if we have an SR-IOV device with IOV BAR that can't
2564c51f3e1SOliver O'Halloran * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch).
2574c51f3e1SOliver O'Halloran * In that case we don't allow VFs to be enabled since one of their
2584c51f3e1SOliver O'Halloran * BARs would not be placed in the correct PE.
2594c51f3e1SOliver O'Halloran */
2604c51f3e1SOliver O'Halloran if (!iov)
2614c51f3e1SOliver O'Halloran return align;
2624c51f3e1SOliver O'Halloran
2634c51f3e1SOliver O'Halloran /*
2644c51f3e1SOliver O'Halloran * If we're using single mode then we can just use the native VF BAR
2654c51f3e1SOliver O'Halloran * alignment. We validated that it's possible to use a single PE
2664c51f3e1SOliver O'Halloran * window above when we did the fixup.
2674c51f3e1SOliver O'Halloran */
2684c51f3e1SOliver O'Halloran if (iov->m64_single_mode[resno - PCI_IOV_RESOURCES])
2694c51f3e1SOliver O'Halloran return align;
2704c51f3e1SOliver O'Halloran
2714c51f3e1SOliver O'Halloran /*
27237b59ef0SOliver O'Halloran * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
27337b59ef0SOliver O'Halloran * SR-IOV. While from hardware perspective, the range mapped by M64
27437b59ef0SOliver O'Halloran * BAR should be size aligned.
27537b59ef0SOliver O'Halloran *
27637b59ef0SOliver O'Halloran * This function returns the total IOV BAR size if M64 BAR is in
27737b59ef0SOliver O'Halloran * Shared PE mode or just VF BAR size if not.
27837b59ef0SOliver O'Halloran * If the M64 BAR is in Single PE mode, return the VF BAR size or
27937b59ef0SOliver O'Halloran * M64 segment size if IOV BAR size is less.
28037b59ef0SOliver O'Halloran */
28184d8505eSOliver O'Halloran return phb->ioda.total_pe_num * align;
28237b59ef0SOliver O'Halloran }
28337b59ef0SOliver O'Halloran
pnv_pci_vf_release_m64(struct pci_dev * pdev,u16 num_vfs)28437b59ef0SOliver O'Halloran static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
28537b59ef0SOliver O'Halloran {
28637b59ef0SOliver O'Halloran struct pnv_iov_data *iov;
28737b59ef0SOliver O'Halloran struct pnv_phb *phb;
288ad9add52SOliver O'Halloran int window_id;
28937b59ef0SOliver O'Halloran
29037b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus);
29137b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev);
29237b59ef0SOliver O'Halloran
293ad9add52SOliver O'Halloran for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) {
29437b59ef0SOliver O'Halloran opal_pci_phb_mmio_enable(phb->opal_id,
295ad9add52SOliver O'Halloran OPAL_M64_WINDOW_TYPE,
296ad9add52SOliver O'Halloran window_id,
297ad9add52SOliver O'Halloran 0);
298ad9add52SOliver O'Halloran
299ad9add52SOliver O'Halloran clear_bit(window_id, &phb->ioda.m64_bar_alloc);
30037b59ef0SOliver O'Halloran }
30137b59ef0SOliver O'Halloran
30237b59ef0SOliver O'Halloran return 0;
30337b59ef0SOliver O'Halloran }
30437b59ef0SOliver O'Halloran
305a610d35cSOliver O'Halloran
306a610d35cSOliver O'Halloran /*
307a610d35cSOliver O'Halloran * PHB3 and beyond support segmented windows. The window's address range
308a610d35cSOliver O'Halloran * is subdivided into phb->ioda.total_pe_num segments and there's a 1-1
309a610d35cSOliver O'Halloran * mapping between PEs and segments.
310a610d35cSOliver O'Halloran */
pnv_ioda_map_m64_segmented(struct pnv_phb * phb,int window_id,resource_size_t start,resource_size_t size)311a610d35cSOliver O'Halloran static int64_t pnv_ioda_map_m64_segmented(struct pnv_phb *phb,
312a610d35cSOliver O'Halloran int window_id,
313a610d35cSOliver O'Halloran resource_size_t start,
314a610d35cSOliver O'Halloran resource_size_t size)
315a610d35cSOliver O'Halloran {
316a610d35cSOliver O'Halloran int64_t rc;
317a610d35cSOliver O'Halloran
318a610d35cSOliver O'Halloran rc = opal_pci_set_phb_mem_window(phb->opal_id,
319a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE,
320a610d35cSOliver O'Halloran window_id,
321a610d35cSOliver O'Halloran start,
322a610d35cSOliver O'Halloran 0, /* unused */
323a610d35cSOliver O'Halloran size);
324a610d35cSOliver O'Halloran if (rc)
325a610d35cSOliver O'Halloran goto out;
326a610d35cSOliver O'Halloran
327a610d35cSOliver O'Halloran rc = opal_pci_phb_mmio_enable(phb->opal_id,
328a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE,
329a610d35cSOliver O'Halloran window_id,
330a610d35cSOliver O'Halloran OPAL_ENABLE_M64_SPLIT);
331a610d35cSOliver O'Halloran out:
332a610d35cSOliver O'Halloran if (rc)
333a610d35cSOliver O'Halloran pr_err("Failed to map M64 window #%d: %lld\n", window_id, rc);
334a610d35cSOliver O'Halloran
335a610d35cSOliver O'Halloran return rc;
336a610d35cSOliver O'Halloran }
337a610d35cSOliver O'Halloran
pnv_ioda_map_m64_single(struct pnv_phb * phb,int pe_num,int window_id,resource_size_t start,resource_size_t size)338a610d35cSOliver O'Halloran static int64_t pnv_ioda_map_m64_single(struct pnv_phb *phb,
339a610d35cSOliver O'Halloran int pe_num,
340a610d35cSOliver O'Halloran int window_id,
341a610d35cSOliver O'Halloran resource_size_t start,
342a610d35cSOliver O'Halloran resource_size_t size)
343a610d35cSOliver O'Halloran {
344a610d35cSOliver O'Halloran int64_t rc;
345a610d35cSOliver O'Halloran
346a610d35cSOliver O'Halloran /*
347a610d35cSOliver O'Halloran * The API for setting up m64 mmio windows seems to have been designed
348a610d35cSOliver O'Halloran * with P7-IOC in mind. For that chip each M64 BAR (window) had a fixed
349a610d35cSOliver O'Halloran * split of 8 equally sized segments each of which could individually
350a610d35cSOliver O'Halloran * assigned to a PE.
351a610d35cSOliver O'Halloran *
352a610d35cSOliver O'Halloran * The problem with this is that the API doesn't have any way to
353a610d35cSOliver O'Halloran * communicate the number of segments we want on a BAR. This wasn't
354a610d35cSOliver O'Halloran * a problem for p7-ioc since you didn't have a choice, but the
355a610d35cSOliver O'Halloran * single PE windows added in PHB3 don't map cleanly to this API.
356a610d35cSOliver O'Halloran *
357a610d35cSOliver O'Halloran * As a result we've got this slightly awkward process where we
358a610d35cSOliver O'Halloran * call opal_pci_map_pe_mmio_window() to put the single in single
359a610d35cSOliver O'Halloran * PE mode, and set the PE for the window before setting the address
360a610d35cSOliver O'Halloran * bounds. We need to do it this way because the single PE windows
361a610d35cSOliver O'Halloran * for PHB3 have different alignment requirements on PHB3.
362a610d35cSOliver O'Halloran */
363a610d35cSOliver O'Halloran rc = opal_pci_map_pe_mmio_window(phb->opal_id,
364a610d35cSOliver O'Halloran pe_num,
365a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE,
366a610d35cSOliver O'Halloran window_id,
367a610d35cSOliver O'Halloran 0);
368a610d35cSOliver O'Halloran if (rc)
369a610d35cSOliver O'Halloran goto out;
370a610d35cSOliver O'Halloran
371a610d35cSOliver O'Halloran /*
372a610d35cSOliver O'Halloran * NB: In single PE mode the window needs to be aligned to 32MB
373a610d35cSOliver O'Halloran */
374a610d35cSOliver O'Halloran rc = opal_pci_set_phb_mem_window(phb->opal_id,
375a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE,
376a610d35cSOliver O'Halloran window_id,
377a610d35cSOliver O'Halloran start,
378a610d35cSOliver O'Halloran 0, /* ignored by FW, m64 is 1-1 */
379a610d35cSOliver O'Halloran size);
380a610d35cSOliver O'Halloran if (rc)
381a610d35cSOliver O'Halloran goto out;
382a610d35cSOliver O'Halloran
383a610d35cSOliver O'Halloran /*
384a610d35cSOliver O'Halloran * Now actually enable it. We specified the BAR should be in "non-split"
385a610d35cSOliver O'Halloran * mode so FW will validate that the BAR is in single PE mode.
386a610d35cSOliver O'Halloran */
387a610d35cSOliver O'Halloran rc = opal_pci_phb_mmio_enable(phb->opal_id,
388a610d35cSOliver O'Halloran OPAL_M64_WINDOW_TYPE,
389a610d35cSOliver O'Halloran window_id,
390a610d35cSOliver O'Halloran OPAL_ENABLE_M64_NON_SPLIT);
391a610d35cSOliver O'Halloran out:
392a610d35cSOliver O'Halloran if (rc)
393a610d35cSOliver O'Halloran pr_err("Error mapping single PE BAR\n");
394a610d35cSOliver O'Halloran
395a610d35cSOliver O'Halloran return rc;
396a610d35cSOliver O'Halloran }
397a610d35cSOliver O'Halloran
pnv_pci_alloc_m64_bar(struct pnv_phb * phb,struct pnv_iov_data * iov)39839efc03eSOliver O'Halloran static int pnv_pci_alloc_m64_bar(struct pnv_phb *phb, struct pnv_iov_data *iov)
39939efc03eSOliver O'Halloran {
40039efc03eSOliver O'Halloran int win;
40139efc03eSOliver O'Halloran
40239efc03eSOliver O'Halloran do {
40339efc03eSOliver O'Halloran win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
40439efc03eSOliver O'Halloran phb->ioda.m64_bar_idx + 1, 0);
40539efc03eSOliver O'Halloran
40639efc03eSOliver O'Halloran if (win >= phb->ioda.m64_bar_idx + 1)
40739efc03eSOliver O'Halloran return -1;
40839efc03eSOliver O'Halloran } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
40939efc03eSOliver O'Halloran
41039efc03eSOliver O'Halloran set_bit(win, iov->used_m64_bar_mask);
41139efc03eSOliver O'Halloran
41239efc03eSOliver O'Halloran return win;
41339efc03eSOliver O'Halloran }
41439efc03eSOliver O'Halloran
pnv_pci_vf_assign_m64(struct pci_dev * pdev,u16 num_vfs)41537b59ef0SOliver O'Halloran static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
41637b59ef0SOliver O'Halloran {
41737b59ef0SOliver O'Halloran struct pnv_iov_data *iov;
41837b59ef0SOliver O'Halloran struct pnv_phb *phb;
419027717a4SKaixu Xia int win;
42037b59ef0SOliver O'Halloran struct resource *res;
42137b59ef0SOliver O'Halloran int i, j;
42237b59ef0SOliver O'Halloran int64_t rc;
42337b59ef0SOliver O'Halloran resource_size_t size, start;
424a0be516fSOliver O'Halloran int base_pe_num;
42537b59ef0SOliver O'Halloran
42637b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus);
42737b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev);
42837b59ef0SOliver O'Halloran
42937b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
43037b59ef0SOliver O'Halloran res = &pdev->resource[i + PCI_IOV_RESOURCES];
43137b59ef0SOliver O'Halloran if (!res->flags || !res->parent)
43237b59ef0SOliver O'Halloran continue;
43337b59ef0SOliver O'Halloran
434a0be516fSOliver O'Halloran /* don't need single mode? map everything in one go! */
4354c51f3e1SOliver O'Halloran if (!iov->m64_single_mode[i]) {
43639efc03eSOliver O'Halloran win = pnv_pci_alloc_m64_bar(phb, iov);
43739efc03eSOliver O'Halloran if (win < 0)
43837b59ef0SOliver O'Halloran goto m64_failed;
439a610d35cSOliver O'Halloran
44037b59ef0SOliver O'Halloran size = resource_size(res);
44137b59ef0SOliver O'Halloran start = res->start;
44237b59ef0SOliver O'Halloran
443a0be516fSOliver O'Halloran rc = pnv_ioda_map_m64_segmented(phb, win, start, size);
444a0be516fSOliver O'Halloran if (rc)
445a0be516fSOliver O'Halloran goto m64_failed;
446a0be516fSOliver O'Halloran
447a0be516fSOliver O'Halloran continue;
448a610d35cSOliver O'Halloran }
44937b59ef0SOliver O'Halloran
450a0be516fSOliver O'Halloran /* otherwise map each VF with single PE BARs */
451a0be516fSOliver O'Halloran size = pci_iov_resource_size(pdev, PCI_IOV_RESOURCES + i);
452a0be516fSOliver O'Halloran base_pe_num = iov->vf_pe_arr[0].pe_number;
453a0be516fSOliver O'Halloran
454a0be516fSOliver O'Halloran for (j = 0; j < num_vfs; j++) {
455a0be516fSOliver O'Halloran win = pnv_pci_alloc_m64_bar(phb, iov);
456a0be516fSOliver O'Halloran if (win < 0)
45737b59ef0SOliver O'Halloran goto m64_failed;
458a0be516fSOliver O'Halloran
459a0be516fSOliver O'Halloran start = res->start + size * j;
460a0be516fSOliver O'Halloran rc = pnv_ioda_map_m64_single(phb, win,
461a0be516fSOliver O'Halloran base_pe_num + j,
462a0be516fSOliver O'Halloran start,
463a0be516fSOliver O'Halloran size);
464a0be516fSOliver O'Halloran if (rc)
465a0be516fSOliver O'Halloran goto m64_failed;
46637b59ef0SOliver O'Halloran }
46737b59ef0SOliver O'Halloran }
46837b59ef0SOliver O'Halloran return 0;
46937b59ef0SOliver O'Halloran
47037b59ef0SOliver O'Halloran m64_failed:
47137b59ef0SOliver O'Halloran pnv_pci_vf_release_m64(pdev, num_vfs);
47237b59ef0SOliver O'Halloran return -EBUSY;
47337b59ef0SOliver O'Halloran }
47437b59ef0SOliver O'Halloran
pnv_ioda_release_vf_PE(struct pci_dev * pdev)47537b59ef0SOliver O'Halloran static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
47637b59ef0SOliver O'Halloran {
47737b59ef0SOliver O'Halloran struct pnv_phb *phb;
47837b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe, *pe_n;
47937b59ef0SOliver O'Halloran
48037b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus);
48137b59ef0SOliver O'Halloran
48237b59ef0SOliver O'Halloran if (!pdev->is_physfn)
48337b59ef0SOliver O'Halloran return;
48437b59ef0SOliver O'Halloran
48537b59ef0SOliver O'Halloran /* FIXME: Use pnv_ioda_release_pe()? */
48637b59ef0SOliver O'Halloran list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
48737b59ef0SOliver O'Halloran if (pe->parent_dev != pdev)
48837b59ef0SOliver O'Halloran continue;
48937b59ef0SOliver O'Halloran
49037b59ef0SOliver O'Halloran pnv_pci_ioda2_release_pe_dma(pe);
49137b59ef0SOliver O'Halloran
49237b59ef0SOliver O'Halloran /* Remove from list */
49337b59ef0SOliver O'Halloran mutex_lock(&phb->ioda.pe_list_mutex);
49437b59ef0SOliver O'Halloran list_del(&pe->list);
49537b59ef0SOliver O'Halloran mutex_unlock(&phb->ioda.pe_list_mutex);
49637b59ef0SOliver O'Halloran
49737b59ef0SOliver O'Halloran pnv_ioda_deconfigure_pe(phb, pe);
49837b59ef0SOliver O'Halloran
49937b59ef0SOliver O'Halloran pnv_ioda_free_pe(pe);
50037b59ef0SOliver O'Halloran }
50137b59ef0SOliver O'Halloran }
50237b59ef0SOliver O'Halloran
pnv_pci_vf_resource_shift(struct pci_dev * dev,int offset)50337b59ef0SOliver O'Halloran static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
50437b59ef0SOliver O'Halloran {
50537b59ef0SOliver O'Halloran struct resource *res, res2;
50637b59ef0SOliver O'Halloran struct pnv_iov_data *iov;
50737b59ef0SOliver O'Halloran resource_size_t size;
50837b59ef0SOliver O'Halloran u16 num_vfs;
50937b59ef0SOliver O'Halloran int i;
51037b59ef0SOliver O'Halloran
51137b59ef0SOliver O'Halloran if (!dev->is_physfn)
51237b59ef0SOliver O'Halloran return -EINVAL;
51337b59ef0SOliver O'Halloran iov = pnv_iov_get(dev);
51437b59ef0SOliver O'Halloran
51537b59ef0SOliver O'Halloran /*
51637b59ef0SOliver O'Halloran * "offset" is in VFs. The M64 windows are sized so that when they
51737b59ef0SOliver O'Halloran * are segmented, each segment is the same size as the IOV BAR.
51837b59ef0SOliver O'Halloran * Each segment is in a separate PE, and the high order bits of the
51937b59ef0SOliver O'Halloran * address are the PE number. Therefore, each VF's BAR is in a
52037b59ef0SOliver O'Halloran * separate PE, and changing the IOV BAR start address changes the
52137b59ef0SOliver O'Halloran * range of PEs the VFs are in.
52237b59ef0SOliver O'Halloran */
52337b59ef0SOliver O'Halloran num_vfs = iov->num_vfs;
52437b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
52537b59ef0SOliver O'Halloran res = &dev->resource[i + PCI_IOV_RESOURCES];
52637b59ef0SOliver O'Halloran if (!res->flags || !res->parent)
52737b59ef0SOliver O'Halloran continue;
5284c51f3e1SOliver O'Halloran if (iov->m64_single_mode[i])
5294c51f3e1SOliver O'Halloran continue;
53037b59ef0SOliver O'Halloran
53137b59ef0SOliver O'Halloran /*
53237b59ef0SOliver O'Halloran * The actual IOV BAR range is determined by the start address
53337b59ef0SOliver O'Halloran * and the actual size for num_vfs VFs BAR. This check is to
53437b59ef0SOliver O'Halloran * make sure that after shifting, the range will not overlap
53537b59ef0SOliver O'Halloran * with another device.
53637b59ef0SOliver O'Halloran */
53737b59ef0SOliver O'Halloran size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
53837b59ef0SOliver O'Halloran res2.flags = res->flags;
53937b59ef0SOliver O'Halloran res2.start = res->start + (size * offset);
54037b59ef0SOliver O'Halloran res2.end = res2.start + (size * num_vfs) - 1;
54137b59ef0SOliver O'Halloran
54237b59ef0SOliver O'Halloran if (res2.end > res->end) {
54337b59ef0SOliver O'Halloran dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
54437b59ef0SOliver O'Halloran i, &res2, res, num_vfs, offset);
54537b59ef0SOliver O'Halloran return -EBUSY;
54637b59ef0SOliver O'Halloran }
54737b59ef0SOliver O'Halloran }
54837b59ef0SOliver O'Halloran
54937b59ef0SOliver O'Halloran /*
55037b59ef0SOliver O'Halloran * Since M64 BAR shares segments among all possible 256 PEs,
55137b59ef0SOliver O'Halloran * we have to shift the beginning of PF IOV BAR to make it start from
55237b59ef0SOliver O'Halloran * the segment which belongs to the PE number assigned to the first VF.
55337b59ef0SOliver O'Halloran * This creates a "hole" in the /proc/iomem which could be used for
55437b59ef0SOliver O'Halloran * allocating other resources so we reserve this area below and
55537b59ef0SOliver O'Halloran * release when IOV is released.
55637b59ef0SOliver O'Halloran */
55737b59ef0SOliver O'Halloran for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
55837b59ef0SOliver O'Halloran res = &dev->resource[i + PCI_IOV_RESOURCES];
55937b59ef0SOliver O'Halloran if (!res->flags || !res->parent)
56037b59ef0SOliver O'Halloran continue;
5614c51f3e1SOliver O'Halloran if (iov->m64_single_mode[i])
5624c51f3e1SOliver O'Halloran continue;
56337b59ef0SOliver O'Halloran
56437b59ef0SOliver O'Halloran size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
56537b59ef0SOliver O'Halloran res2 = *res;
56637b59ef0SOliver O'Halloran res->start += size * offset;
56737b59ef0SOliver O'Halloran
56837b59ef0SOliver O'Halloran dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
56937b59ef0SOliver O'Halloran i, &res2, res, (offset > 0) ? "En" : "Dis",
57037b59ef0SOliver O'Halloran num_vfs, offset);
57137b59ef0SOliver O'Halloran
57237b59ef0SOliver O'Halloran if (offset < 0) {
57337b59ef0SOliver O'Halloran devm_release_resource(&dev->dev, &iov->holes[i]);
57437b59ef0SOliver O'Halloran memset(&iov->holes[i], 0, sizeof(iov->holes[i]));
57537b59ef0SOliver O'Halloran }
57637b59ef0SOliver O'Halloran
57737b59ef0SOliver O'Halloran pci_update_resource(dev, i + PCI_IOV_RESOURCES);
57837b59ef0SOliver O'Halloran
57937b59ef0SOliver O'Halloran if (offset > 0) {
58037b59ef0SOliver O'Halloran iov->holes[i].start = res2.start;
58137b59ef0SOliver O'Halloran iov->holes[i].end = res2.start + size * offset - 1;
58237b59ef0SOliver O'Halloran iov->holes[i].flags = IORESOURCE_BUS;
58337b59ef0SOliver O'Halloran iov->holes[i].name = "pnv_iov_reserved";
58437b59ef0SOliver O'Halloran devm_request_resource(&dev->dev, res->parent,
58537b59ef0SOliver O'Halloran &iov->holes[i]);
58637b59ef0SOliver O'Halloran }
58737b59ef0SOliver O'Halloran }
58837b59ef0SOliver O'Halloran return 0;
58937b59ef0SOliver O'Halloran }
59037b59ef0SOliver O'Halloran
pnv_pci_sriov_disable(struct pci_dev * pdev)59137b59ef0SOliver O'Halloran static void pnv_pci_sriov_disable(struct pci_dev *pdev)
59237b59ef0SOliver O'Halloran {
593d29a2488SOliver O'Halloran u16 num_vfs, base_pe;
59437b59ef0SOliver O'Halloran struct pnv_iov_data *iov;
59537b59ef0SOliver O'Halloran
59637b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev);
597052da31dSOliver O'Halloran if (WARN_ON(!iov))
598052da31dSOliver O'Halloran return;
599052da31dSOliver O'Halloran
600*f4f913c9SColin Ian King num_vfs = iov->num_vfs;
601*f4f913c9SColin Ian King base_pe = iov->vf_pe_arr[0].pe_number;
602*f4f913c9SColin Ian King
60337b59ef0SOliver O'Halloran /* Release VF PEs */
60437b59ef0SOliver O'Halloran pnv_ioda_release_vf_PE(pdev);
60537b59ef0SOliver O'Halloran
6064c51f3e1SOliver O'Halloran /* Un-shift the IOV BARs if we need to */
6074c51f3e1SOliver O'Halloran if (iov->need_shift)
608d29a2488SOliver O'Halloran pnv_pci_vf_resource_shift(pdev, -base_pe);
60937b59ef0SOliver O'Halloran
61037b59ef0SOliver O'Halloran /* Release M64 windows */
61137b59ef0SOliver O'Halloran pnv_pci_vf_release_m64(pdev, num_vfs);
61237b59ef0SOliver O'Halloran }
61337b59ef0SOliver O'Halloran
pnv_ioda_setup_vf_PE(struct pci_dev * pdev,u16 num_vfs)61437b59ef0SOliver O'Halloran static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
61537b59ef0SOliver O'Halloran {
61637b59ef0SOliver O'Halloran struct pnv_phb *phb;
61737b59ef0SOliver O'Halloran struct pnv_ioda_pe *pe;
61837b59ef0SOliver O'Halloran int pe_num;
61937b59ef0SOliver O'Halloran u16 vf_index;
62037b59ef0SOliver O'Halloran struct pnv_iov_data *iov;
62137b59ef0SOliver O'Halloran struct pci_dn *pdn;
62237b59ef0SOliver O'Halloran
62337b59ef0SOliver O'Halloran if (!pdev->is_physfn)
62437b59ef0SOliver O'Halloran return;
62537b59ef0SOliver O'Halloran
62637b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus);
62737b59ef0SOliver O'Halloran pdn = pci_get_pdn(pdev);
62837b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev);
62937b59ef0SOliver O'Halloran
63037b59ef0SOliver O'Halloran /* Reserve PE for each VF */
63137b59ef0SOliver O'Halloran for (vf_index = 0; vf_index < num_vfs; vf_index++) {
63237b59ef0SOliver O'Halloran int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
63337b59ef0SOliver O'Halloran int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
63437b59ef0SOliver O'Halloran struct pci_dn *vf_pdn;
63537b59ef0SOliver O'Halloran
636d29a2488SOliver O'Halloran pe = &iov->vf_pe_arr[vf_index];
63737b59ef0SOliver O'Halloran pe->phb = phb;
63837b59ef0SOliver O'Halloran pe->flags = PNV_IODA_PE_VF;
63937b59ef0SOliver O'Halloran pe->pbus = NULL;
64037b59ef0SOliver O'Halloran pe->parent_dev = pdev;
64137b59ef0SOliver O'Halloran pe->mve_number = -1;
64237b59ef0SOliver O'Halloran pe->rid = (vf_bus << 8) | vf_devfn;
64337b59ef0SOliver O'Halloran
644d29a2488SOliver O'Halloran pe_num = pe->pe_number;
64537b59ef0SOliver O'Halloran pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
64637b59ef0SOliver O'Halloran pci_domain_nr(pdev->bus), pdev->bus->number,
64737b59ef0SOliver O'Halloran PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
64837b59ef0SOliver O'Halloran
64937b59ef0SOliver O'Halloran if (pnv_ioda_configure_pe(phb, pe)) {
65037b59ef0SOliver O'Halloran /* XXX What do we do here ? */
65137b59ef0SOliver O'Halloran pnv_ioda_free_pe(pe);
65237b59ef0SOliver O'Halloran pe->pdev = NULL;
65337b59ef0SOliver O'Halloran continue;
65437b59ef0SOliver O'Halloran }
65537b59ef0SOliver O'Halloran
65637b59ef0SOliver O'Halloran /* Put PE to the list */
65737b59ef0SOliver O'Halloran mutex_lock(&phb->ioda.pe_list_mutex);
65837b59ef0SOliver O'Halloran list_add_tail(&pe->list, &phb->ioda.pe_list);
65937b59ef0SOliver O'Halloran mutex_unlock(&phb->ioda.pe_list_mutex);
66037b59ef0SOliver O'Halloran
66137b59ef0SOliver O'Halloran /* associate this pe to it's pdn */
66237b59ef0SOliver O'Halloran list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
66337b59ef0SOliver O'Halloran if (vf_pdn->busno == vf_bus &&
66437b59ef0SOliver O'Halloran vf_pdn->devfn == vf_devfn) {
66537b59ef0SOliver O'Halloran vf_pdn->pe_number = pe_num;
66637b59ef0SOliver O'Halloran break;
66737b59ef0SOliver O'Halloran }
66837b59ef0SOliver O'Halloran }
66937b59ef0SOliver O'Halloran
67037b59ef0SOliver O'Halloran pnv_pci_ioda2_setup_dma_pe(phb, pe);
67137b59ef0SOliver O'Halloran }
67237b59ef0SOliver O'Halloran }
67337b59ef0SOliver O'Halloran
pnv_pci_sriov_enable(struct pci_dev * pdev,u16 num_vfs)67437b59ef0SOliver O'Halloran static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
67537b59ef0SOliver O'Halloran {
676d29a2488SOliver O'Halloran struct pnv_ioda_pe *base_pe;
67737b59ef0SOliver O'Halloran struct pnv_iov_data *iov;
67837b59ef0SOliver O'Halloran struct pnv_phb *phb;
67937b59ef0SOliver O'Halloran int ret;
68037b59ef0SOliver O'Halloran u16 i;
68137b59ef0SOliver O'Halloran
68237b59ef0SOliver O'Halloran phb = pci_bus_to_pnvhb(pdev->bus);
68337b59ef0SOliver O'Halloran iov = pnv_iov_get(pdev);
68437b59ef0SOliver O'Halloran
685052da31dSOliver O'Halloran /*
686052da31dSOliver O'Halloran * There's a calls to IODA2 PE setup code littered throughout. We could
687052da31dSOliver O'Halloran * probably fix that, but we'd still have problems due to the
688052da31dSOliver O'Halloran * restriction inherent on IODA1 PHBs.
689052da31dSOliver O'Halloran *
690052da31dSOliver O'Halloran * NB: We class IODA3 as IODA2 since they're very similar.
691052da31dSOliver O'Halloran */
692052da31dSOliver O'Halloran if (phb->type != PNV_PHB_IODA2) {
693052da31dSOliver O'Halloran pci_err(pdev, "SR-IOV is not supported on this PHB\n");
694052da31dSOliver O'Halloran return -ENXIO;
695052da31dSOliver O'Halloran }
696052da31dSOliver O'Halloran
69784d8505eSOliver O'Halloran if (!iov) {
698052da31dSOliver O'Halloran dev_info(&pdev->dev, "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n");
69937b59ef0SOliver O'Halloran return -ENOSPC;
70037b59ef0SOliver O'Halloran }
70137b59ef0SOliver O'Halloran
7021fd02f66SJulia Lawall /* allocate a contiguous block of PEs for our VFs */
703d29a2488SOliver O'Halloran base_pe = pnv_ioda_alloc_pe(phb, num_vfs);
704d29a2488SOliver O'Halloran if (!base_pe) {
705d29a2488SOliver O'Halloran pci_err(pdev, "Unable to allocate PEs for %d VFs\n", num_vfs);
70637b59ef0SOliver O'Halloran return -EBUSY;
70737b59ef0SOliver O'Halloran }
70837b59ef0SOliver O'Halloran
709d29a2488SOliver O'Halloran iov->vf_pe_arr = base_pe;
71037b59ef0SOliver O'Halloran iov->num_vfs = num_vfs;
71137b59ef0SOliver O'Halloran
71237b59ef0SOliver O'Halloran /* Assign M64 window accordingly */
71337b59ef0SOliver O'Halloran ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
71437b59ef0SOliver O'Halloran if (ret) {
71537b59ef0SOliver O'Halloran dev_info(&pdev->dev, "Not enough M64 window resources\n");
71637b59ef0SOliver O'Halloran goto m64_failed;
71737b59ef0SOliver O'Halloran }
71837b59ef0SOliver O'Halloran
71937b59ef0SOliver O'Halloran /*
72037b59ef0SOliver O'Halloran * When using one M64 BAR to map one IOV BAR, we need to shift
72137b59ef0SOliver O'Halloran * the IOV BAR according to the PE# allocated to the VFs.
72237b59ef0SOliver O'Halloran * Otherwise, the PE# for the VF will conflict with others.
72337b59ef0SOliver O'Halloran */
7244c51f3e1SOliver O'Halloran if (iov->need_shift) {
7254c51f3e1SOliver O'Halloran ret = pnv_pci_vf_resource_shift(pdev, base_pe->pe_number);
72637b59ef0SOliver O'Halloran if (ret)
727d29a2488SOliver O'Halloran goto shift_failed;
72837b59ef0SOliver O'Halloran }
72937b59ef0SOliver O'Halloran
73037b59ef0SOliver O'Halloran /* Setup VF PEs */
73137b59ef0SOliver O'Halloran pnv_ioda_setup_vf_PE(pdev, num_vfs);
73237b59ef0SOliver O'Halloran
73337b59ef0SOliver O'Halloran return 0;
73437b59ef0SOliver O'Halloran
735d29a2488SOliver O'Halloran shift_failed:
736d29a2488SOliver O'Halloran pnv_pci_vf_release_m64(pdev, num_vfs);
737d29a2488SOliver O'Halloran
73837b59ef0SOliver O'Halloran m64_failed:
739d29a2488SOliver O'Halloran for (i = 0; i < num_vfs; i++)
740d29a2488SOliver O'Halloran pnv_ioda_free_pe(&iov->vf_pe_arr[i]);
74137b59ef0SOliver O'Halloran
74237b59ef0SOliver O'Halloran return ret;
74337b59ef0SOliver O'Halloran }
74437b59ef0SOliver O'Halloran
pnv_pcibios_sriov_disable(struct pci_dev * pdev)74537b59ef0SOliver O'Halloran int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
74637b59ef0SOliver O'Halloran {
74737b59ef0SOliver O'Halloran pnv_pci_sriov_disable(pdev);
74837b59ef0SOliver O'Halloran
74937b59ef0SOliver O'Halloran /* Release PCI data */
75037b59ef0SOliver O'Halloran remove_sriov_vf_pdns(pdev);
75137b59ef0SOliver O'Halloran return 0;
75237b59ef0SOliver O'Halloran }
75337b59ef0SOliver O'Halloran
pnv_pcibios_sriov_enable(struct pci_dev * pdev,u16 num_vfs)75437b59ef0SOliver O'Halloran int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
75537b59ef0SOliver O'Halloran {
75637b59ef0SOliver O'Halloran /* Allocate PCI data */
75737b59ef0SOliver O'Halloran add_sriov_vf_pdns(pdev);
75837b59ef0SOliver O'Halloran
75937b59ef0SOliver O'Halloran return pnv_pci_sriov_enable(pdev, num_vfs);
76037b59ef0SOliver O'Halloran }
761