1 /* 2 * Copyright 2014-2016 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/module.h> 11 #include <asm/pci-bridge.h> 12 #include <asm/pnv-pci.h> 13 #include <asm/opal.h> 14 #include <misc/cxl.h> 15 16 #include "pci.h" 17 18 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) 19 { 20 struct pci_controller *hose = pci_bus_to_host(dev->bus); 21 22 return of_node_get(hose->dn); 23 } 24 EXPORT_SYMBOL(pnv_pci_get_phb_node); 25 26 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) 27 { 28 struct pci_controller *hose = pci_bus_to_host(dev->bus); 29 struct pnv_phb *phb = hose->private_data; 30 struct pnv_ioda_pe *pe; 31 int rc; 32 33 pe = pnv_ioda_get_pe(dev); 34 if (!pe) 35 return -ENODEV; 36 37 pe_info(pe, "Switching PHB to CXL\n"); 38 39 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); 40 if (rc == OPAL_UNSUPPORTED) 41 dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n"); 42 else if (rc) 43 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); 44 45 return rc; 46 } 47 EXPORT_SYMBOL(pnv_phb_to_cxl_mode); 48 49 /* Find PHB for cxl dev and allocate MSI hwirqs? 50 * Returns the absolute hardware IRQ number 51 */ 52 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) 53 { 54 struct pci_controller *hose = pci_bus_to_host(dev->bus); 55 struct pnv_phb *phb = hose->private_data; 56 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); 57 58 if (hwirq < 0) { 59 dev_warn(&dev->dev, "Failed to find a free MSI\n"); 60 return -ENOSPC; 61 } 62 63 return phb->msi_base + hwirq; 64 } 65 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); 66 67 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) 68 { 69 struct pci_controller *hose = pci_bus_to_host(dev->bus); 70 struct pnv_phb *phb = hose->private_data; 71 72 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); 73 } 74 EXPORT_SYMBOL(pnv_cxl_release_hwirqs); 75 76 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, 77 struct pci_dev *dev) 78 { 79 struct pci_controller *hose = pci_bus_to_host(dev->bus); 80 struct pnv_phb *phb = hose->private_data; 81 int i, hwirq; 82 83 for (i = 1; i < CXL_IRQ_RANGES; i++) { 84 if (!irqs->range[i]) 85 continue; 86 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", 87 i, irqs->offset[i], 88 irqs->range[i]); 89 hwirq = irqs->offset[i] - phb->msi_base; 90 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 91 irqs->range[i]); 92 } 93 } 94 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); 95 96 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, 97 struct pci_dev *dev, int num) 98 { 99 struct pci_controller *hose = pci_bus_to_host(dev->bus); 100 struct pnv_phb *phb = hose->private_data; 101 int i, hwirq, try; 102 103 memset(irqs, 0, sizeof(struct cxl_irq_ranges)); 104 105 /* 0 is reserved for the multiplexed PSL DSI interrupt */ 106 for (i = 1; i < CXL_IRQ_RANGES && num; i++) { 107 try = num; 108 while (try) { 109 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); 110 if (hwirq >= 0) 111 break; 112 try /= 2; 113 } 114 if (!try) 115 goto fail; 116 117 irqs->offset[i] = phb->msi_base + hwirq; 118 irqs->range[i] = try; 119 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", 120 i, irqs->offset[i], irqs->range[i]); 121 num -= try; 122 } 123 if (num) 124 goto fail; 125 126 return 0; 127 fail: 128 pnv_cxl_release_hwirq_ranges(irqs, dev); 129 return -ENOSPC; 130 } 131 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); 132 133 int pnv_cxl_get_irq_count(struct pci_dev *dev) 134 { 135 struct pci_controller *hose = pci_bus_to_host(dev->bus); 136 struct pnv_phb *phb = hose->private_data; 137 138 return phb->msi_bmp.irq_count; 139 } 140 EXPORT_SYMBOL(pnv_cxl_get_irq_count); 141 142 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, 143 unsigned int virq) 144 { 145 struct pci_controller *hose = pci_bus_to_host(dev->bus); 146 struct pnv_phb *phb = hose->private_data; 147 unsigned int xive_num = hwirq - phb->msi_base; 148 struct pnv_ioda_pe *pe; 149 int rc; 150 151 if (!(pe = pnv_ioda_get_pe(dev))) 152 return -ENODEV; 153 154 /* Assign XIVE to PE */ 155 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); 156 if (rc) { 157 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " 158 "hwirq 0x%x XIVE 0x%x PE\n", 159 pci_name(dev), rc, phb->msi_base, hwirq, xive_num); 160 return -EIO; 161 } 162 pnv_set_msi_irq_chip(phb, virq); 163 164 return 0; 165 } 166 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); 167 168 /* 169 * Sets flags and switches the controller ops to enable the cxl kernel api. 170 * Originally the cxl kernel API operated on a virtual PHB, but certain cards 171 * such as the Mellanox CX4 use a peer model instead and for these cards the 172 * cxl kernel api will operate on the real PHB. 173 */ 174 int pnv_cxl_enable_phb_kernel_api(struct pci_controller *hose, bool enable) 175 { 176 struct pnv_phb *phb = hose->private_data; 177 struct module *cxl_module; 178 179 if (!enable) { 180 /* 181 * Once cxl mode is enabled on the PHB, there is currently no 182 * known safe method to disable it again, and trying risks a 183 * checkstop. If we can find a way to safely disable cxl mode 184 * in the future we can revisit this, but for now the only sane 185 * thing to do is to refuse to disable cxl mode: 186 */ 187 return -EPERM; 188 } 189 190 /* 191 * Hold a reference to the cxl module since several PHB operations now 192 * depend on it, and it would be insane to allow it to be removed so 193 * long as we are in this mode (and since we can't safely disable this 194 * mode once enabled...). 195 */ 196 mutex_lock(&module_mutex); 197 cxl_module = find_module("cxl"); 198 if (cxl_module) 199 __module_get(cxl_module); 200 mutex_unlock(&module_mutex); 201 if (!cxl_module) 202 return -ENODEV; 203 204 phb->flags |= PNV_PHB_FLAG_CXL; 205 hose->controller_ops = pnv_cxl_cx4_ioda_controller_ops; 206 207 return 0; 208 } 209 EXPORT_SYMBOL_GPL(pnv_cxl_enable_phb_kernel_api); 210 211 bool pnv_pci_on_cxl_phb(struct pci_dev *dev) 212 { 213 struct pci_controller *hose = pci_bus_to_host(dev->bus); 214 struct pnv_phb *phb = hose->private_data; 215 216 return !!(phb->flags & PNV_PHB_FLAG_CXL); 217 } 218 EXPORT_SYMBOL_GPL(pnv_pci_on_cxl_phb); 219 220 struct cxl_afu *pnv_cxl_phb_to_afu(struct pci_controller *hose) 221 { 222 struct pnv_phb *phb = hose->private_data; 223 224 return (struct cxl_afu *)phb->cxl_afu; 225 } 226 EXPORT_SYMBOL_GPL(pnv_cxl_phb_to_afu); 227 228 void pnv_cxl_phb_set_peer_afu(struct pci_dev *dev, struct cxl_afu *afu) 229 { 230 struct pci_controller *hose = pci_bus_to_host(dev->bus); 231 struct pnv_phb *phb = hose->private_data; 232 233 phb->cxl_afu = afu; 234 } 235 EXPORT_SYMBOL_GPL(pnv_cxl_phb_set_peer_afu); 236 237 /* 238 * In the peer cxl model, the XSL/PSL is physical function 0, and will be used 239 * by other functions on the device for memory access and interrupts. When the 240 * other functions are enabled we explicitly take a reference on the cxl 241 * function since they will use it, and allocate a default context associated 242 * with that function just like the vPHB model of the cxl kernel API. 243 */ 244 bool pnv_cxl_enable_device_hook(struct pci_dev *dev) 245 { 246 struct pci_controller *hose = pci_bus_to_host(dev->bus); 247 struct pnv_phb *phb = hose->private_data; 248 struct cxl_afu *afu = phb->cxl_afu; 249 250 if (!pnv_pci_enable_device_hook(dev)) 251 return false; 252 253 254 /* No special handling for the cxl function, which is always PF 0 */ 255 if (PCI_FUNC(dev->devfn) == 0) 256 return true; 257 258 if (!afu) { 259 dev_WARN(&dev->dev, "Attempted to enable function > 0 on CXL PHB without a peer AFU\n"); 260 return false; 261 } 262 263 dev_info(&dev->dev, "Enabling function on CXL enabled PHB with peer AFU\n"); 264 265 /* Make sure the peer AFU can't go away while this device is active */ 266 cxl_afu_get(afu); 267 268 return cxl_pci_associate_default_context(dev, afu); 269 } 270 271 void pnv_cxl_disable_device(struct pci_dev *dev) 272 { 273 struct pci_controller *hose = pci_bus_to_host(dev->bus); 274 struct pnv_phb *phb = hose->private_data; 275 struct cxl_afu *afu = phb->cxl_afu; 276 277 /* No special handling for cxl function: */ 278 if (PCI_FUNC(dev->devfn) == 0) 279 return; 280 281 cxl_pci_disable_device(dev); 282 cxl_afu_put(afu); 283 } 284