1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * OPAL IMC interface detection driver
4  * Supported on POWERNV platform
5  *
6  * Copyright	(C) 2017 Madhavan Srinivasan, IBM Corporation.
7  *		(C) 2017 Anju T Sudhakar, IBM Corporation.
8  *		(C) 2017 Hemant K Shaw, IBM Corporation.
9  */
10 #include <linux/kernel.h>
11 #include <linux/platform_device.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <linux/crash_dump.h>
16 #include <asm/opal.h>
17 #include <asm/io.h>
18 #include <asm/imc-pmu.h>
19 #include <asm/cputhreads.h>
20 #include <asm/debugfs.h>
21 
22 static struct dentry *imc_debugfs_parent;
23 
24 /* Helpers to export imc command and mode via debugfs */
25 static int imc_mem_get(void *data, u64 *val)
26 {
27 	*val = cpu_to_be64(*(u64 *)data);
28 	return 0;
29 }
30 
31 static int imc_mem_set(void *data, u64 val)
32 {
33 	*(u64 *)data = cpu_to_be64(val);
34 	return 0;
35 }
36 DEFINE_DEBUGFS_ATTRIBUTE(fops_imc_x64, imc_mem_get, imc_mem_set, "0x%016llx\n");
37 
38 static struct dentry *imc_debugfs_create_x64(const char *name, umode_t mode,
39 					     struct dentry *parent, u64  *value)
40 {
41 	return debugfs_create_file_unsafe(name, mode, parent,
42 					  value, &fops_imc_x64);
43 }
44 
45 /*
46  * export_imc_mode_and_cmd: Create a debugfs interface
47  *                     for imc_cmd and imc_mode
48  *                     for each node in the system.
49  *  imc_mode and imc_cmd can be changed by echo into
50  *  this interface.
51  */
52 static void export_imc_mode_and_cmd(struct device_node *node,
53 				    struct imc_pmu *pmu_ptr)
54 {
55 	static u64 loc, *imc_mode_addr, *imc_cmd_addr;
56 	int chip = 0, nid;
57 	char mode[16], cmd[16];
58 	u32 cb_offset;
59 
60 	imc_debugfs_parent = debugfs_create_dir("imc", powerpc_debugfs_root);
61 
62 	/*
63 	 * Return here, either because 'imc' directory already exists,
64 	 * Or failed to create a new one.
65 	 */
66 	if (!imc_debugfs_parent)
67 		return;
68 
69 	if (of_property_read_u32(node, "cb_offset", &cb_offset))
70 		cb_offset = IMC_CNTL_BLK_OFFSET;
71 
72 	for_each_node(nid) {
73 		loc = (u64)(pmu_ptr->mem_info[chip].vbase) + cb_offset;
74 		imc_mode_addr = (u64 *)(loc + IMC_CNTL_BLK_MODE_OFFSET);
75 		sprintf(mode, "imc_mode_%d", nid);
76 		if (!imc_debugfs_create_x64(mode, 0600, imc_debugfs_parent,
77 					    imc_mode_addr))
78 			goto err;
79 
80 		imc_cmd_addr = (u64 *)(loc + IMC_CNTL_BLK_CMD_OFFSET);
81 		sprintf(cmd, "imc_cmd_%d", nid);
82 		if (!imc_debugfs_create_x64(cmd, 0600, imc_debugfs_parent,
83 					    imc_cmd_addr))
84 			goto err;
85 		chip++;
86 	}
87 	return;
88 
89 err:
90 	debugfs_remove_recursive(imc_debugfs_parent);
91 }
92 
93 /*
94  * imc_get_mem_addr_nest: Function to get nest counter memory region
95  * for each chip
96  */
97 static int imc_get_mem_addr_nest(struct device_node *node,
98 				 struct imc_pmu *pmu_ptr,
99 				 u32 offset)
100 {
101 	int nr_chips = 0, i;
102 	u64 *base_addr_arr, baddr;
103 	u32 *chipid_arr;
104 
105 	nr_chips = of_property_count_u32_elems(node, "chip-id");
106 	if (nr_chips <= 0)
107 		return -ENODEV;
108 
109 	base_addr_arr = kcalloc(nr_chips, sizeof(*base_addr_arr), GFP_KERNEL);
110 	if (!base_addr_arr)
111 		return -ENOMEM;
112 
113 	chipid_arr = kcalloc(nr_chips, sizeof(*chipid_arr), GFP_KERNEL);
114 	if (!chipid_arr) {
115 		kfree(base_addr_arr);
116 		return -ENOMEM;
117 	}
118 
119 	if (of_property_read_u32_array(node, "chip-id", chipid_arr, nr_chips))
120 		goto error;
121 
122 	if (of_property_read_u64_array(node, "base-addr", base_addr_arr,
123 								nr_chips))
124 		goto error;
125 
126 	pmu_ptr->mem_info = kcalloc(nr_chips + 1, sizeof(*pmu_ptr->mem_info),
127 				    GFP_KERNEL);
128 	if (!pmu_ptr->mem_info)
129 		goto error;
130 
131 	for (i = 0; i < nr_chips; i++) {
132 		pmu_ptr->mem_info[i].id = chipid_arr[i];
133 		baddr = base_addr_arr[i] + offset;
134 		pmu_ptr->mem_info[i].vbase = phys_to_virt(baddr);
135 	}
136 
137 	pmu_ptr->imc_counter_mmaped = true;
138 	export_imc_mode_and_cmd(node, pmu_ptr);
139 	kfree(base_addr_arr);
140 	kfree(chipid_arr);
141 	return 0;
142 
143 error:
144 	kfree(base_addr_arr);
145 	kfree(chipid_arr);
146 	return -1;
147 }
148 
149 /*
150  * imc_pmu_create : Takes the parent device which is the pmu unit, pmu_index
151  *		    and domain as the inputs.
152  * Allocates memory for the struct imc_pmu, sets up its domain, size and offsets
153  */
154 static int imc_pmu_create(struct device_node *parent, int pmu_index, int domain)
155 {
156 	int ret = 0;
157 	struct imc_pmu *pmu_ptr;
158 	u32 offset;
159 
160 	/* memory for pmu */
161 	pmu_ptr = kzalloc(sizeof(*pmu_ptr), GFP_KERNEL);
162 	if (!pmu_ptr)
163 		return -ENOMEM;
164 
165 	/* Set the domain */
166 	pmu_ptr->domain = domain;
167 
168 	ret = of_property_read_u32(parent, "size", &pmu_ptr->counter_mem_size);
169 	if (ret) {
170 		ret = -EINVAL;
171 		goto free_pmu;
172 	}
173 
174 	if (!of_property_read_u32(parent, "offset", &offset)) {
175 		if (imc_get_mem_addr_nest(parent, pmu_ptr, offset)) {
176 			ret = -EINVAL;
177 			goto free_pmu;
178 		}
179 	}
180 
181 	/* Function to register IMC pmu */
182 	ret = init_imc_pmu(parent, pmu_ptr, pmu_index);
183 	if (ret) {
184 		pr_err("IMC PMU %s Register failed\n", pmu_ptr->pmu.name);
185 		kfree(pmu_ptr->pmu.name);
186 		if (pmu_ptr->domain == IMC_DOMAIN_NEST)
187 			kfree(pmu_ptr->mem_info);
188 		kfree(pmu_ptr);
189 		return ret;
190 	}
191 
192 	return 0;
193 
194 free_pmu:
195 	kfree(pmu_ptr);
196 	return ret;
197 }
198 
199 static void disable_nest_pmu_counters(void)
200 {
201 	int nid, cpu;
202 	const struct cpumask *l_cpumask;
203 
204 	get_online_cpus();
205 	for_each_node_with_cpus(nid) {
206 		l_cpumask = cpumask_of_node(nid);
207 		cpu = cpumask_first_and(l_cpumask, cpu_online_mask);
208 		if (cpu >= nr_cpu_ids)
209 			continue;
210 		opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
211 				       get_hard_smp_processor_id(cpu));
212 	}
213 	put_online_cpus();
214 }
215 
216 static void disable_core_pmu_counters(void)
217 {
218 	cpumask_t cores_map;
219 	int cpu, rc;
220 
221 	get_online_cpus();
222 	/* Disable the IMC Core functions */
223 	cores_map = cpu_online_cores_map();
224 	for_each_cpu(cpu, &cores_map) {
225 		rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
226 					    get_hard_smp_processor_id(cpu));
227 		if (rc)
228 			pr_err("%s: Failed to stop Core (cpu = %d)\n",
229 				__FUNCTION__, cpu);
230 	}
231 	put_online_cpus();
232 }
233 
234 int get_max_nest_dev(void)
235 {
236 	struct device_node *node;
237 	u32 pmu_units = 0, type;
238 
239 	for_each_compatible_node(node, NULL, IMC_DTB_UNIT_COMPAT) {
240 		if (of_property_read_u32(node, "type", &type))
241 			continue;
242 
243 		if (type == IMC_TYPE_CHIP)
244 			pmu_units++;
245 	}
246 
247 	return pmu_units;
248 }
249 
250 static int opal_imc_counters_probe(struct platform_device *pdev)
251 {
252 	struct device_node *imc_dev = pdev->dev.of_node;
253 	int pmu_count = 0, domain;
254 	bool core_imc_reg = false, thread_imc_reg = false;
255 	u32 type;
256 
257 	/*
258 	 * Check whether this is kdump kernel. If yes, force the engines to
259 	 * stop and return.
260 	 */
261 	if (is_kdump_kernel()) {
262 		disable_nest_pmu_counters();
263 		disable_core_pmu_counters();
264 		return -ENODEV;
265 	}
266 
267 	for_each_compatible_node(imc_dev, NULL, IMC_DTB_UNIT_COMPAT) {
268 		if (of_property_read_u32(imc_dev, "type", &type)) {
269 			pr_warn("IMC Device without type property\n");
270 			continue;
271 		}
272 
273 		switch (type) {
274 		case IMC_TYPE_CHIP:
275 			domain = IMC_DOMAIN_NEST;
276 			break;
277 		case IMC_TYPE_CORE:
278 			domain =IMC_DOMAIN_CORE;
279 			break;
280 		case IMC_TYPE_THREAD:
281 			domain = IMC_DOMAIN_THREAD;
282 			break;
283 		case IMC_TYPE_TRACE:
284 			domain = IMC_DOMAIN_TRACE;
285 			break;
286 		default:
287 			pr_warn("IMC Unknown Device type \n");
288 			domain = -1;
289 			break;
290 		}
291 
292 		if (!imc_pmu_create(imc_dev, pmu_count, domain)) {
293 			if (domain == IMC_DOMAIN_NEST)
294 				pmu_count++;
295 			if (domain == IMC_DOMAIN_CORE)
296 				core_imc_reg = true;
297 			if (domain == IMC_DOMAIN_THREAD)
298 				thread_imc_reg = true;
299 		}
300 	}
301 
302 	/* If none of the nest units are registered, remove debugfs interface */
303 	if (pmu_count == 0)
304 		debugfs_remove_recursive(imc_debugfs_parent);
305 
306 	/* If core imc is not registered, unregister thread-imc */
307 	if (!core_imc_reg && thread_imc_reg)
308 		unregister_thread_imc();
309 
310 	return 0;
311 }
312 
313 static void opal_imc_counters_shutdown(struct platform_device *pdev)
314 {
315 	/*
316 	 * Function only stops the engines which is bare minimum.
317 	 * TODO: Need to handle proper memory cleanup and pmu
318 	 * unregister.
319 	 */
320 	disable_nest_pmu_counters();
321 	disable_core_pmu_counters();
322 }
323 
324 static const struct of_device_id opal_imc_match[] = {
325 	{ .compatible = IMC_DTB_COMPAT },
326 	{},
327 };
328 
329 static struct platform_driver opal_imc_driver = {
330 	.driver = {
331 		.name = "opal-imc-counters",
332 		.of_match_table = opal_imc_match,
333 	},
334 	.probe = opal_imc_counters_probe,
335 	.shutdown = opal_imc_counters_shutdown,
336 };
337 
338 builtin_platform_driver(opal_imc_driver);
339