1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV cpuidle code 4 * 5 * Copyright 2015 IBM Corp. 6 */ 7 8 #include <linux/types.h> 9 #include <linux/mm.h> 10 #include <linux/slab.h> 11 #include <linux/of.h> 12 #include <linux/device.h> 13 #include <linux/cpu.h> 14 15 #include <asm/asm-prototypes.h> 16 #include <asm/firmware.h> 17 #include <asm/interrupt.h> 18 #include <asm/machdep.h> 19 #include <asm/opal.h> 20 #include <asm/cputhreads.h> 21 #include <asm/cpuidle.h> 22 #include <asm/code-patching.h> 23 #include <asm/smp.h> 24 #include <asm/runlatch.h> 25 #include <asm/dbell.h> 26 27 #include "powernv.h" 28 #include "subcore.h" 29 30 /* Power ISA 3.0 allows for stop states 0x0 - 0xF */ 31 #define MAX_STOP_STATE 0xF 32 33 #define P9_STOP_SPR_MSR 2000 34 #define P9_STOP_SPR_PSSCR 855 35 36 static u32 supported_cpuidle_states; 37 struct pnv_idle_states_t *pnv_idle_states; 38 int nr_pnv_idle_states; 39 40 /* 41 * The default stop state that will be used by ppc_md.power_save 42 * function on platforms that support stop instruction. 43 */ 44 static u64 pnv_default_stop_val; 45 static u64 pnv_default_stop_mask; 46 static bool default_stop_found; 47 48 /* 49 * First stop state levels when SPR and TB loss can occur. 50 */ 51 static u64 pnv_first_tb_loss_level = MAX_STOP_STATE + 1; 52 static u64 deep_spr_loss_state = MAX_STOP_STATE + 1; 53 54 /* 55 * psscr value and mask of the deepest stop idle state. 56 * Used when a cpu is offlined. 57 */ 58 static u64 pnv_deepest_stop_psscr_val; 59 static u64 pnv_deepest_stop_psscr_mask; 60 static u64 pnv_deepest_stop_flag; 61 static bool deepest_stop_found; 62 63 static unsigned long power7_offline_type; 64 65 static int pnv_save_sprs_for_deep_states(void) 66 { 67 int cpu; 68 int rc; 69 70 /* 71 * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across 72 * all cpus at boot. Get these reg values of current cpu and use the 73 * same across all cpus. 74 */ 75 uint64_t lpcr_val = mfspr(SPRN_LPCR); 76 uint64_t hid0_val = mfspr(SPRN_HID0); 77 uint64_t hmeer_val = mfspr(SPRN_HMEER); 78 uint64_t msr_val = MSR_IDLE; 79 uint64_t psscr_val = pnv_deepest_stop_psscr_val; 80 81 for_each_present_cpu(cpu) { 82 uint64_t pir = get_hard_smp_processor_id(cpu); 83 uint64_t hsprg0_val = (uint64_t)paca_ptrs[cpu]; 84 85 rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); 86 if (rc != 0) 87 return rc; 88 89 rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 90 if (rc != 0) 91 return rc; 92 93 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 94 rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); 95 if (rc) 96 return rc; 97 98 rc = opal_slw_set_reg(pir, 99 P9_STOP_SPR_PSSCR, psscr_val); 100 101 if (rc) 102 return rc; 103 } 104 105 /* HIDs are per core registers */ 106 if (cpu_thread_in_core(cpu) == 0) { 107 108 rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); 109 if (rc != 0) 110 return rc; 111 112 rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); 113 if (rc != 0) 114 return rc; 115 116 /* Only p8 needs to set extra HID regiters */ 117 if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 118 uint64_t hid1_val = mfspr(SPRN_HID1); 119 uint64_t hid4_val = mfspr(SPRN_HID4); 120 uint64_t hid5_val = mfspr(SPRN_HID5); 121 122 rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); 123 if (rc != 0) 124 return rc; 125 126 rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); 127 if (rc != 0) 128 return rc; 129 130 rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); 131 if (rc != 0) 132 return rc; 133 } 134 } 135 } 136 137 return 0; 138 } 139 140 u32 pnv_get_supported_cpuidle_states(void) 141 { 142 return supported_cpuidle_states; 143 } 144 EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states); 145 146 static void pnv_fastsleep_workaround_apply(void *info) 147 148 { 149 int cpu = smp_processor_id(); 150 int rc; 151 int *err = info; 152 153 if (cpu_first_thread_sibling(cpu) != cpu) 154 return; 155 156 rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 157 OPAL_CONFIG_IDLE_APPLY); 158 if (rc) 159 *err = 1; 160 } 161 162 static bool power7_fastsleep_workaround_entry = true; 163 static bool power7_fastsleep_workaround_exit = true; 164 165 /* 166 * Used to store fastsleep workaround state 167 * 0 - Workaround applied/undone at fastsleep entry/exit path (Default) 168 * 1 - Workaround applied once, never undone. 169 */ 170 static u8 fastsleep_workaround_applyonce; 171 172 static ssize_t show_fastsleep_workaround_applyonce(struct device *dev, 173 struct device_attribute *attr, char *buf) 174 { 175 return sprintf(buf, "%u\n", fastsleep_workaround_applyonce); 176 } 177 178 static ssize_t store_fastsleep_workaround_applyonce(struct device *dev, 179 struct device_attribute *attr, const char *buf, 180 size_t count) 181 { 182 int err; 183 u8 val; 184 185 if (kstrtou8(buf, 0, &val) || val != 1) 186 return -EINVAL; 187 188 if (fastsleep_workaround_applyonce == 1) 189 return count; 190 191 /* 192 * fastsleep_workaround_applyonce = 1 implies 193 * fastsleep workaround needs to be left in 'applied' state on all 194 * the cores. Do this by- 195 * 1. Disable the 'undo' workaround in fastsleep exit path 196 * 2. Sendi IPIs to all the cores which have at least one online thread 197 * 3. Disable the 'apply' workaround in fastsleep entry path 198 * 199 * There is no need to send ipi to cores which have all threads 200 * offlined, as last thread of the core entering fastsleep or deeper 201 * state would have applied workaround. 202 */ 203 power7_fastsleep_workaround_exit = false; 204 205 cpus_read_lock(); 206 on_each_cpu(pnv_fastsleep_workaround_apply, &err, 1); 207 cpus_read_unlock(); 208 if (err) { 209 pr_err("fastsleep_workaround_applyonce change failed while running pnv_fastsleep_workaround_apply"); 210 goto fail; 211 } 212 213 power7_fastsleep_workaround_entry = false; 214 215 fastsleep_workaround_applyonce = 1; 216 217 return count; 218 fail: 219 return -EIO; 220 } 221 222 static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600, 223 show_fastsleep_workaround_applyonce, 224 store_fastsleep_workaround_applyonce); 225 226 static inline void atomic_start_thread_idle(void) 227 { 228 int cpu = raw_smp_processor_id(); 229 int first = cpu_first_thread_sibling(cpu); 230 int thread_nr = cpu_thread_in_core(cpu); 231 unsigned long *state = &paca_ptrs[first]->idle_state; 232 233 clear_bit(thread_nr, state); 234 } 235 236 static inline void atomic_stop_thread_idle(void) 237 { 238 int cpu = raw_smp_processor_id(); 239 int first = cpu_first_thread_sibling(cpu); 240 int thread_nr = cpu_thread_in_core(cpu); 241 unsigned long *state = &paca_ptrs[first]->idle_state; 242 243 set_bit(thread_nr, state); 244 } 245 246 static inline void atomic_lock_thread_idle(void) 247 { 248 int cpu = raw_smp_processor_id(); 249 int first = cpu_first_thread_sibling(cpu); 250 unsigned long *state = &paca_ptrs[first]->idle_state; 251 252 while (unlikely(test_and_set_bit_lock(NR_PNV_CORE_IDLE_LOCK_BIT, state))) 253 barrier(); 254 } 255 256 static inline void atomic_unlock_and_stop_thread_idle(void) 257 { 258 int cpu = raw_smp_processor_id(); 259 int first = cpu_first_thread_sibling(cpu); 260 unsigned long thread = 1UL << cpu_thread_in_core(cpu); 261 unsigned long *state = &paca_ptrs[first]->idle_state; 262 u64 s = READ_ONCE(*state); 263 u64 new, tmp; 264 265 BUG_ON(!(s & PNV_CORE_IDLE_LOCK_BIT)); 266 BUG_ON(s & thread); 267 268 again: 269 new = (s | thread) & ~PNV_CORE_IDLE_LOCK_BIT; 270 tmp = cmpxchg(state, s, new); 271 if (unlikely(tmp != s)) { 272 s = tmp; 273 goto again; 274 } 275 } 276 277 static inline void atomic_unlock_thread_idle(void) 278 { 279 int cpu = raw_smp_processor_id(); 280 int first = cpu_first_thread_sibling(cpu); 281 unsigned long *state = &paca_ptrs[first]->idle_state; 282 283 BUG_ON(!test_bit(NR_PNV_CORE_IDLE_LOCK_BIT, state)); 284 clear_bit_unlock(NR_PNV_CORE_IDLE_LOCK_BIT, state); 285 } 286 287 /* P7 and P8 */ 288 struct p7_sprs { 289 /* per core */ 290 u64 tscr; 291 u64 worc; 292 293 /* per subcore */ 294 u64 sdr1; 295 u64 rpr; 296 297 /* per thread */ 298 u64 lpcr; 299 u64 hfscr; 300 u64 fscr; 301 u64 purr; 302 u64 spurr; 303 u64 dscr; 304 u64 wort; 305 306 /* per thread SPRs that get lost in shallow states */ 307 u64 amr; 308 u64 iamr; 309 u64 uamor; 310 /* amor is restored to constant ~0 */ 311 }; 312 313 static unsigned long power7_idle_insn(unsigned long type) 314 { 315 int cpu = raw_smp_processor_id(); 316 int first = cpu_first_thread_sibling(cpu); 317 unsigned long *state = &paca_ptrs[first]->idle_state; 318 unsigned long thread = 1UL << cpu_thread_in_core(cpu); 319 unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 320 unsigned long srr1; 321 bool full_winkle; 322 struct p7_sprs sprs = {}; /* avoid false use-uninitialised */ 323 bool sprs_saved = false; 324 int rc; 325 326 if (unlikely(type != PNV_THREAD_NAP)) { 327 atomic_lock_thread_idle(); 328 329 BUG_ON(!(*state & thread)); 330 *state &= ~thread; 331 332 if (power7_fastsleep_workaround_entry) { 333 if ((*state & core_thread_mask) == 0) { 334 rc = opal_config_cpu_idle_state( 335 OPAL_CONFIG_IDLE_FASTSLEEP, 336 OPAL_CONFIG_IDLE_APPLY); 337 BUG_ON(rc); 338 } 339 } 340 341 if (type == PNV_THREAD_WINKLE) { 342 sprs.tscr = mfspr(SPRN_TSCR); 343 sprs.worc = mfspr(SPRN_WORC); 344 345 sprs.sdr1 = mfspr(SPRN_SDR1); 346 sprs.rpr = mfspr(SPRN_RPR); 347 348 sprs.lpcr = mfspr(SPRN_LPCR); 349 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 350 sprs.hfscr = mfspr(SPRN_HFSCR); 351 sprs.fscr = mfspr(SPRN_FSCR); 352 } 353 sprs.purr = mfspr(SPRN_PURR); 354 sprs.spurr = mfspr(SPRN_SPURR); 355 sprs.dscr = mfspr(SPRN_DSCR); 356 sprs.wort = mfspr(SPRN_WORT); 357 358 sprs_saved = true; 359 360 /* 361 * Increment winkle counter and set all winkle bits if 362 * all threads are winkling. This allows wakeup side to 363 * distinguish between fast sleep and winkle state 364 * loss. Fast sleep still has to resync the timebase so 365 * this may not be a really big win. 366 */ 367 *state += 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 368 if ((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) 369 >> PNV_CORE_IDLE_WINKLE_COUNT_SHIFT 370 == threads_per_core) 371 *state |= PNV_CORE_IDLE_THREAD_WINKLE_BITS; 372 WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 373 } 374 375 atomic_unlock_thread_idle(); 376 } 377 378 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 379 sprs.amr = mfspr(SPRN_AMR); 380 sprs.iamr = mfspr(SPRN_IAMR); 381 sprs.uamor = mfspr(SPRN_UAMOR); 382 } 383 384 local_paca->thread_idle_state = type; 385 srr1 = isa206_idle_insn_mayloss(type); /* go idle */ 386 local_paca->thread_idle_state = PNV_THREAD_RUNNING; 387 388 WARN_ON_ONCE(!srr1); 389 WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 390 391 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 392 if ((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS) { 393 /* 394 * We don't need an isync after the mtsprs here because 395 * the upcoming mtmsrd is execution synchronizing. 396 */ 397 mtspr(SPRN_AMR, sprs.amr); 398 mtspr(SPRN_IAMR, sprs.iamr); 399 mtspr(SPRN_AMOR, ~0); 400 mtspr(SPRN_UAMOR, sprs.uamor); 401 } 402 } 403 404 if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 405 hmi_exception_realmode(NULL); 406 407 if (likely((srr1 & SRR1_WAKESTATE) != SRR1_WS_HVLOSS)) { 408 if (unlikely(type != PNV_THREAD_NAP)) { 409 atomic_lock_thread_idle(); 410 if (type == PNV_THREAD_WINKLE) { 411 WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 412 *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 413 *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); 414 } 415 atomic_unlock_and_stop_thread_idle(); 416 } 417 return srr1; 418 } 419 420 /* HV state loss */ 421 BUG_ON(type == PNV_THREAD_NAP); 422 423 atomic_lock_thread_idle(); 424 425 full_winkle = false; 426 if (type == PNV_THREAD_WINKLE) { 427 WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 428 *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 429 if (*state & (thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT)) { 430 *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); 431 full_winkle = true; 432 BUG_ON(!sprs_saved); 433 } 434 } 435 436 WARN_ON(*state & thread); 437 438 if ((*state & core_thread_mask) != 0) 439 goto core_woken; 440 441 /* Per-core SPRs */ 442 if (full_winkle) { 443 mtspr(SPRN_TSCR, sprs.tscr); 444 mtspr(SPRN_WORC, sprs.worc); 445 } 446 447 if (power7_fastsleep_workaround_exit) { 448 rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 449 OPAL_CONFIG_IDLE_UNDO); 450 BUG_ON(rc); 451 } 452 453 /* TB */ 454 if (opal_resync_timebase() != OPAL_SUCCESS) 455 BUG(); 456 457 core_woken: 458 if (!full_winkle) 459 goto subcore_woken; 460 461 if ((*state & local_paca->subcore_sibling_mask) != 0) 462 goto subcore_woken; 463 464 /* Per-subcore SPRs */ 465 mtspr(SPRN_SDR1, sprs.sdr1); 466 mtspr(SPRN_RPR, sprs.rpr); 467 468 subcore_woken: 469 /* 470 * isync after restoring shared SPRs and before unlocking. Unlock 471 * only contains hwsync which does not necessarily do the right 472 * thing for SPRs. 473 */ 474 isync(); 475 atomic_unlock_and_stop_thread_idle(); 476 477 /* Fast sleep does not lose SPRs */ 478 if (!full_winkle) 479 return srr1; 480 481 /* Per-thread SPRs */ 482 mtspr(SPRN_LPCR, sprs.lpcr); 483 if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 484 mtspr(SPRN_HFSCR, sprs.hfscr); 485 mtspr(SPRN_FSCR, sprs.fscr); 486 } 487 mtspr(SPRN_PURR, sprs.purr); 488 mtspr(SPRN_SPURR, sprs.spurr); 489 mtspr(SPRN_DSCR, sprs.dscr); 490 mtspr(SPRN_WORT, sprs.wort); 491 492 mtspr(SPRN_SPRG3, local_paca->sprg_vdso); 493 494 #ifdef CONFIG_PPC_64S_HASH_MMU 495 /* 496 * The SLB has to be restored here, but it sometimes still 497 * contains entries, so the __ variant must be used to prevent 498 * multi hits. 499 */ 500 __slb_restore_bolted_realmode(); 501 #endif 502 503 return srr1; 504 } 505 506 extern unsigned long idle_kvm_start_guest(unsigned long srr1); 507 508 #ifdef CONFIG_HOTPLUG_CPU 509 static unsigned long power7_offline(void) 510 { 511 unsigned long srr1; 512 513 mtmsr(MSR_IDLE); 514 515 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 516 /* Tell KVM we're entering idle. */ 517 /******************************************************/ 518 /* N O T E W E L L ! ! ! N O T E W E L L */ 519 /* The following store to HSTATE_HWTHREAD_STATE(r13) */ 520 /* MUST occur in real mode, i.e. with the MMU off, */ 521 /* and the MMU must stay off until we clear this flag */ 522 /* and test HSTATE_HWTHREAD_REQ(r13) in */ 523 /* pnv_powersave_wakeup in this file. */ 524 /* The reason is that another thread can switch the */ 525 /* MMU to a guest context whenever this flag is set */ 526 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ 527 /* that would potentially cause this thread to start */ 528 /* executing instructions from guest memory in */ 529 /* hypervisor mode, leading to a host crash or data */ 530 /* corruption, or worse. */ 531 /******************************************************/ 532 local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_IDLE; 533 #endif 534 535 __ppc64_runlatch_off(); 536 srr1 = power7_idle_insn(power7_offline_type); 537 __ppc64_runlatch_on(); 538 539 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 540 local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_KERNEL; 541 /* Order setting hwthread_state vs. testing hwthread_req */ 542 smp_mb(); 543 if (local_paca->kvm_hstate.hwthread_req) 544 srr1 = idle_kvm_start_guest(srr1); 545 #endif 546 547 mtmsr(MSR_KERNEL); 548 549 return srr1; 550 } 551 #endif 552 553 void power7_idle_type(unsigned long type) 554 { 555 unsigned long srr1; 556 557 if (!prep_irq_for_idle_irqsoff()) 558 return; 559 560 mtmsr(MSR_IDLE); 561 __ppc64_runlatch_off(); 562 srr1 = power7_idle_insn(type); 563 __ppc64_runlatch_on(); 564 mtmsr(MSR_KERNEL); 565 566 fini_irq_for_idle_irqsoff(); 567 irq_set_pending_from_srr1(srr1); 568 } 569 570 static void power7_idle(void) 571 { 572 if (!powersave_nap) 573 return; 574 575 power7_idle_type(PNV_THREAD_NAP); 576 } 577 578 struct p9_sprs { 579 /* per core */ 580 u64 ptcr; 581 u64 rpr; 582 u64 tscr; 583 u64 ldbar; 584 585 /* per thread */ 586 u64 lpcr; 587 u64 hfscr; 588 u64 fscr; 589 u64 pid; 590 u64 purr; 591 u64 spurr; 592 u64 dscr; 593 u64 ciabr; 594 595 u64 mmcra; 596 u32 mmcr0; 597 u32 mmcr1; 598 u64 mmcr2; 599 600 /* per thread SPRs that get lost in shallow states */ 601 u64 amr; 602 u64 iamr; 603 u64 amor; 604 u64 uamor; 605 }; 606 607 static unsigned long power9_idle_stop(unsigned long psscr) 608 { 609 int cpu = raw_smp_processor_id(); 610 int first = cpu_first_thread_sibling(cpu); 611 unsigned long *state = &paca_ptrs[first]->idle_state; 612 unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 613 unsigned long srr1; 614 unsigned long pls; 615 unsigned long mmcr0 = 0; 616 unsigned long mmcra = 0; 617 struct p9_sprs sprs = {}; /* avoid false used-uninitialised */ 618 bool sprs_saved = false; 619 620 if (!(psscr & (PSSCR_EC|PSSCR_ESL))) { 621 /* EC=ESL=0 case */ 622 623 /* 624 * Wake synchronously. SRESET via xscom may still cause 625 * a 0x100 powersave wakeup with SRR1 reason! 626 */ 627 srr1 = isa300_idle_stop_noloss(psscr); /* go idle */ 628 if (likely(!srr1)) 629 return 0; 630 631 /* 632 * Registers not saved, can't recover! 633 * This would be a hardware bug 634 */ 635 BUG_ON((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS); 636 637 goto out; 638 } 639 640 /* EC=ESL=1 case */ 641 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 642 if (cpu_has_feature(CPU_FTR_P9_TM_XER_SO_BUG)) { 643 local_paca->requested_psscr = psscr; 644 /* order setting requested_psscr vs testing dont_stop */ 645 smp_mb(); 646 if (atomic_read(&local_paca->dont_stop)) { 647 local_paca->requested_psscr = 0; 648 return 0; 649 } 650 } 651 #endif 652 653 if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { 654 /* 655 * POWER9 DD2 can incorrectly set PMAO when waking up 656 * after a state-loss idle. Saving and restoring MMCR0 657 * over idle is a workaround. 658 */ 659 mmcr0 = mfspr(SPRN_MMCR0); 660 } 661 662 if ((psscr & PSSCR_RL_MASK) >= deep_spr_loss_state) { 663 sprs.lpcr = mfspr(SPRN_LPCR); 664 sprs.hfscr = mfspr(SPRN_HFSCR); 665 sprs.fscr = mfspr(SPRN_FSCR); 666 sprs.pid = mfspr(SPRN_PID); 667 sprs.purr = mfspr(SPRN_PURR); 668 sprs.spurr = mfspr(SPRN_SPURR); 669 sprs.dscr = mfspr(SPRN_DSCR); 670 sprs.ciabr = mfspr(SPRN_CIABR); 671 672 sprs.mmcra = mfspr(SPRN_MMCRA); 673 sprs.mmcr0 = mfspr(SPRN_MMCR0); 674 sprs.mmcr1 = mfspr(SPRN_MMCR1); 675 sprs.mmcr2 = mfspr(SPRN_MMCR2); 676 677 sprs.ptcr = mfspr(SPRN_PTCR); 678 sprs.rpr = mfspr(SPRN_RPR); 679 sprs.tscr = mfspr(SPRN_TSCR); 680 if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) 681 sprs.ldbar = mfspr(SPRN_LDBAR); 682 683 sprs_saved = true; 684 685 atomic_start_thread_idle(); 686 } 687 688 sprs.amr = mfspr(SPRN_AMR); 689 sprs.iamr = mfspr(SPRN_IAMR); 690 sprs.uamor = mfspr(SPRN_UAMOR); 691 692 srr1 = isa300_idle_stop_mayloss(psscr); /* go idle */ 693 694 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 695 local_paca->requested_psscr = 0; 696 #endif 697 698 psscr = mfspr(SPRN_PSSCR); 699 700 WARN_ON_ONCE(!srr1); 701 WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 702 703 if ((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS) { 704 /* 705 * We don't need an isync after the mtsprs here because the 706 * upcoming mtmsrd is execution synchronizing. 707 */ 708 mtspr(SPRN_AMR, sprs.amr); 709 mtspr(SPRN_IAMR, sprs.iamr); 710 mtspr(SPRN_AMOR, ~0); 711 mtspr(SPRN_UAMOR, sprs.uamor); 712 713 /* 714 * Workaround for POWER9 DD2.0, if we lost resources, the ERAT 715 * might have been corrupted and needs flushing. We also need 716 * to reload MMCR0 (see mmcr0 comment above). 717 */ 718 if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { 719 asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT); 720 mtspr(SPRN_MMCR0, mmcr0); 721 } 722 723 /* 724 * DD2.2 and earlier need to set then clear bit 60 in MMCRA 725 * to ensure the PMU starts running. 726 */ 727 mmcra = mfspr(SPRN_MMCRA); 728 mmcra |= PPC_BIT(60); 729 mtspr(SPRN_MMCRA, mmcra); 730 mmcra &= ~PPC_BIT(60); 731 mtspr(SPRN_MMCRA, mmcra); 732 } 733 734 if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 735 hmi_exception_realmode(NULL); 736 737 /* 738 * On POWER9, SRR1 bits do not match exactly as expected. 739 * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so 740 * just always test PSSCR for SPR/TB state loss. 741 */ 742 pls = (psscr & PSSCR_PLS) >> PSSCR_PLS_SHIFT; 743 if (likely(pls < deep_spr_loss_state)) { 744 if (sprs_saved) 745 atomic_stop_thread_idle(); 746 goto out; 747 } 748 749 /* HV state loss */ 750 BUG_ON(!sprs_saved); 751 752 atomic_lock_thread_idle(); 753 754 if ((*state & core_thread_mask) != 0) 755 goto core_woken; 756 757 /* Per-core SPRs */ 758 mtspr(SPRN_PTCR, sprs.ptcr); 759 mtspr(SPRN_RPR, sprs.rpr); 760 mtspr(SPRN_TSCR, sprs.tscr); 761 762 if (pls >= pnv_first_tb_loss_level) { 763 /* TB loss */ 764 if (opal_resync_timebase() != OPAL_SUCCESS) 765 BUG(); 766 } 767 768 /* 769 * isync after restoring shared SPRs and before unlocking. Unlock 770 * only contains hwsync which does not necessarily do the right 771 * thing for SPRs. 772 */ 773 isync(); 774 775 core_woken: 776 atomic_unlock_and_stop_thread_idle(); 777 778 /* Per-thread SPRs */ 779 mtspr(SPRN_LPCR, sprs.lpcr); 780 mtspr(SPRN_HFSCR, sprs.hfscr); 781 mtspr(SPRN_FSCR, sprs.fscr); 782 mtspr(SPRN_PID, sprs.pid); 783 mtspr(SPRN_PURR, sprs.purr); 784 mtspr(SPRN_SPURR, sprs.spurr); 785 mtspr(SPRN_DSCR, sprs.dscr); 786 mtspr(SPRN_CIABR, sprs.ciabr); 787 788 mtspr(SPRN_MMCRA, sprs.mmcra); 789 mtspr(SPRN_MMCR0, sprs.mmcr0); 790 mtspr(SPRN_MMCR1, sprs.mmcr1); 791 mtspr(SPRN_MMCR2, sprs.mmcr2); 792 if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) 793 mtspr(SPRN_LDBAR, sprs.ldbar); 794 795 mtspr(SPRN_SPRG3, local_paca->sprg_vdso); 796 797 if (!radix_enabled()) 798 __slb_restore_bolted_realmode(); 799 800 out: 801 mtmsr(MSR_KERNEL); 802 803 return srr1; 804 } 805 806 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 807 /* 808 * This is used in working around bugs in thread reconfiguration 809 * on POWER9 (at least up to Nimbus DD2.2) relating to transactional 810 * memory and the way that XER[SO] is checkpointed. 811 * This function forces the core into SMT4 in order by asking 812 * all other threads not to stop, and sending a message to any 813 * that are in a stop state. 814 * Must be called with preemption disabled. 815 */ 816 void pnv_power9_force_smt4_catch(void) 817 { 818 int cpu, cpu0, thr; 819 int awake_threads = 1; /* this thread is awake */ 820 int poke_threads = 0; 821 int need_awake = threads_per_core; 822 823 cpu = smp_processor_id(); 824 cpu0 = cpu & ~(threads_per_core - 1); 825 for (thr = 0; thr < threads_per_core; ++thr) { 826 if (cpu != cpu0 + thr) 827 atomic_inc(&paca_ptrs[cpu0+thr]->dont_stop); 828 } 829 /* order setting dont_stop vs testing requested_psscr */ 830 smp_mb(); 831 for (thr = 0; thr < threads_per_core; ++thr) { 832 if (!paca_ptrs[cpu0+thr]->requested_psscr) 833 ++awake_threads; 834 else 835 poke_threads |= (1 << thr); 836 } 837 838 /* If at least 3 threads are awake, the core is in SMT4 already */ 839 if (awake_threads < need_awake) { 840 /* We have to wake some threads; we'll use msgsnd */ 841 for (thr = 0; thr < threads_per_core; ++thr) { 842 if (poke_threads & (1 << thr)) { 843 ppc_msgsnd_sync(); 844 ppc_msgsnd(PPC_DBELL_MSGTYPE, 0, 845 paca_ptrs[cpu0+thr]->hw_cpu_id); 846 } 847 } 848 /* now spin until at least 3 threads are awake */ 849 do { 850 for (thr = 0; thr < threads_per_core; ++thr) { 851 if ((poke_threads & (1 << thr)) && 852 !paca_ptrs[cpu0+thr]->requested_psscr) { 853 ++awake_threads; 854 poke_threads &= ~(1 << thr); 855 } 856 } 857 } while (awake_threads < need_awake); 858 } 859 } 860 EXPORT_SYMBOL_GPL(pnv_power9_force_smt4_catch); 861 862 void pnv_power9_force_smt4_release(void) 863 { 864 int cpu, cpu0, thr; 865 866 cpu = smp_processor_id(); 867 cpu0 = cpu & ~(threads_per_core - 1); 868 869 /* clear all the dont_stop flags */ 870 for (thr = 0; thr < threads_per_core; ++thr) { 871 if (cpu != cpu0 + thr) 872 atomic_dec(&paca_ptrs[cpu0+thr]->dont_stop); 873 } 874 } 875 EXPORT_SYMBOL_GPL(pnv_power9_force_smt4_release); 876 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 877 878 struct p10_sprs { 879 /* 880 * SPRs that get lost in shallow states: 881 * 882 * P10 loses CR, LR, CTR, FPSCR, VSCR, XER, TAR, SPRG2, and HSPRG1 883 * isa300 idle routines restore CR, LR. 884 * CTR is volatile 885 * idle thread doesn't use FP or VEC 886 * kernel doesn't use TAR 887 * HSPRG1 is only live in HV interrupt entry 888 * SPRG2 is only live in KVM guests, KVM handles it. 889 */ 890 }; 891 892 static unsigned long power10_idle_stop(unsigned long psscr) 893 { 894 int cpu = raw_smp_processor_id(); 895 int first = cpu_first_thread_sibling(cpu); 896 unsigned long *state = &paca_ptrs[first]->idle_state; 897 unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 898 unsigned long srr1; 899 unsigned long pls; 900 // struct p10_sprs sprs = {}; /* avoid false used-uninitialised */ 901 bool sprs_saved = false; 902 903 if (!(psscr & (PSSCR_EC|PSSCR_ESL))) { 904 /* EC=ESL=0 case */ 905 906 /* 907 * Wake synchronously. SRESET via xscom may still cause 908 * a 0x100 powersave wakeup with SRR1 reason! 909 */ 910 srr1 = isa300_idle_stop_noloss(psscr); /* go idle */ 911 if (likely(!srr1)) 912 return 0; 913 914 /* 915 * Registers not saved, can't recover! 916 * This would be a hardware bug 917 */ 918 BUG_ON((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS); 919 920 goto out; 921 } 922 923 /* EC=ESL=1 case */ 924 if ((psscr & PSSCR_RL_MASK) >= deep_spr_loss_state) { 925 /* XXX: save SPRs for deep state loss here. */ 926 927 sprs_saved = true; 928 929 atomic_start_thread_idle(); 930 } 931 932 srr1 = isa300_idle_stop_mayloss(psscr); /* go idle */ 933 934 psscr = mfspr(SPRN_PSSCR); 935 936 WARN_ON_ONCE(!srr1); 937 WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 938 939 if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 940 hmi_exception_realmode(NULL); 941 942 /* 943 * On POWER10, SRR1 bits do not match exactly as expected. 944 * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so 945 * just always test PSSCR for SPR/TB state loss. 946 */ 947 pls = (psscr & PSSCR_PLS) >> PSSCR_PLS_SHIFT; 948 if (likely(pls < deep_spr_loss_state)) { 949 if (sprs_saved) 950 atomic_stop_thread_idle(); 951 goto out; 952 } 953 954 /* HV state loss */ 955 BUG_ON(!sprs_saved); 956 957 atomic_lock_thread_idle(); 958 959 if ((*state & core_thread_mask) != 0) 960 goto core_woken; 961 962 /* XXX: restore per-core SPRs here */ 963 964 if (pls >= pnv_first_tb_loss_level) { 965 /* TB loss */ 966 if (opal_resync_timebase() != OPAL_SUCCESS) 967 BUG(); 968 } 969 970 /* 971 * isync after restoring shared SPRs and before unlocking. Unlock 972 * only contains hwsync which does not necessarily do the right 973 * thing for SPRs. 974 */ 975 isync(); 976 977 core_woken: 978 atomic_unlock_and_stop_thread_idle(); 979 980 /* XXX: restore per-thread SPRs here */ 981 982 if (!radix_enabled()) 983 __slb_restore_bolted_realmode(); 984 985 out: 986 mtmsr(MSR_KERNEL); 987 988 return srr1; 989 } 990 991 #ifdef CONFIG_HOTPLUG_CPU 992 static unsigned long arch300_offline_stop(unsigned long psscr) 993 { 994 unsigned long srr1; 995 996 if (cpu_has_feature(CPU_FTR_ARCH_31)) 997 srr1 = power10_idle_stop(psscr); 998 else 999 srr1 = power9_idle_stop(psscr); 1000 1001 return srr1; 1002 } 1003 #endif 1004 1005 void arch300_idle_type(unsigned long stop_psscr_val, 1006 unsigned long stop_psscr_mask) 1007 { 1008 unsigned long psscr; 1009 unsigned long srr1; 1010 1011 if (!prep_irq_for_idle_irqsoff()) 1012 return; 1013 1014 psscr = mfspr(SPRN_PSSCR); 1015 psscr = (psscr & ~stop_psscr_mask) | stop_psscr_val; 1016 1017 __ppc64_runlatch_off(); 1018 if (cpu_has_feature(CPU_FTR_ARCH_31)) 1019 srr1 = power10_idle_stop(psscr); 1020 else 1021 srr1 = power9_idle_stop(psscr); 1022 __ppc64_runlatch_on(); 1023 1024 fini_irq_for_idle_irqsoff(); 1025 1026 irq_set_pending_from_srr1(srr1); 1027 } 1028 1029 /* 1030 * Used for ppc_md.power_save which needs a function with no parameters 1031 */ 1032 static void arch300_idle(void) 1033 { 1034 arch300_idle_type(pnv_default_stop_val, pnv_default_stop_mask); 1035 } 1036 1037 #ifdef CONFIG_HOTPLUG_CPU 1038 1039 void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val) 1040 { 1041 u64 pir = get_hard_smp_processor_id(cpu); 1042 1043 mtspr(SPRN_LPCR, lpcr_val); 1044 1045 /* 1046 * Program the LPCR via stop-api only if the deepest stop state 1047 * can lose hypervisor context. 1048 */ 1049 if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) 1050 opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 1051 } 1052 1053 /* 1054 * pnv_cpu_offline: A function that puts the CPU into the deepest 1055 * available platform idle state on a CPU-Offline. 1056 * interrupts hard disabled and no lazy irq pending. 1057 */ 1058 unsigned long pnv_cpu_offline(unsigned int cpu) 1059 { 1060 unsigned long srr1; 1061 1062 __ppc64_runlatch_off(); 1063 1064 if (cpu_has_feature(CPU_FTR_ARCH_300) && deepest_stop_found) { 1065 unsigned long psscr; 1066 1067 psscr = mfspr(SPRN_PSSCR); 1068 psscr = (psscr & ~pnv_deepest_stop_psscr_mask) | 1069 pnv_deepest_stop_psscr_val; 1070 srr1 = arch300_offline_stop(psscr); 1071 } else if (cpu_has_feature(CPU_FTR_ARCH_206) && power7_offline_type) { 1072 srr1 = power7_offline(); 1073 } else { 1074 /* This is the fallback method. We emulate snooze */ 1075 while (!generic_check_cpu_restart(cpu)) { 1076 HMT_low(); 1077 HMT_very_low(); 1078 } 1079 srr1 = 0; 1080 HMT_medium(); 1081 } 1082 1083 __ppc64_runlatch_on(); 1084 1085 return srr1; 1086 } 1087 #endif 1088 1089 /* 1090 * Power ISA 3.0 idle initialization. 1091 * 1092 * POWER ISA 3.0 defines a new SPR Processor stop Status and Control 1093 * Register (PSSCR) to control idle behavior. 1094 * 1095 * PSSCR layout: 1096 * ---------------------------------------------------------- 1097 * | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | 1098 * ---------------------------------------------------------- 1099 * 0 4 41 42 43 44 48 54 56 60 1100 * 1101 * PSSCR key fields: 1102 * Bits 0:3 - Power-Saving Level Status (PLS). This field indicates the 1103 * lowest power-saving state the thread entered since stop instruction was 1104 * last executed. 1105 * 1106 * Bit 41 - Status Disable(SD) 1107 * 0 - Shows PLS entries 1108 * 1 - PLS entries are all 0 1109 * 1110 * Bit 42 - Enable State Loss 1111 * 0 - No state is lost irrespective of other fields 1112 * 1 - Allows state loss 1113 * 1114 * Bit 43 - Exit Criterion 1115 * 0 - Exit from power-save mode on any interrupt 1116 * 1 - Exit from power-save mode controlled by LPCR's PECE bits 1117 * 1118 * Bits 44:47 - Power-Saving Level Limit 1119 * This limits the power-saving level that can be entered into. 1120 * 1121 * Bits 60:63 - Requested Level 1122 * Used to specify which power-saving level must be entered on executing 1123 * stop instruction 1124 */ 1125 1126 int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags) 1127 { 1128 int err = 0; 1129 1130 /* 1131 * psscr_mask == 0xf indicates an older firmware. 1132 * Set remaining fields of psscr to the default values. 1133 * See NOTE above definition of PSSCR_HV_DEFAULT_VAL 1134 */ 1135 if (*psscr_mask == 0xf) { 1136 *psscr_val = *psscr_val | PSSCR_HV_DEFAULT_VAL; 1137 *psscr_mask = PSSCR_HV_DEFAULT_MASK; 1138 return err; 1139 } 1140 1141 /* 1142 * New firmware is expected to set the psscr_val bits correctly. 1143 * Validate that the following invariants are correctly maintained by 1144 * the new firmware. 1145 * - ESL bit value matches the EC bit value. 1146 * - ESL bit is set for all the deep stop states. 1147 */ 1148 if (GET_PSSCR_ESL(*psscr_val) != GET_PSSCR_EC(*psscr_val)) { 1149 err = ERR_EC_ESL_MISMATCH; 1150 } else if ((flags & OPAL_PM_LOSE_FULL_CONTEXT) && 1151 GET_PSSCR_ESL(*psscr_val) == 0) { 1152 err = ERR_DEEP_STATE_ESL_MISMATCH; 1153 } 1154 1155 return err; 1156 } 1157 1158 /* 1159 * pnv_arch300_idle_init: Initializes the default idle state, first 1160 * deep idle state and deepest idle state on 1161 * ISA 3.0 CPUs. 1162 * 1163 * @np: /ibm,opal/power-mgt device node 1164 * @flags: cpu-idle-state-flags array 1165 * @dt_idle_states: Number of idle state entries 1166 * Returns 0 on success 1167 */ 1168 static void __init pnv_arch300_idle_init(void) 1169 { 1170 u64 max_residency_ns = 0; 1171 int i; 1172 1173 /* stop is not really architected, we only have p9,p10 drivers */ 1174 if (!pvr_version_is(PVR_POWER10) && !pvr_version_is(PVR_POWER9)) 1175 return; 1176 1177 /* 1178 * pnv_deepest_stop_{val,mask} should be set to values corresponding to 1179 * the deepest stop state. 1180 * 1181 * pnv_default_stop_{val,mask} should be set to values corresponding to 1182 * the deepest loss-less (OPAL_PM_STOP_INST_FAST) stop state. 1183 */ 1184 pnv_first_tb_loss_level = MAX_STOP_STATE + 1; 1185 deep_spr_loss_state = MAX_STOP_STATE + 1; 1186 for (i = 0; i < nr_pnv_idle_states; i++) { 1187 int err; 1188 struct pnv_idle_states_t *state = &pnv_idle_states[i]; 1189 u64 psscr_rl = state->psscr_val & PSSCR_RL_MASK; 1190 1191 /* No deep loss driver implemented for POWER10 yet */ 1192 if (pvr_version_is(PVR_POWER10) && 1193 state->flags & (OPAL_PM_TIMEBASE_STOP|OPAL_PM_LOSE_FULL_CONTEXT)) 1194 continue; 1195 1196 if ((state->flags & OPAL_PM_TIMEBASE_STOP) && 1197 (pnv_first_tb_loss_level > psscr_rl)) 1198 pnv_first_tb_loss_level = psscr_rl; 1199 1200 if ((state->flags & OPAL_PM_LOSE_FULL_CONTEXT) && 1201 (deep_spr_loss_state > psscr_rl)) 1202 deep_spr_loss_state = psscr_rl; 1203 1204 /* 1205 * The idle code does not deal with TB loss occurring 1206 * in a shallower state than SPR loss, so force it to 1207 * behave like SPRs are lost if TB is lost. POWER9 would 1208 * never encouter this, but a POWER8 core would if it 1209 * implemented the stop instruction. So this is for forward 1210 * compatibility. 1211 */ 1212 if ((state->flags & OPAL_PM_TIMEBASE_STOP) && 1213 (deep_spr_loss_state > psscr_rl)) 1214 deep_spr_loss_state = psscr_rl; 1215 1216 err = validate_psscr_val_mask(&state->psscr_val, 1217 &state->psscr_mask, 1218 state->flags); 1219 if (err) { 1220 report_invalid_psscr_val(state->psscr_val, err); 1221 continue; 1222 } 1223 1224 state->valid = true; 1225 1226 if (max_residency_ns < state->residency_ns) { 1227 max_residency_ns = state->residency_ns; 1228 pnv_deepest_stop_psscr_val = state->psscr_val; 1229 pnv_deepest_stop_psscr_mask = state->psscr_mask; 1230 pnv_deepest_stop_flag = state->flags; 1231 deepest_stop_found = true; 1232 } 1233 1234 if (!default_stop_found && 1235 (state->flags & OPAL_PM_STOP_INST_FAST)) { 1236 pnv_default_stop_val = state->psscr_val; 1237 pnv_default_stop_mask = state->psscr_mask; 1238 default_stop_found = true; 1239 WARN_ON(state->flags & OPAL_PM_LOSE_FULL_CONTEXT); 1240 } 1241 } 1242 1243 if (unlikely(!default_stop_found)) { 1244 pr_warn("cpuidle-powernv: No suitable default stop state found. Disabling platform idle.\n"); 1245 } else { 1246 ppc_md.power_save = arch300_idle; 1247 pr_info("cpuidle-powernv: Default stop: psscr = 0x%016llx,mask=0x%016llx\n", 1248 pnv_default_stop_val, pnv_default_stop_mask); 1249 } 1250 1251 if (unlikely(!deepest_stop_found)) { 1252 pr_warn("cpuidle-powernv: No suitable stop state for CPU-Hotplug. Offlined CPUs will busy wait"); 1253 } else { 1254 pr_info("cpuidle-powernv: Deepest stop: psscr = 0x%016llx,mask=0x%016llx\n", 1255 pnv_deepest_stop_psscr_val, 1256 pnv_deepest_stop_psscr_mask); 1257 } 1258 1259 pr_info("cpuidle-powernv: First stop level that may lose SPRs = 0x%llx\n", 1260 deep_spr_loss_state); 1261 1262 pr_info("cpuidle-powernv: First stop level that may lose timebase = 0x%llx\n", 1263 pnv_first_tb_loss_level); 1264 } 1265 1266 static void __init pnv_disable_deep_states(void) 1267 { 1268 /* 1269 * The stop-api is unable to restore hypervisor 1270 * resources on wakeup from platform idle states which 1271 * lose full context. So disable such states. 1272 */ 1273 supported_cpuidle_states &= ~OPAL_PM_LOSE_FULL_CONTEXT; 1274 pr_warn("cpuidle-powernv: Disabling idle states that lose full context\n"); 1275 pr_warn("cpuidle-powernv: Idle power-savings, CPU-Hotplug affected\n"); 1276 1277 if (cpu_has_feature(CPU_FTR_ARCH_300) && 1278 (pnv_deepest_stop_flag & OPAL_PM_LOSE_FULL_CONTEXT)) { 1279 /* 1280 * Use the default stop state for CPU-Hotplug 1281 * if available. 1282 */ 1283 if (default_stop_found) { 1284 pnv_deepest_stop_psscr_val = pnv_default_stop_val; 1285 pnv_deepest_stop_psscr_mask = pnv_default_stop_mask; 1286 pr_warn("cpuidle-powernv: Offlined CPUs will stop with psscr = 0x%016llx\n", 1287 pnv_deepest_stop_psscr_val); 1288 } else { /* Fallback to snooze loop for CPU-Hotplug */ 1289 deepest_stop_found = false; 1290 pr_warn("cpuidle-powernv: Offlined CPUs will busy wait\n"); 1291 } 1292 } 1293 } 1294 1295 /* 1296 * Probe device tree for supported idle states 1297 */ 1298 static void __init pnv_probe_idle_states(void) 1299 { 1300 int i; 1301 1302 if (nr_pnv_idle_states < 0) { 1303 pr_warn("cpuidle-powernv: no idle states found in the DT\n"); 1304 return; 1305 } 1306 1307 if (cpu_has_feature(CPU_FTR_ARCH_300)) 1308 pnv_arch300_idle_init(); 1309 1310 for (i = 0; i < nr_pnv_idle_states; i++) 1311 supported_cpuidle_states |= pnv_idle_states[i].flags; 1312 } 1313 1314 /* 1315 * This function parses device-tree and populates all the information 1316 * into pnv_idle_states structure. It also sets up nr_pnv_idle_states 1317 * which is the number of cpuidle states discovered through device-tree. 1318 */ 1319 1320 static int pnv_parse_cpuidle_dt(void) 1321 { 1322 struct device_node *np; 1323 int nr_idle_states, i; 1324 int rc = 0; 1325 u32 *temp_u32; 1326 u64 *temp_u64; 1327 const char **temp_string; 1328 1329 np = of_find_node_by_path("/ibm,opal/power-mgt"); 1330 if (!np) { 1331 pr_warn("opal: PowerMgmt Node not found\n"); 1332 return -ENODEV; 1333 } 1334 nr_idle_states = of_property_count_u32_elems(np, 1335 "ibm,cpu-idle-state-flags"); 1336 1337 pnv_idle_states = kcalloc(nr_idle_states, sizeof(*pnv_idle_states), 1338 GFP_KERNEL); 1339 temp_u32 = kcalloc(nr_idle_states, sizeof(u32), GFP_KERNEL); 1340 temp_u64 = kcalloc(nr_idle_states, sizeof(u64), GFP_KERNEL); 1341 temp_string = kcalloc(nr_idle_states, sizeof(char *), GFP_KERNEL); 1342 1343 if (!(pnv_idle_states && temp_u32 && temp_u64 && temp_string)) { 1344 pr_err("Could not allocate memory for dt parsing\n"); 1345 rc = -ENOMEM; 1346 goto out; 1347 } 1348 1349 /* Read flags */ 1350 if (of_property_read_u32_array(np, "ibm,cpu-idle-state-flags", 1351 temp_u32, nr_idle_states)) { 1352 pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n"); 1353 rc = -EINVAL; 1354 goto out; 1355 } 1356 for (i = 0; i < nr_idle_states; i++) 1357 pnv_idle_states[i].flags = temp_u32[i]; 1358 1359 /* Read latencies */ 1360 if (of_property_read_u32_array(np, "ibm,cpu-idle-state-latencies-ns", 1361 temp_u32, nr_idle_states)) { 1362 pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-latencies-ns in DT\n"); 1363 rc = -EINVAL; 1364 goto out; 1365 } 1366 for (i = 0; i < nr_idle_states; i++) 1367 pnv_idle_states[i].latency_ns = temp_u32[i]; 1368 1369 /* Read residencies */ 1370 if (of_property_read_u32_array(np, "ibm,cpu-idle-state-residency-ns", 1371 temp_u32, nr_idle_states)) { 1372 pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-residency-ns in DT\n"); 1373 rc = -EINVAL; 1374 goto out; 1375 } 1376 for (i = 0; i < nr_idle_states; i++) 1377 pnv_idle_states[i].residency_ns = temp_u32[i]; 1378 1379 /* For power9 and later */ 1380 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 1381 /* Read pm_crtl_val */ 1382 if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr", 1383 temp_u64, nr_idle_states)) { 1384 pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n"); 1385 rc = -EINVAL; 1386 goto out; 1387 } 1388 for (i = 0; i < nr_idle_states; i++) 1389 pnv_idle_states[i].psscr_val = temp_u64[i]; 1390 1391 /* Read pm_crtl_mask */ 1392 if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr-mask", 1393 temp_u64, nr_idle_states)) { 1394 pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n"); 1395 rc = -EINVAL; 1396 goto out; 1397 } 1398 for (i = 0; i < nr_idle_states; i++) 1399 pnv_idle_states[i].psscr_mask = temp_u64[i]; 1400 } 1401 1402 /* 1403 * power8 specific properties ibm,cpu-idle-state-pmicr-mask and 1404 * ibm,cpu-idle-state-pmicr-val were never used and there is no 1405 * plan to use it in near future. Hence, not parsing these properties 1406 */ 1407 1408 if (of_property_read_string_array(np, "ibm,cpu-idle-state-names", 1409 temp_string, nr_idle_states) < 0) { 1410 pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-names in DT\n"); 1411 rc = -EINVAL; 1412 goto out; 1413 } 1414 for (i = 0; i < nr_idle_states; i++) 1415 strlcpy(pnv_idle_states[i].name, temp_string[i], 1416 PNV_IDLE_NAME_LEN); 1417 nr_pnv_idle_states = nr_idle_states; 1418 rc = 0; 1419 out: 1420 kfree(temp_u32); 1421 kfree(temp_u64); 1422 kfree(temp_string); 1423 return rc; 1424 } 1425 1426 static int __init pnv_init_idle_states(void) 1427 { 1428 int cpu; 1429 int rc = 0; 1430 1431 /* Set up PACA fields */ 1432 for_each_present_cpu(cpu) { 1433 struct paca_struct *p = paca_ptrs[cpu]; 1434 1435 p->idle_state = 0; 1436 if (cpu == cpu_first_thread_sibling(cpu)) 1437 p->idle_state = (1 << threads_per_core) - 1; 1438 1439 if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1440 /* P7/P8 nap */ 1441 p->thread_idle_state = PNV_THREAD_RUNNING; 1442 } else if (pvr_version_is(PVR_POWER9)) { 1443 /* P9 stop workarounds */ 1444 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 1445 p->requested_psscr = 0; 1446 atomic_set(&p->dont_stop, 0); 1447 #endif 1448 } 1449 } 1450 1451 /* In case we error out nr_pnv_idle_states will be zero */ 1452 nr_pnv_idle_states = 0; 1453 supported_cpuidle_states = 0; 1454 1455 if (cpuidle_disable != IDLE_NO_OVERRIDE) 1456 goto out; 1457 rc = pnv_parse_cpuidle_dt(); 1458 if (rc) 1459 return rc; 1460 pnv_probe_idle_states(); 1461 1462 if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1463 if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { 1464 power7_fastsleep_workaround_entry = false; 1465 power7_fastsleep_workaround_exit = false; 1466 } else { 1467 /* 1468 * OPAL_PM_SLEEP_ENABLED_ER1 is set. It indicates that 1469 * workaround is needed to use fastsleep. Provide sysfs 1470 * control to choose how this workaround has to be 1471 * applied. 1472 */ 1473 device_create_file(cpu_subsys.dev_root, 1474 &dev_attr_fastsleep_workaround_applyonce); 1475 } 1476 1477 update_subcore_sibling_mask(); 1478 1479 if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED) { 1480 ppc_md.power_save = power7_idle; 1481 power7_offline_type = PNV_THREAD_NAP; 1482 } 1483 1484 if ((supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED) && 1485 (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT)) 1486 power7_offline_type = PNV_THREAD_WINKLE; 1487 else if ((supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED) || 1488 (supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) 1489 power7_offline_type = PNV_THREAD_SLEEP; 1490 } 1491 1492 if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) { 1493 if (pnv_save_sprs_for_deep_states()) 1494 pnv_disable_deep_states(); 1495 } 1496 1497 out: 1498 return 0; 1499 } 1500 machine_subsys_initcall(powernv, pnv_init_idle_states); 1501