12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2d405a98cSShreyas B. Prabhu /* 3d405a98cSShreyas B. Prabhu * PowerNV cpuidle code 4d405a98cSShreyas B. Prabhu * 5d405a98cSShreyas B. Prabhu * Copyright 2015 IBM Corp. 6d405a98cSShreyas B. Prabhu */ 7d405a98cSShreyas B. Prabhu 8d405a98cSShreyas B. Prabhu #include <linux/types.h> 9d405a98cSShreyas B. Prabhu #include <linux/mm.h> 10d405a98cSShreyas B. Prabhu #include <linux/slab.h> 11d405a98cSShreyas B. Prabhu #include <linux/of.h> 125703d2f4SShreyas B. Prabhu #include <linux/device.h> 135703d2f4SShreyas B. Prabhu #include <linux/cpu.h> 14d405a98cSShreyas B. Prabhu 1510d91611SNicholas Piggin #include <asm/asm-prototypes.h> 16d405a98cSShreyas B. Prabhu #include <asm/firmware.h> 174bece972SMichael Ellerman #include <asm/machdep.h> 18d405a98cSShreyas B. Prabhu #include <asm/opal.h> 19d405a98cSShreyas B. Prabhu #include <asm/cputhreads.h> 20d405a98cSShreyas B. Prabhu #include <asm/cpuidle.h> 21d405a98cSShreyas B. Prabhu #include <asm/code-patching.h> 22d405a98cSShreyas B. Prabhu #include <asm/smp.h> 232201f994SNicholas Piggin #include <asm/runlatch.h> 247672691aSPaul Mackerras #include <asm/dbell.h> 25d405a98cSShreyas B. Prabhu 26d405a98cSShreyas B. Prabhu #include "powernv.h" 27d405a98cSShreyas B. Prabhu #include "subcore.h" 28d405a98cSShreyas B. Prabhu 29bcef83a0SShreyas B. Prabhu /* Power ISA 3.0 allows for stop states 0x0 - 0xF */ 30bcef83a0SShreyas B. Prabhu #define MAX_STOP_STATE 0xF 31bcef83a0SShreyas B. Prabhu 321e1601b3SAkshay Adiga #define P9_STOP_SPR_MSR 2000 331e1601b3SAkshay Adiga #define P9_STOP_SPR_PSSCR 855 341e1601b3SAkshay Adiga 35d405a98cSShreyas B. Prabhu static u32 supported_cpuidle_states; 369c7b185aSAkshay Adiga struct pnv_idle_states_t *pnv_idle_states; 379c7b185aSAkshay Adiga int nr_pnv_idle_states; 38d405a98cSShreyas B. Prabhu 391e1601b3SAkshay Adiga /* 401e1601b3SAkshay Adiga * The default stop state that will be used by ppc_md.power_save 411e1601b3SAkshay Adiga * function on platforms that support stop instruction. 421e1601b3SAkshay Adiga */ 431e1601b3SAkshay Adiga static u64 pnv_default_stop_val; 441e1601b3SAkshay Adiga static u64 pnv_default_stop_mask; 451e1601b3SAkshay Adiga static bool default_stop_found; 461e1601b3SAkshay Adiga 471e1601b3SAkshay Adiga /* 4810d91611SNicholas Piggin * First stop state levels when SPR and TB loss can occur. 491e1601b3SAkshay Adiga */ 5010d91611SNicholas Piggin static u64 pnv_first_tb_loss_level = MAX_STOP_STATE + 1; 51dcbbfa6bSPratik Rajesh Sampat static u64 deep_spr_loss_state = MAX_STOP_STATE + 1; 521e1601b3SAkshay Adiga 531e1601b3SAkshay Adiga /* 541e1601b3SAkshay Adiga * psscr value and mask of the deepest stop idle state. 551e1601b3SAkshay Adiga * Used when a cpu is offlined. 561e1601b3SAkshay Adiga */ 571e1601b3SAkshay Adiga static u64 pnv_deepest_stop_psscr_val; 581e1601b3SAkshay Adiga static u64 pnv_deepest_stop_psscr_mask; 59785a12afSGautham R. Shenoy static u64 pnv_deepest_stop_flag; 601e1601b3SAkshay Adiga static bool deepest_stop_found; 611e1601b3SAkshay Adiga 6210d91611SNicholas Piggin static unsigned long power7_offline_type; 6310d91611SNicholas Piggin 64bcef83a0SShreyas B. Prabhu static int pnv_save_sprs_for_deep_states(void) 65d405a98cSShreyas B. Prabhu { 66d405a98cSShreyas B. Prabhu int cpu; 67d405a98cSShreyas B. Prabhu int rc; 68d405a98cSShreyas B. Prabhu 69d405a98cSShreyas B. Prabhu /* 70446957baSAdam Buchbinder * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across 71d405a98cSShreyas B. Prabhu * all cpus at boot. Get these reg values of current cpu and use the 72446957baSAdam Buchbinder * same across all cpus. 73d405a98cSShreyas B. Prabhu */ 7424be85a2SGautham R. Shenoy uint64_t lpcr_val = mfspr(SPRN_LPCR); 75d405a98cSShreyas B. Prabhu uint64_t hid0_val = mfspr(SPRN_HID0); 76d405a98cSShreyas B. Prabhu uint64_t hmeer_val = mfspr(SPRN_HMEER); 771e1601b3SAkshay Adiga uint64_t msr_val = MSR_IDLE; 781e1601b3SAkshay Adiga uint64_t psscr_val = pnv_deepest_stop_psscr_val; 79d405a98cSShreyas B. Prabhu 80ac9816dcSAkshay Adiga for_each_present_cpu(cpu) { 81d405a98cSShreyas B. Prabhu uint64_t pir = get_hard_smp_processor_id(cpu); 82d2e60075SNicholas Piggin uint64_t hsprg0_val = (uint64_t)paca_ptrs[cpu]; 83d405a98cSShreyas B. Prabhu 84d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); 85d405a98cSShreyas B. Prabhu if (rc != 0) 86d405a98cSShreyas B. Prabhu return rc; 87d405a98cSShreyas B. Prabhu 88d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 89d405a98cSShreyas B. Prabhu if (rc != 0) 90d405a98cSShreyas B. Prabhu return rc; 91d405a98cSShreyas B. Prabhu 921e1601b3SAkshay Adiga if (cpu_has_feature(CPU_FTR_ARCH_300)) { 931e1601b3SAkshay Adiga rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); 941e1601b3SAkshay Adiga if (rc) 951e1601b3SAkshay Adiga return rc; 961e1601b3SAkshay Adiga 971e1601b3SAkshay Adiga rc = opal_slw_set_reg(pir, 981e1601b3SAkshay Adiga P9_STOP_SPR_PSSCR, psscr_val); 991e1601b3SAkshay Adiga 1001e1601b3SAkshay Adiga if (rc) 1011e1601b3SAkshay Adiga return rc; 1021e1601b3SAkshay Adiga } 1031e1601b3SAkshay Adiga 104d405a98cSShreyas B. Prabhu /* HIDs are per core registers */ 105d405a98cSShreyas B. Prabhu if (cpu_thread_in_core(cpu) == 0) { 106d405a98cSShreyas B. Prabhu 107d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); 108d405a98cSShreyas B. Prabhu if (rc != 0) 109d405a98cSShreyas B. Prabhu return rc; 110d405a98cSShreyas B. Prabhu 111d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); 112d405a98cSShreyas B. Prabhu if (rc != 0) 113d405a98cSShreyas B. Prabhu return rc; 114d405a98cSShreyas B. Prabhu 1151e1601b3SAkshay Adiga /* Only p8 needs to set extra HID regiters */ 1161e1601b3SAkshay Adiga if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1175c92fb1bSPratik Rajesh Sampat uint64_t hid1_val = mfspr(SPRN_HID1); 1185c92fb1bSPratik Rajesh Sampat uint64_t hid4_val = mfspr(SPRN_HID4); 1195c92fb1bSPratik Rajesh Sampat uint64_t hid5_val = mfspr(SPRN_HID5); 1201e1601b3SAkshay Adiga 121d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); 122d405a98cSShreyas B. Prabhu if (rc != 0) 123d405a98cSShreyas B. Prabhu return rc; 124d405a98cSShreyas B. Prabhu 125d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); 126d405a98cSShreyas B. Prabhu if (rc != 0) 127d405a98cSShreyas B. Prabhu return rc; 128d405a98cSShreyas B. Prabhu 129d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); 130d405a98cSShreyas B. Prabhu if (rc != 0) 131d405a98cSShreyas B. Prabhu return rc; 132d405a98cSShreyas B. Prabhu } 133d405a98cSShreyas B. Prabhu } 1341e1601b3SAkshay Adiga } 135d405a98cSShreyas B. Prabhu 136d405a98cSShreyas B. Prabhu return 0; 137d405a98cSShreyas B. Prabhu } 138d405a98cSShreyas B. Prabhu 139d405a98cSShreyas B. Prabhu u32 pnv_get_supported_cpuidle_states(void) 140d405a98cSShreyas B. Prabhu { 141d405a98cSShreyas B. Prabhu return supported_cpuidle_states; 142d405a98cSShreyas B. Prabhu } 143d405a98cSShreyas B. Prabhu EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states); 144d405a98cSShreyas B. Prabhu 1455703d2f4SShreyas B. Prabhu static void pnv_fastsleep_workaround_apply(void *info) 1465703d2f4SShreyas B. Prabhu 1475703d2f4SShreyas B. Prabhu { 1485703d2f4SShreyas B. Prabhu int rc; 1495703d2f4SShreyas B. Prabhu int *err = info; 1505703d2f4SShreyas B. Prabhu 1515703d2f4SShreyas B. Prabhu rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 1525703d2f4SShreyas B. Prabhu OPAL_CONFIG_IDLE_APPLY); 1535703d2f4SShreyas B. Prabhu if (rc) 1545703d2f4SShreyas B. Prabhu *err = 1; 1555703d2f4SShreyas B. Prabhu } 1565703d2f4SShreyas B. Prabhu 15710d91611SNicholas Piggin static bool power7_fastsleep_workaround_entry = true; 15810d91611SNicholas Piggin static bool power7_fastsleep_workaround_exit = true; 15910d91611SNicholas Piggin 1605703d2f4SShreyas B. Prabhu /* 1615703d2f4SShreyas B. Prabhu * Used to store fastsleep workaround state 1625703d2f4SShreyas B. Prabhu * 0 - Workaround applied/undone at fastsleep entry/exit path (Default) 1635703d2f4SShreyas B. Prabhu * 1 - Workaround applied once, never undone. 1645703d2f4SShreyas B. Prabhu */ 1655703d2f4SShreyas B. Prabhu static u8 fastsleep_workaround_applyonce; 1665703d2f4SShreyas B. Prabhu 1675703d2f4SShreyas B. Prabhu static ssize_t show_fastsleep_workaround_applyonce(struct device *dev, 1685703d2f4SShreyas B. Prabhu struct device_attribute *attr, char *buf) 1695703d2f4SShreyas B. Prabhu { 1705703d2f4SShreyas B. Prabhu return sprintf(buf, "%u\n", fastsleep_workaround_applyonce); 1715703d2f4SShreyas B. Prabhu } 1725703d2f4SShreyas B. Prabhu 1735703d2f4SShreyas B. Prabhu static ssize_t store_fastsleep_workaround_applyonce(struct device *dev, 1745703d2f4SShreyas B. Prabhu struct device_attribute *attr, const char *buf, 1755703d2f4SShreyas B. Prabhu size_t count) 1765703d2f4SShreyas B. Prabhu { 1775703d2f4SShreyas B. Prabhu cpumask_t primary_thread_mask; 1785703d2f4SShreyas B. Prabhu int err; 1795703d2f4SShreyas B. Prabhu u8 val; 1805703d2f4SShreyas B. Prabhu 1815703d2f4SShreyas B. Prabhu if (kstrtou8(buf, 0, &val) || val != 1) 1825703d2f4SShreyas B. Prabhu return -EINVAL; 1835703d2f4SShreyas B. Prabhu 1845703d2f4SShreyas B. Prabhu if (fastsleep_workaround_applyonce == 1) 1855703d2f4SShreyas B. Prabhu return count; 1865703d2f4SShreyas B. Prabhu 1875703d2f4SShreyas B. Prabhu /* 1885703d2f4SShreyas B. Prabhu * fastsleep_workaround_applyonce = 1 implies 1895703d2f4SShreyas B. Prabhu * fastsleep workaround needs to be left in 'applied' state on all 1905703d2f4SShreyas B. Prabhu * the cores. Do this by- 19110d91611SNicholas Piggin * 1. Disable the 'undo' workaround in fastsleep exit path 19210d91611SNicholas Piggin * 2. Sendi IPIs to all the cores which have at least one online thread 19310d91611SNicholas Piggin * 3. Disable the 'apply' workaround in fastsleep entry path 19410d91611SNicholas Piggin * 1955703d2f4SShreyas B. Prabhu * There is no need to send ipi to cores which have all threads 1965703d2f4SShreyas B. Prabhu * offlined, as last thread of the core entering fastsleep or deeper 1975703d2f4SShreyas B. Prabhu * state would have applied workaround. 1985703d2f4SShreyas B. Prabhu */ 19910d91611SNicholas Piggin power7_fastsleep_workaround_exit = false; 2005703d2f4SShreyas B. Prabhu 2015703d2f4SShreyas B. Prabhu get_online_cpus(); 2025703d2f4SShreyas B. Prabhu primary_thread_mask = cpu_online_cores_map(); 2035703d2f4SShreyas B. Prabhu on_each_cpu_mask(&primary_thread_mask, 2045703d2f4SShreyas B. Prabhu pnv_fastsleep_workaround_apply, 2055703d2f4SShreyas B. Prabhu &err, 1); 2065703d2f4SShreyas B. Prabhu put_online_cpus(); 2075703d2f4SShreyas B. Prabhu if (err) { 2085703d2f4SShreyas B. Prabhu pr_err("fastsleep_workaround_applyonce change failed while running pnv_fastsleep_workaround_apply"); 2095703d2f4SShreyas B. Prabhu goto fail; 2105703d2f4SShreyas B. Prabhu } 2115703d2f4SShreyas B. Prabhu 21210d91611SNicholas Piggin power7_fastsleep_workaround_entry = false; 2135703d2f4SShreyas B. Prabhu 2145703d2f4SShreyas B. Prabhu fastsleep_workaround_applyonce = 1; 2155703d2f4SShreyas B. Prabhu 2165703d2f4SShreyas B. Prabhu return count; 2175703d2f4SShreyas B. Prabhu fail: 2185703d2f4SShreyas B. Prabhu return -EIO; 2195703d2f4SShreyas B. Prabhu } 2205703d2f4SShreyas B. Prabhu 2215703d2f4SShreyas B. Prabhu static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600, 2225703d2f4SShreyas B. Prabhu show_fastsleep_workaround_applyonce, 2235703d2f4SShreyas B. Prabhu store_fastsleep_workaround_applyonce); 2245703d2f4SShreyas B. Prabhu 22510d91611SNicholas Piggin static inline void atomic_start_thread_idle(void) 2262201f994SNicholas Piggin { 22710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 22810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 22910d91611SNicholas Piggin int thread_nr = cpu_thread_in_core(cpu); 23010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 23110d91611SNicholas Piggin 23210d91611SNicholas Piggin clear_bit(thread_nr, state); 23310d91611SNicholas Piggin } 23410d91611SNicholas Piggin 23510d91611SNicholas Piggin static inline void atomic_stop_thread_idle(void) 23610d91611SNicholas Piggin { 23710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 23810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 23910d91611SNicholas Piggin int thread_nr = cpu_thread_in_core(cpu); 24010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 24110d91611SNicholas Piggin 24210d91611SNicholas Piggin set_bit(thread_nr, state); 24310d91611SNicholas Piggin } 24410d91611SNicholas Piggin 24510d91611SNicholas Piggin static inline void atomic_lock_thread_idle(void) 24610d91611SNicholas Piggin { 24710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 24810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 24910d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 25010d91611SNicholas Piggin 25110d91611SNicholas Piggin while (unlikely(test_and_set_bit_lock(NR_PNV_CORE_IDLE_LOCK_BIT, state))) 25210d91611SNicholas Piggin barrier(); 25310d91611SNicholas Piggin } 25410d91611SNicholas Piggin 25510d91611SNicholas Piggin static inline void atomic_unlock_and_stop_thread_idle(void) 25610d91611SNicholas Piggin { 25710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 25810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 25910d91611SNicholas Piggin unsigned long thread = 1UL << cpu_thread_in_core(cpu); 26010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 26110d91611SNicholas Piggin u64 s = READ_ONCE(*state); 26210d91611SNicholas Piggin u64 new, tmp; 26310d91611SNicholas Piggin 26410d91611SNicholas Piggin BUG_ON(!(s & PNV_CORE_IDLE_LOCK_BIT)); 26510d91611SNicholas Piggin BUG_ON(s & thread); 26610d91611SNicholas Piggin 26710d91611SNicholas Piggin again: 26810d91611SNicholas Piggin new = (s | thread) & ~PNV_CORE_IDLE_LOCK_BIT; 26910d91611SNicholas Piggin tmp = cmpxchg(state, s, new); 27010d91611SNicholas Piggin if (unlikely(tmp != s)) { 27110d91611SNicholas Piggin s = tmp; 27210d91611SNicholas Piggin goto again; 27310d91611SNicholas Piggin } 27410d91611SNicholas Piggin } 27510d91611SNicholas Piggin 27610d91611SNicholas Piggin static inline void atomic_unlock_thread_idle(void) 27710d91611SNicholas Piggin { 27810d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 27910d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 28010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 28110d91611SNicholas Piggin 28210d91611SNicholas Piggin BUG_ON(!test_bit(NR_PNV_CORE_IDLE_LOCK_BIT, state)); 28310d91611SNicholas Piggin clear_bit_unlock(NR_PNV_CORE_IDLE_LOCK_BIT, state); 28410d91611SNicholas Piggin } 28510d91611SNicholas Piggin 28610d91611SNicholas Piggin /* P7 and P8 */ 28710d91611SNicholas Piggin struct p7_sprs { 28810d91611SNicholas Piggin /* per core */ 28910d91611SNicholas Piggin u64 tscr; 29010d91611SNicholas Piggin u64 worc; 29110d91611SNicholas Piggin 29210d91611SNicholas Piggin /* per subcore */ 29310d91611SNicholas Piggin u64 sdr1; 29410d91611SNicholas Piggin u64 rpr; 29510d91611SNicholas Piggin 29610d91611SNicholas Piggin /* per thread */ 29710d91611SNicholas Piggin u64 lpcr; 29810d91611SNicholas Piggin u64 hfscr; 29910d91611SNicholas Piggin u64 fscr; 30010d91611SNicholas Piggin u64 purr; 30110d91611SNicholas Piggin u64 spurr; 30210d91611SNicholas Piggin u64 dscr; 30310d91611SNicholas Piggin u64 wort; 304e9cef018SMichael Ellerman 305e9cef018SMichael Ellerman /* per thread SPRs that get lost in shallow states */ 306e9cef018SMichael Ellerman u64 amr; 307e9cef018SMichael Ellerman u64 iamr; 308e9cef018SMichael Ellerman u64 amor; 309e9cef018SMichael Ellerman u64 uamor; 31010d91611SNicholas Piggin }; 31110d91611SNicholas Piggin 31210d91611SNicholas Piggin static unsigned long power7_idle_insn(unsigned long type) 31310d91611SNicholas Piggin { 31410d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 31510d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 31610d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 31710d91611SNicholas Piggin unsigned long thread = 1UL << cpu_thread_in_core(cpu); 31810d91611SNicholas Piggin unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 3192201f994SNicholas Piggin unsigned long srr1; 32010d91611SNicholas Piggin bool full_winkle; 32110d91611SNicholas Piggin struct p7_sprs sprs = {}; /* avoid false use-uninitialised */ 32210d91611SNicholas Piggin bool sprs_saved = false; 32310d91611SNicholas Piggin int rc; 3242201f994SNicholas Piggin 32510d91611SNicholas Piggin if (unlikely(type != PNV_THREAD_NAP)) { 32610d91611SNicholas Piggin atomic_lock_thread_idle(); 3272201f994SNicholas Piggin 32810d91611SNicholas Piggin BUG_ON(!(*state & thread)); 32910d91611SNicholas Piggin *state &= ~thread; 3302201f994SNicholas Piggin 33110d91611SNicholas Piggin if (power7_fastsleep_workaround_entry) { 33210d91611SNicholas Piggin if ((*state & core_thread_mask) == 0) { 33310d91611SNicholas Piggin rc = opal_config_cpu_idle_state( 33410d91611SNicholas Piggin OPAL_CONFIG_IDLE_FASTSLEEP, 33510d91611SNicholas Piggin OPAL_CONFIG_IDLE_APPLY); 33610d91611SNicholas Piggin BUG_ON(rc); 33710d91611SNicholas Piggin } 33810d91611SNicholas Piggin } 33910d91611SNicholas Piggin 34010d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 34110d91611SNicholas Piggin sprs.tscr = mfspr(SPRN_TSCR); 34210d91611SNicholas Piggin sprs.worc = mfspr(SPRN_WORC); 34310d91611SNicholas Piggin 34410d91611SNicholas Piggin sprs.sdr1 = mfspr(SPRN_SDR1); 34510d91611SNicholas Piggin sprs.rpr = mfspr(SPRN_RPR); 34610d91611SNicholas Piggin 34710d91611SNicholas Piggin sprs.lpcr = mfspr(SPRN_LPCR); 34810d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 34910d91611SNicholas Piggin sprs.hfscr = mfspr(SPRN_HFSCR); 35010d91611SNicholas Piggin sprs.fscr = mfspr(SPRN_FSCR); 35110d91611SNicholas Piggin } 35210d91611SNicholas Piggin sprs.purr = mfspr(SPRN_PURR); 35310d91611SNicholas Piggin sprs.spurr = mfspr(SPRN_SPURR); 35410d91611SNicholas Piggin sprs.dscr = mfspr(SPRN_DSCR); 35510d91611SNicholas Piggin sprs.wort = mfspr(SPRN_WORT); 35610d91611SNicholas Piggin 35710d91611SNicholas Piggin sprs_saved = true; 35810d91611SNicholas Piggin 35910d91611SNicholas Piggin /* 36010d91611SNicholas Piggin * Increment winkle counter and set all winkle bits if 36110d91611SNicholas Piggin * all threads are winkling. This allows wakeup side to 36210d91611SNicholas Piggin * distinguish between fast sleep and winkle state 36310d91611SNicholas Piggin * loss. Fast sleep still has to resync the timebase so 36410d91611SNicholas Piggin * this may not be a really big win. 36510d91611SNicholas Piggin */ 36610d91611SNicholas Piggin *state += 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 36710d91611SNicholas Piggin if ((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) 36810d91611SNicholas Piggin >> PNV_CORE_IDLE_WINKLE_COUNT_SHIFT 36910d91611SNicholas Piggin == threads_per_core) 37010d91611SNicholas Piggin *state |= PNV_CORE_IDLE_THREAD_WINKLE_BITS; 37110d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 37210d91611SNicholas Piggin } 37310d91611SNicholas Piggin 37410d91611SNicholas Piggin atomic_unlock_thread_idle(); 37510d91611SNicholas Piggin } 37610d91611SNicholas Piggin 377e9cef018SMichael Ellerman if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 378e9cef018SMichael Ellerman sprs.amr = mfspr(SPRN_AMR); 379e9cef018SMichael Ellerman sprs.iamr = mfspr(SPRN_IAMR); 380e9cef018SMichael Ellerman sprs.amor = mfspr(SPRN_AMOR); 381e9cef018SMichael Ellerman sprs.uamor = mfspr(SPRN_UAMOR); 382e9cef018SMichael Ellerman } 383e9cef018SMichael Ellerman 38410d91611SNicholas Piggin local_paca->thread_idle_state = type; 38510d91611SNicholas Piggin srr1 = isa206_idle_insn_mayloss(type); /* go idle */ 38610d91611SNicholas Piggin local_paca->thread_idle_state = PNV_THREAD_RUNNING; 38710d91611SNicholas Piggin 38810d91611SNicholas Piggin WARN_ON_ONCE(!srr1); 38910d91611SNicholas Piggin WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 39010d91611SNicholas Piggin 391e9cef018SMichael Ellerman if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 392e9cef018SMichael Ellerman if ((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS) { 393e9cef018SMichael Ellerman /* 394e9cef018SMichael Ellerman * We don't need an isync after the mtsprs here because 395e9cef018SMichael Ellerman * the upcoming mtmsrd is execution synchronizing. 396e9cef018SMichael Ellerman */ 397e9cef018SMichael Ellerman mtspr(SPRN_AMR, sprs.amr); 398e9cef018SMichael Ellerman mtspr(SPRN_IAMR, sprs.iamr); 399e9cef018SMichael Ellerman mtspr(SPRN_AMOR, sprs.amor); 400e9cef018SMichael Ellerman mtspr(SPRN_UAMOR, sprs.uamor); 401e9cef018SMichael Ellerman } 402e9cef018SMichael Ellerman } 403e9cef018SMichael Ellerman 40410d91611SNicholas Piggin if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 40510d91611SNicholas Piggin hmi_exception_realmode(NULL); 40610d91611SNicholas Piggin 40710d91611SNicholas Piggin if (likely((srr1 & SRR1_WAKESTATE) != SRR1_WS_HVLOSS)) { 40810d91611SNicholas Piggin if (unlikely(type != PNV_THREAD_NAP)) { 40910d91611SNicholas Piggin atomic_lock_thread_idle(); 41010d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 41110d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 41210d91611SNicholas Piggin *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 41310d91611SNicholas Piggin *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); 41410d91611SNicholas Piggin } 41510d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 41610d91611SNicholas Piggin } 41710d91611SNicholas Piggin return srr1; 41810d91611SNicholas Piggin } 41910d91611SNicholas Piggin 42010d91611SNicholas Piggin /* HV state loss */ 42110d91611SNicholas Piggin BUG_ON(type == PNV_THREAD_NAP); 42210d91611SNicholas Piggin 42310d91611SNicholas Piggin atomic_lock_thread_idle(); 42410d91611SNicholas Piggin 42510d91611SNicholas Piggin full_winkle = false; 42610d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 42710d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 42810d91611SNicholas Piggin *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 42910d91611SNicholas Piggin if (*state & (thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT)) { 43010d91611SNicholas Piggin *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); 43110d91611SNicholas Piggin full_winkle = true; 43210d91611SNicholas Piggin BUG_ON(!sprs_saved); 43310d91611SNicholas Piggin } 43410d91611SNicholas Piggin } 43510d91611SNicholas Piggin 43610d91611SNicholas Piggin WARN_ON(*state & thread); 43710d91611SNicholas Piggin 43810d91611SNicholas Piggin if ((*state & core_thread_mask) != 0) 43910d91611SNicholas Piggin goto core_woken; 44010d91611SNicholas Piggin 44110d91611SNicholas Piggin /* Per-core SPRs */ 44210d91611SNicholas Piggin if (full_winkle) { 44310d91611SNicholas Piggin mtspr(SPRN_TSCR, sprs.tscr); 44410d91611SNicholas Piggin mtspr(SPRN_WORC, sprs.worc); 44510d91611SNicholas Piggin } 44610d91611SNicholas Piggin 44710d91611SNicholas Piggin if (power7_fastsleep_workaround_exit) { 44810d91611SNicholas Piggin rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 44910d91611SNicholas Piggin OPAL_CONFIG_IDLE_UNDO); 45010d91611SNicholas Piggin BUG_ON(rc); 45110d91611SNicholas Piggin } 45210d91611SNicholas Piggin 45310d91611SNicholas Piggin /* TB */ 45410d91611SNicholas Piggin if (opal_resync_timebase() != OPAL_SUCCESS) 45510d91611SNicholas Piggin BUG(); 45610d91611SNicholas Piggin 45710d91611SNicholas Piggin core_woken: 45810d91611SNicholas Piggin if (!full_winkle) 45910d91611SNicholas Piggin goto subcore_woken; 46010d91611SNicholas Piggin 46110d91611SNicholas Piggin if ((*state & local_paca->subcore_sibling_mask) != 0) 46210d91611SNicholas Piggin goto subcore_woken; 46310d91611SNicholas Piggin 46410d91611SNicholas Piggin /* Per-subcore SPRs */ 46510d91611SNicholas Piggin mtspr(SPRN_SDR1, sprs.sdr1); 46610d91611SNicholas Piggin mtspr(SPRN_RPR, sprs.rpr); 46710d91611SNicholas Piggin 46810d91611SNicholas Piggin subcore_woken: 46910d91611SNicholas Piggin /* 47010d91611SNicholas Piggin * isync after restoring shared SPRs and before unlocking. Unlock 47110d91611SNicholas Piggin * only contains hwsync which does not necessarily do the right 47210d91611SNicholas Piggin * thing for SPRs. 47310d91611SNicholas Piggin */ 47410d91611SNicholas Piggin isync(); 47510d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 47610d91611SNicholas Piggin 47710d91611SNicholas Piggin /* Fast sleep does not lose SPRs */ 47810d91611SNicholas Piggin if (!full_winkle) 47910d91611SNicholas Piggin return srr1; 48010d91611SNicholas Piggin 48110d91611SNicholas Piggin /* Per-thread SPRs */ 48210d91611SNicholas Piggin mtspr(SPRN_LPCR, sprs.lpcr); 48310d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 48410d91611SNicholas Piggin mtspr(SPRN_HFSCR, sprs.hfscr); 48510d91611SNicholas Piggin mtspr(SPRN_FSCR, sprs.fscr); 48610d91611SNicholas Piggin } 48710d91611SNicholas Piggin mtspr(SPRN_PURR, sprs.purr); 48810d91611SNicholas Piggin mtspr(SPRN_SPURR, sprs.spurr); 48910d91611SNicholas Piggin mtspr(SPRN_DSCR, sprs.dscr); 49010d91611SNicholas Piggin mtspr(SPRN_WORT, sprs.wort); 49110d91611SNicholas Piggin 49210d91611SNicholas Piggin mtspr(SPRN_SPRG3, local_paca->sprg_vdso); 49310d91611SNicholas Piggin 49410d91611SNicholas Piggin /* 49510d91611SNicholas Piggin * The SLB has to be restored here, but it sometimes still 49610d91611SNicholas Piggin * contains entries, so the __ variant must be used to prevent 49710d91611SNicholas Piggin * multi hits. 49810d91611SNicholas Piggin */ 49910d91611SNicholas Piggin __slb_restore_bolted_realmode(); 5002201f994SNicholas Piggin 5012201f994SNicholas Piggin return srr1; 5022201f994SNicholas Piggin } 5032201f994SNicholas Piggin 50410d91611SNicholas Piggin extern unsigned long idle_kvm_start_guest(unsigned long srr1); 50510d91611SNicholas Piggin 50610d91611SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 50710d91611SNicholas Piggin static unsigned long power7_offline(void) 50810d91611SNicholas Piggin { 50910d91611SNicholas Piggin unsigned long srr1; 51010d91611SNicholas Piggin 51110d91611SNicholas Piggin mtmsr(MSR_IDLE); 51210d91611SNicholas Piggin 51310d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 51410d91611SNicholas Piggin /* Tell KVM we're entering idle. */ 51510d91611SNicholas Piggin /******************************************************/ 51610d91611SNicholas Piggin /* N O T E W E L L ! ! ! N O T E W E L L */ 51710d91611SNicholas Piggin /* The following store to HSTATE_HWTHREAD_STATE(r13) */ 51810d91611SNicholas Piggin /* MUST occur in real mode, i.e. with the MMU off, */ 51910d91611SNicholas Piggin /* and the MMU must stay off until we clear this flag */ 52010d91611SNicholas Piggin /* and test HSTATE_HWTHREAD_REQ(r13) in */ 52110d91611SNicholas Piggin /* pnv_powersave_wakeup in this file. */ 52210d91611SNicholas Piggin /* The reason is that another thread can switch the */ 52310d91611SNicholas Piggin /* MMU to a guest context whenever this flag is set */ 52410d91611SNicholas Piggin /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ 52510d91611SNicholas Piggin /* that would potentially cause this thread to start */ 52610d91611SNicholas Piggin /* executing instructions from guest memory in */ 52710d91611SNicholas Piggin /* hypervisor mode, leading to a host crash or data */ 52810d91611SNicholas Piggin /* corruption, or worse. */ 52910d91611SNicholas Piggin /******************************************************/ 53010d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_IDLE; 53110d91611SNicholas Piggin #endif 53210d91611SNicholas Piggin 53310d91611SNicholas Piggin __ppc64_runlatch_off(); 53410d91611SNicholas Piggin srr1 = power7_idle_insn(power7_offline_type); 53510d91611SNicholas Piggin __ppc64_runlatch_on(); 53610d91611SNicholas Piggin 53710d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 53810d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_KERNEL; 53910d91611SNicholas Piggin /* Order setting hwthread_state vs. testing hwthread_req */ 54010d91611SNicholas Piggin smp_mb(); 54110d91611SNicholas Piggin if (local_paca->kvm_hstate.hwthread_req) 54210d91611SNicholas Piggin srr1 = idle_kvm_start_guest(srr1); 54310d91611SNicholas Piggin #endif 54410d91611SNicholas Piggin 54510d91611SNicholas Piggin mtmsr(MSR_KERNEL); 54610d91611SNicholas Piggin 54710d91611SNicholas Piggin return srr1; 54810d91611SNicholas Piggin } 54910d91611SNicholas Piggin #endif 55010d91611SNicholas Piggin 5512201f994SNicholas Piggin void power7_idle_type(unsigned long type) 5522201f994SNicholas Piggin { 553771d4304SNicholas Piggin unsigned long srr1; 554771d4304SNicholas Piggin 55510d91611SNicholas Piggin if (!prep_irq_for_idle_irqsoff()) 55610d91611SNicholas Piggin return; 55710d91611SNicholas Piggin 55810d91611SNicholas Piggin mtmsr(MSR_IDLE); 55910d91611SNicholas Piggin __ppc64_runlatch_off(); 56010d91611SNicholas Piggin srr1 = power7_idle_insn(type); 56110d91611SNicholas Piggin __ppc64_runlatch_on(); 56210d91611SNicholas Piggin mtmsr(MSR_KERNEL); 56310d91611SNicholas Piggin 56410d91611SNicholas Piggin fini_irq_for_idle_irqsoff(); 565771d4304SNicholas Piggin irq_set_pending_from_srr1(srr1); 5662201f994SNicholas Piggin } 5672201f994SNicholas Piggin 568ffd2961bSNicholas Piggin static void power7_idle(void) 5692201f994SNicholas Piggin { 5702201f994SNicholas Piggin if (!powersave_nap) 5712201f994SNicholas Piggin return; 5722201f994SNicholas Piggin 5732201f994SNicholas Piggin power7_idle_type(PNV_THREAD_NAP); 5742201f994SNicholas Piggin } 5752201f994SNicholas Piggin 57610d91611SNicholas Piggin struct p9_sprs { 57710d91611SNicholas Piggin /* per core */ 57810d91611SNicholas Piggin u64 ptcr; 57910d91611SNicholas Piggin u64 rpr; 58010d91611SNicholas Piggin u64 tscr; 58110d91611SNicholas Piggin u64 ldbar; 58210d91611SNicholas Piggin 58310d91611SNicholas Piggin /* per thread */ 58410d91611SNicholas Piggin u64 lpcr; 58510d91611SNicholas Piggin u64 hfscr; 58610d91611SNicholas Piggin u64 fscr; 58710d91611SNicholas Piggin u64 pid; 58810d91611SNicholas Piggin u64 purr; 58910d91611SNicholas Piggin u64 spurr; 59010d91611SNicholas Piggin u64 dscr; 59110d91611SNicholas Piggin u64 wort; 59210d91611SNicholas Piggin 59310d91611SNicholas Piggin u64 mmcra; 59410d91611SNicholas Piggin u32 mmcr0; 59510d91611SNicholas Piggin u32 mmcr1; 59610d91611SNicholas Piggin u64 mmcr2; 597e9cef018SMichael Ellerman 598e9cef018SMichael Ellerman /* per thread SPRs that get lost in shallow states */ 599e9cef018SMichael Ellerman u64 amr; 600e9cef018SMichael Ellerman u64 iamr; 601e9cef018SMichael Ellerman u64 amor; 602e9cef018SMichael Ellerman u64 uamor; 60310d91611SNicholas Piggin }; 60410d91611SNicholas Piggin 60510d91611SNicholas Piggin static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on) 60610d91611SNicholas Piggin { 60710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 60810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 60910d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 61010d91611SNicholas Piggin unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 61110d91611SNicholas Piggin unsigned long srr1; 61210d91611SNicholas Piggin unsigned long pls; 61310d91611SNicholas Piggin unsigned long mmcr0 = 0; 6141cade527SAthira Rajeev unsigned long mmcra = 0; 61510d91611SNicholas Piggin struct p9_sprs sprs = {}; /* avoid false used-uninitialised */ 61610d91611SNicholas Piggin bool sprs_saved = false; 61710d91611SNicholas Piggin 61810d91611SNicholas Piggin if (!(psscr & (PSSCR_EC|PSSCR_ESL))) { 61910d91611SNicholas Piggin /* EC=ESL=0 case */ 62010d91611SNicholas Piggin 62110d91611SNicholas Piggin BUG_ON(!mmu_on); 62210d91611SNicholas Piggin 62310d91611SNicholas Piggin /* 62410d91611SNicholas Piggin * Wake synchronously. SRESET via xscom may still cause 62510d91611SNicholas Piggin * a 0x100 powersave wakeup with SRR1 reason! 62610d91611SNicholas Piggin */ 62710d91611SNicholas Piggin srr1 = isa300_idle_stop_noloss(psscr); /* go idle */ 62810d91611SNicholas Piggin if (likely(!srr1)) 62910d91611SNicholas Piggin return 0; 63010d91611SNicholas Piggin 63110d91611SNicholas Piggin /* 63210d91611SNicholas Piggin * Registers not saved, can't recover! 63310d91611SNicholas Piggin * This would be a hardware bug 63410d91611SNicholas Piggin */ 63510d91611SNicholas Piggin BUG_ON((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS); 63610d91611SNicholas Piggin 63710d91611SNicholas Piggin goto out; 63810d91611SNicholas Piggin } 63910d91611SNicholas Piggin 64010d91611SNicholas Piggin /* EC=ESL=1 case */ 64110d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 64210d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_P9_TM_XER_SO_BUG)) { 64310d91611SNicholas Piggin local_paca->requested_psscr = psscr; 64410d91611SNicholas Piggin /* order setting requested_psscr vs testing dont_stop */ 64510d91611SNicholas Piggin smp_mb(); 64610d91611SNicholas Piggin if (atomic_read(&local_paca->dont_stop)) { 64710d91611SNicholas Piggin local_paca->requested_psscr = 0; 64810d91611SNicholas Piggin return 0; 64910d91611SNicholas Piggin } 65010d91611SNicholas Piggin } 65110d91611SNicholas Piggin #endif 65210d91611SNicholas Piggin 65310d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { 65410d91611SNicholas Piggin /* 65510d91611SNicholas Piggin * POWER9 DD2 can incorrectly set PMAO when waking up 65610d91611SNicholas Piggin * after a state-loss idle. Saving and restoring MMCR0 65710d91611SNicholas Piggin * over idle is a workaround. 65810d91611SNicholas Piggin */ 65910d91611SNicholas Piggin mmcr0 = mfspr(SPRN_MMCR0); 66010d91611SNicholas Piggin } 6611cade527SAthira Rajeev 662dcbbfa6bSPratik Rajesh Sampat if ((psscr & PSSCR_RL_MASK) >= deep_spr_loss_state) { 66310d91611SNicholas Piggin sprs.lpcr = mfspr(SPRN_LPCR); 66410d91611SNicholas Piggin sprs.hfscr = mfspr(SPRN_HFSCR); 66510d91611SNicholas Piggin sprs.fscr = mfspr(SPRN_FSCR); 66610d91611SNicholas Piggin sprs.pid = mfspr(SPRN_PID); 66710d91611SNicholas Piggin sprs.purr = mfspr(SPRN_PURR); 66810d91611SNicholas Piggin sprs.spurr = mfspr(SPRN_SPURR); 66910d91611SNicholas Piggin sprs.dscr = mfspr(SPRN_DSCR); 67010d91611SNicholas Piggin sprs.wort = mfspr(SPRN_WORT); 67110d91611SNicholas Piggin 67210d91611SNicholas Piggin sprs.mmcra = mfspr(SPRN_MMCRA); 67310d91611SNicholas Piggin sprs.mmcr0 = mfspr(SPRN_MMCR0); 67410d91611SNicholas Piggin sprs.mmcr1 = mfspr(SPRN_MMCR1); 67510d91611SNicholas Piggin sprs.mmcr2 = mfspr(SPRN_MMCR2); 67610d91611SNicholas Piggin 67710d91611SNicholas Piggin sprs.ptcr = mfspr(SPRN_PTCR); 67810d91611SNicholas Piggin sprs.rpr = mfspr(SPRN_RPR); 67910d91611SNicholas Piggin sprs.tscr = mfspr(SPRN_TSCR); 680512a5a64SClaudio Carvalho if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) 68110d91611SNicholas Piggin sprs.ldbar = mfspr(SPRN_LDBAR); 68210d91611SNicholas Piggin 68310d91611SNicholas Piggin sprs_saved = true; 68410d91611SNicholas Piggin 68510d91611SNicholas Piggin atomic_start_thread_idle(); 68610d91611SNicholas Piggin } 68710d91611SNicholas Piggin 688e9cef018SMichael Ellerman sprs.amr = mfspr(SPRN_AMR); 689e9cef018SMichael Ellerman sprs.iamr = mfspr(SPRN_IAMR); 690e9cef018SMichael Ellerman sprs.amor = mfspr(SPRN_AMOR); 691e9cef018SMichael Ellerman sprs.uamor = mfspr(SPRN_UAMOR); 692e9cef018SMichael Ellerman 69310d91611SNicholas Piggin srr1 = isa300_idle_stop_mayloss(psscr); /* go idle */ 69410d91611SNicholas Piggin 69510d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 69610d91611SNicholas Piggin local_paca->requested_psscr = 0; 69710d91611SNicholas Piggin #endif 69810d91611SNicholas Piggin 69910d91611SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 70010d91611SNicholas Piggin 70110d91611SNicholas Piggin WARN_ON_ONCE(!srr1); 70210d91611SNicholas Piggin WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 70310d91611SNicholas Piggin 70410d91611SNicholas Piggin if ((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS) { 70510d91611SNicholas Piggin /* 706e9cef018SMichael Ellerman * We don't need an isync after the mtsprs here because the 707e9cef018SMichael Ellerman * upcoming mtmsrd is execution synchronizing. 708e9cef018SMichael Ellerman */ 709e9cef018SMichael Ellerman mtspr(SPRN_AMR, sprs.amr); 710e9cef018SMichael Ellerman mtspr(SPRN_IAMR, sprs.iamr); 711e9cef018SMichael Ellerman mtspr(SPRN_AMOR, sprs.amor); 712e9cef018SMichael Ellerman mtspr(SPRN_UAMOR, sprs.uamor); 713e9cef018SMichael Ellerman 714e9cef018SMichael Ellerman /* 71510d91611SNicholas Piggin * Workaround for POWER9 DD2.0, if we lost resources, the ERAT 71610d91611SNicholas Piggin * might have been corrupted and needs flushing. We also need 71710d91611SNicholas Piggin * to reload MMCR0 (see mmcr0 comment above). 71810d91611SNicholas Piggin */ 71910d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { 720fe7946ceSNicholas Piggin asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT); 72110d91611SNicholas Piggin mtspr(SPRN_MMCR0, mmcr0); 72210d91611SNicholas Piggin } 72310d91611SNicholas Piggin 72410d91611SNicholas Piggin /* 72510d91611SNicholas Piggin * DD2.2 and earlier need to set then clear bit 60 in MMCRA 72610d91611SNicholas Piggin * to ensure the PMU starts running. 72710d91611SNicholas Piggin */ 72810d91611SNicholas Piggin mmcra = mfspr(SPRN_MMCRA); 72910d91611SNicholas Piggin mmcra |= PPC_BIT(60); 73010d91611SNicholas Piggin mtspr(SPRN_MMCRA, mmcra); 73110d91611SNicholas Piggin mmcra &= ~PPC_BIT(60); 73210d91611SNicholas Piggin mtspr(SPRN_MMCRA, mmcra); 73310d91611SNicholas Piggin } 73410d91611SNicholas Piggin 73510d91611SNicholas Piggin if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 73610d91611SNicholas Piggin hmi_exception_realmode(NULL); 73710d91611SNicholas Piggin 73810d91611SNicholas Piggin /* 73910d91611SNicholas Piggin * On POWER9, SRR1 bits do not match exactly as expected. 74010d91611SNicholas Piggin * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so 74110d91611SNicholas Piggin * just always test PSSCR for SPR/TB state loss. 74210d91611SNicholas Piggin */ 74310d91611SNicholas Piggin pls = (psscr & PSSCR_PLS) >> PSSCR_PLS_SHIFT; 744dcbbfa6bSPratik Rajesh Sampat if (likely(pls < deep_spr_loss_state)) { 74510d91611SNicholas Piggin if (sprs_saved) 74610d91611SNicholas Piggin atomic_stop_thread_idle(); 74710d91611SNicholas Piggin goto out; 74810d91611SNicholas Piggin } 74910d91611SNicholas Piggin 75010d91611SNicholas Piggin /* HV state loss */ 75110d91611SNicholas Piggin BUG_ON(!sprs_saved); 75210d91611SNicholas Piggin 75310d91611SNicholas Piggin atomic_lock_thread_idle(); 75410d91611SNicholas Piggin 75510d91611SNicholas Piggin if ((*state & core_thread_mask) != 0) 75610d91611SNicholas Piggin goto core_woken; 75710d91611SNicholas Piggin 75810d91611SNicholas Piggin /* Per-core SPRs */ 75910d91611SNicholas Piggin mtspr(SPRN_PTCR, sprs.ptcr); 76010d91611SNicholas Piggin mtspr(SPRN_RPR, sprs.rpr); 76110d91611SNicholas Piggin mtspr(SPRN_TSCR, sprs.tscr); 76210d91611SNicholas Piggin 76310d91611SNicholas Piggin if (pls >= pnv_first_tb_loss_level) { 76410d91611SNicholas Piggin /* TB loss */ 76510d91611SNicholas Piggin if (opal_resync_timebase() != OPAL_SUCCESS) 76610d91611SNicholas Piggin BUG(); 76710d91611SNicholas Piggin } 76810d91611SNicholas Piggin 76910d91611SNicholas Piggin /* 77010d91611SNicholas Piggin * isync after restoring shared SPRs and before unlocking. Unlock 77110d91611SNicholas Piggin * only contains hwsync which does not necessarily do the right 77210d91611SNicholas Piggin * thing for SPRs. 77310d91611SNicholas Piggin */ 77410d91611SNicholas Piggin isync(); 77510d91611SNicholas Piggin 77610d91611SNicholas Piggin core_woken: 77710d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 77810d91611SNicholas Piggin 77910d91611SNicholas Piggin /* Per-thread SPRs */ 78010d91611SNicholas Piggin mtspr(SPRN_LPCR, sprs.lpcr); 78110d91611SNicholas Piggin mtspr(SPRN_HFSCR, sprs.hfscr); 78210d91611SNicholas Piggin mtspr(SPRN_FSCR, sprs.fscr); 78310d91611SNicholas Piggin mtspr(SPRN_PID, sprs.pid); 78410d91611SNicholas Piggin mtspr(SPRN_PURR, sprs.purr); 78510d91611SNicholas Piggin mtspr(SPRN_SPURR, sprs.spurr); 78610d91611SNicholas Piggin mtspr(SPRN_DSCR, sprs.dscr); 78710d91611SNicholas Piggin mtspr(SPRN_WORT, sprs.wort); 78810d91611SNicholas Piggin 78910d91611SNicholas Piggin mtspr(SPRN_MMCRA, sprs.mmcra); 79010d91611SNicholas Piggin mtspr(SPRN_MMCR0, sprs.mmcr0); 79110d91611SNicholas Piggin mtspr(SPRN_MMCR1, sprs.mmcr1); 79210d91611SNicholas Piggin mtspr(SPRN_MMCR2, sprs.mmcr2); 793512a5a64SClaudio Carvalho if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) 794f5a9e488SAthira Rajeev mtspr(SPRN_LDBAR, sprs.ldbar); 79510d91611SNicholas Piggin 79610d91611SNicholas Piggin mtspr(SPRN_SPRG3, local_paca->sprg_vdso); 79710d91611SNicholas Piggin 79810d91611SNicholas Piggin if (!radix_enabled()) 79910d91611SNicholas Piggin __slb_restore_bolted_realmode(); 80010d91611SNicholas Piggin 80110d91611SNicholas Piggin out: 80210d91611SNicholas Piggin if (mmu_on) 80310d91611SNicholas Piggin mtmsr(MSR_KERNEL); 80410d91611SNicholas Piggin 80510d91611SNicholas Piggin return srr1; 80610d91611SNicholas Piggin } 80710d91611SNicholas Piggin 8087672691aSPaul Mackerras #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 8097672691aSPaul Mackerras /* 8107672691aSPaul Mackerras * This is used in working around bugs in thread reconfiguration 8117672691aSPaul Mackerras * on POWER9 (at least up to Nimbus DD2.2) relating to transactional 8127672691aSPaul Mackerras * memory and the way that XER[SO] is checkpointed. 8137672691aSPaul Mackerras * This function forces the core into SMT4 in order by asking 8147672691aSPaul Mackerras * all other threads not to stop, and sending a message to any 8157672691aSPaul Mackerras * that are in a stop state. 8167672691aSPaul Mackerras * Must be called with preemption disabled. 8177672691aSPaul Mackerras */ 8187672691aSPaul Mackerras void pnv_power9_force_smt4_catch(void) 8197672691aSPaul Mackerras { 8207672691aSPaul Mackerras int cpu, cpu0, thr; 8217672691aSPaul Mackerras int awake_threads = 1; /* this thread is awake */ 8227672691aSPaul Mackerras int poke_threads = 0; 8237672691aSPaul Mackerras int need_awake = threads_per_core; 8247672691aSPaul Mackerras 8257672691aSPaul Mackerras cpu = smp_processor_id(); 8267672691aSPaul Mackerras cpu0 = cpu & ~(threads_per_core - 1); 8277672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 8287672691aSPaul Mackerras if (cpu != cpu0 + thr) 829f437c517SMichael Ellerman atomic_inc(&paca_ptrs[cpu0+thr]->dont_stop); 8307672691aSPaul Mackerras } 8317672691aSPaul Mackerras /* order setting dont_stop vs testing requested_psscr */ 83210d91611SNicholas Piggin smp_mb(); 8337672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 834f437c517SMichael Ellerman if (!paca_ptrs[cpu0+thr]->requested_psscr) 8357672691aSPaul Mackerras ++awake_threads; 8367672691aSPaul Mackerras else 8377672691aSPaul Mackerras poke_threads |= (1 << thr); 8387672691aSPaul Mackerras } 8397672691aSPaul Mackerras 8407672691aSPaul Mackerras /* If at least 3 threads are awake, the core is in SMT4 already */ 8417672691aSPaul Mackerras if (awake_threads < need_awake) { 8427672691aSPaul Mackerras /* We have to wake some threads; we'll use msgsnd */ 8437672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 8447672691aSPaul Mackerras if (poke_threads & (1 << thr)) { 8457672691aSPaul Mackerras ppc_msgsnd_sync(); 8467672691aSPaul Mackerras ppc_msgsnd(PPC_DBELL_MSGTYPE, 0, 847f437c517SMichael Ellerman paca_ptrs[cpu0+thr]->hw_cpu_id); 8487672691aSPaul Mackerras } 8497672691aSPaul Mackerras } 8507672691aSPaul Mackerras /* now spin until at least 3 threads are awake */ 8517672691aSPaul Mackerras do { 8527672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 8537672691aSPaul Mackerras if ((poke_threads & (1 << thr)) && 854f437c517SMichael Ellerman !paca_ptrs[cpu0+thr]->requested_psscr) { 8557672691aSPaul Mackerras ++awake_threads; 8567672691aSPaul Mackerras poke_threads &= ~(1 << thr); 8577672691aSPaul Mackerras } 8587672691aSPaul Mackerras } 8597672691aSPaul Mackerras } while (awake_threads < need_awake); 8607672691aSPaul Mackerras } 8617672691aSPaul Mackerras } 8627672691aSPaul Mackerras EXPORT_SYMBOL_GPL(pnv_power9_force_smt4_catch); 8637672691aSPaul Mackerras 8647672691aSPaul Mackerras void pnv_power9_force_smt4_release(void) 8657672691aSPaul Mackerras { 8667672691aSPaul Mackerras int cpu, cpu0, thr; 8677672691aSPaul Mackerras 8687672691aSPaul Mackerras cpu = smp_processor_id(); 8697672691aSPaul Mackerras cpu0 = cpu & ~(threads_per_core - 1); 8707672691aSPaul Mackerras 8717672691aSPaul Mackerras /* clear all the dont_stop flags */ 8727672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 8737672691aSPaul Mackerras if (cpu != cpu0 + thr) 874f437c517SMichael Ellerman atomic_dec(&paca_ptrs[cpu0+thr]->dont_stop); 8757672691aSPaul Mackerras } 8767672691aSPaul Mackerras } 8777672691aSPaul Mackerras EXPORT_SYMBOL_GPL(pnv_power9_force_smt4_release); 8787672691aSPaul Mackerras #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 8797672691aSPaul Mackerras 880ffd2961bSNicholas Piggin struct p10_sprs { 881ffd2961bSNicholas Piggin /* 882ffd2961bSNicholas Piggin * SPRs that get lost in shallow states: 883ffd2961bSNicholas Piggin * 884ffd2961bSNicholas Piggin * P10 loses CR, LR, CTR, FPSCR, VSCR, XER, TAR, SPRG2, and HSPRG1 885ffd2961bSNicholas Piggin * isa300 idle routines restore CR, LR. 886ffd2961bSNicholas Piggin * CTR is volatile 887ffd2961bSNicholas Piggin * idle thread doesn't use FP or VEC 888ffd2961bSNicholas Piggin * kernel doesn't use TAR 889ffd2961bSNicholas Piggin * HSPRG1 is only live in HV interrupt entry 890ffd2961bSNicholas Piggin * SPRG2 is only live in KVM guests, KVM handles it. 891ffd2961bSNicholas Piggin */ 892ffd2961bSNicholas Piggin }; 893ffd2961bSNicholas Piggin 894ffd2961bSNicholas Piggin static unsigned long power10_idle_stop(unsigned long psscr, bool mmu_on) 895ffd2961bSNicholas Piggin { 896ffd2961bSNicholas Piggin int cpu = raw_smp_processor_id(); 897ffd2961bSNicholas Piggin int first = cpu_first_thread_sibling(cpu); 898ffd2961bSNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 899ffd2961bSNicholas Piggin unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 900ffd2961bSNicholas Piggin unsigned long srr1; 901ffd2961bSNicholas Piggin unsigned long pls; 902ffd2961bSNicholas Piggin // struct p10_sprs sprs = {}; /* avoid false used-uninitialised */ 903ffd2961bSNicholas Piggin bool sprs_saved = false; 904ffd2961bSNicholas Piggin 905ffd2961bSNicholas Piggin if (!(psscr & (PSSCR_EC|PSSCR_ESL))) { 906ffd2961bSNicholas Piggin /* EC=ESL=0 case */ 907ffd2961bSNicholas Piggin 908ffd2961bSNicholas Piggin BUG_ON(!mmu_on); 909ffd2961bSNicholas Piggin 910ffd2961bSNicholas Piggin /* 911ffd2961bSNicholas Piggin * Wake synchronously. SRESET via xscom may still cause 912ffd2961bSNicholas Piggin * a 0x100 powersave wakeup with SRR1 reason! 913ffd2961bSNicholas Piggin */ 914ffd2961bSNicholas Piggin srr1 = isa300_idle_stop_noloss(psscr); /* go idle */ 915ffd2961bSNicholas Piggin if (likely(!srr1)) 916ffd2961bSNicholas Piggin return 0; 917ffd2961bSNicholas Piggin 918ffd2961bSNicholas Piggin /* 919ffd2961bSNicholas Piggin * Registers not saved, can't recover! 920ffd2961bSNicholas Piggin * This would be a hardware bug 921ffd2961bSNicholas Piggin */ 922ffd2961bSNicholas Piggin BUG_ON((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS); 923ffd2961bSNicholas Piggin 924ffd2961bSNicholas Piggin goto out; 925ffd2961bSNicholas Piggin } 926ffd2961bSNicholas Piggin 927ffd2961bSNicholas Piggin /* EC=ESL=1 case */ 928ffd2961bSNicholas Piggin if ((psscr & PSSCR_RL_MASK) >= deep_spr_loss_state) { 929ffd2961bSNicholas Piggin /* XXX: save SPRs for deep state loss here. */ 930ffd2961bSNicholas Piggin 931ffd2961bSNicholas Piggin sprs_saved = true; 932ffd2961bSNicholas Piggin 933ffd2961bSNicholas Piggin atomic_start_thread_idle(); 934ffd2961bSNicholas Piggin } 935ffd2961bSNicholas Piggin 936ffd2961bSNicholas Piggin srr1 = isa300_idle_stop_mayloss(psscr); /* go idle */ 937ffd2961bSNicholas Piggin 938ffd2961bSNicholas Piggin psscr = mfspr(SPRN_PSSCR); 939ffd2961bSNicholas Piggin 940ffd2961bSNicholas Piggin WARN_ON_ONCE(!srr1); 941ffd2961bSNicholas Piggin WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 942ffd2961bSNicholas Piggin 943ffd2961bSNicholas Piggin if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 944ffd2961bSNicholas Piggin hmi_exception_realmode(NULL); 945ffd2961bSNicholas Piggin 946ffd2961bSNicholas Piggin /* 947ffd2961bSNicholas Piggin * On POWER10, SRR1 bits do not match exactly as expected. 948ffd2961bSNicholas Piggin * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so 949ffd2961bSNicholas Piggin * just always test PSSCR for SPR/TB state loss. 950ffd2961bSNicholas Piggin */ 951ffd2961bSNicholas Piggin pls = (psscr & PSSCR_PLS) >> PSSCR_PLS_SHIFT; 952ffd2961bSNicholas Piggin if (likely(pls < deep_spr_loss_state)) { 953ffd2961bSNicholas Piggin if (sprs_saved) 954ffd2961bSNicholas Piggin atomic_stop_thread_idle(); 955ffd2961bSNicholas Piggin goto out; 956ffd2961bSNicholas Piggin } 957ffd2961bSNicholas Piggin 958ffd2961bSNicholas Piggin /* HV state loss */ 959ffd2961bSNicholas Piggin BUG_ON(!sprs_saved); 960ffd2961bSNicholas Piggin 961ffd2961bSNicholas Piggin atomic_lock_thread_idle(); 962ffd2961bSNicholas Piggin 963ffd2961bSNicholas Piggin if ((*state & core_thread_mask) != 0) 964ffd2961bSNicholas Piggin goto core_woken; 965ffd2961bSNicholas Piggin 966ffd2961bSNicholas Piggin /* XXX: restore per-core SPRs here */ 967ffd2961bSNicholas Piggin 968ffd2961bSNicholas Piggin if (pls >= pnv_first_tb_loss_level) { 969ffd2961bSNicholas Piggin /* TB loss */ 970ffd2961bSNicholas Piggin if (opal_resync_timebase() != OPAL_SUCCESS) 971ffd2961bSNicholas Piggin BUG(); 972ffd2961bSNicholas Piggin } 973ffd2961bSNicholas Piggin 974ffd2961bSNicholas Piggin /* 975ffd2961bSNicholas Piggin * isync after restoring shared SPRs and before unlocking. Unlock 976ffd2961bSNicholas Piggin * only contains hwsync which does not necessarily do the right 977ffd2961bSNicholas Piggin * thing for SPRs. 978ffd2961bSNicholas Piggin */ 979ffd2961bSNicholas Piggin isync(); 980ffd2961bSNicholas Piggin 981ffd2961bSNicholas Piggin core_woken: 982ffd2961bSNicholas Piggin atomic_unlock_and_stop_thread_idle(); 983ffd2961bSNicholas Piggin 984ffd2961bSNicholas Piggin /* XXX: restore per-thread SPRs here */ 985ffd2961bSNicholas Piggin 986ffd2961bSNicholas Piggin if (!radix_enabled()) 987ffd2961bSNicholas Piggin __slb_restore_bolted_realmode(); 988ffd2961bSNicholas Piggin 989ffd2961bSNicholas Piggin out: 990ffd2961bSNicholas Piggin if (mmu_on) 991ffd2961bSNicholas Piggin mtmsr(MSR_KERNEL); 992ffd2961bSNicholas Piggin 993ffd2961bSNicholas Piggin return srr1; 994ffd2961bSNicholas Piggin } 995ffd2961bSNicholas Piggin 996ffd2961bSNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 997ffd2961bSNicholas Piggin static unsigned long arch300_offline_stop(unsigned long psscr) 998ffd2961bSNicholas Piggin { 999ffd2961bSNicholas Piggin unsigned long srr1; 1000ffd2961bSNicholas Piggin 1001ffd2961bSNicholas Piggin #ifndef CONFIG_KVM_BOOK3S_HV_POSSIBLE 1002ffd2961bSNicholas Piggin __ppc64_runlatch_off(); 1003ffd2961bSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_31)) 1004ffd2961bSNicholas Piggin srr1 = power10_idle_stop(psscr, true); 1005ffd2961bSNicholas Piggin else 1006ffd2961bSNicholas Piggin srr1 = power9_idle_stop(psscr, true); 1007ffd2961bSNicholas Piggin __ppc64_runlatch_on(); 1008ffd2961bSNicholas Piggin #else 1009ffd2961bSNicholas Piggin /* 1010ffd2961bSNicholas Piggin * Tell KVM we're entering idle. 1011ffd2961bSNicholas Piggin * This does not have to be done in real mode because the P9 MMU 1012ffd2961bSNicholas Piggin * is independent per-thread. Some steppings share radix/hash mode 1013ffd2961bSNicholas Piggin * between threads, but in that case KVM has a barrier sync in real 1014ffd2961bSNicholas Piggin * mode before and after switching between radix and hash. 1015ffd2961bSNicholas Piggin * 1016ffd2961bSNicholas Piggin * kvm_start_guest must still be called in real mode though, hence 1017ffd2961bSNicholas Piggin * the false argument. 1018ffd2961bSNicholas Piggin */ 1019ffd2961bSNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_IDLE; 1020ffd2961bSNicholas Piggin 1021ffd2961bSNicholas Piggin __ppc64_runlatch_off(); 1022ffd2961bSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_31)) 1023ffd2961bSNicholas Piggin srr1 = power10_idle_stop(psscr, false); 1024ffd2961bSNicholas Piggin else 1025ffd2961bSNicholas Piggin srr1 = power9_idle_stop(psscr, false); 1026ffd2961bSNicholas Piggin __ppc64_runlatch_on(); 1027ffd2961bSNicholas Piggin 1028ffd2961bSNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_KERNEL; 1029ffd2961bSNicholas Piggin /* Order setting hwthread_state vs. testing hwthread_req */ 1030ffd2961bSNicholas Piggin smp_mb(); 1031ffd2961bSNicholas Piggin if (local_paca->kvm_hstate.hwthread_req) 1032ffd2961bSNicholas Piggin srr1 = idle_kvm_start_guest(srr1); 1033ffd2961bSNicholas Piggin mtmsr(MSR_KERNEL); 1034ffd2961bSNicholas Piggin #endif 1035ffd2961bSNicholas Piggin 1036ffd2961bSNicholas Piggin return srr1; 1037ffd2961bSNicholas Piggin } 1038ffd2961bSNicholas Piggin #endif 1039ffd2961bSNicholas Piggin 1040ffd2961bSNicholas Piggin void arch300_idle_type(unsigned long stop_psscr_val, 1041ffd2961bSNicholas Piggin unsigned long stop_psscr_mask) 1042ffd2961bSNicholas Piggin { 1043ffd2961bSNicholas Piggin unsigned long psscr; 1044ffd2961bSNicholas Piggin unsigned long srr1; 1045ffd2961bSNicholas Piggin 1046ffd2961bSNicholas Piggin if (!prep_irq_for_idle_irqsoff()) 1047ffd2961bSNicholas Piggin return; 1048ffd2961bSNicholas Piggin 1049ffd2961bSNicholas Piggin psscr = mfspr(SPRN_PSSCR); 1050ffd2961bSNicholas Piggin psscr = (psscr & ~stop_psscr_mask) | stop_psscr_val; 1051ffd2961bSNicholas Piggin 1052ffd2961bSNicholas Piggin __ppc64_runlatch_off(); 1053ffd2961bSNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_31)) 1054ffd2961bSNicholas Piggin srr1 = power10_idle_stop(psscr, true); 1055ffd2961bSNicholas Piggin else 1056ffd2961bSNicholas Piggin srr1 = power9_idle_stop(psscr, true); 1057ffd2961bSNicholas Piggin __ppc64_runlatch_on(); 1058ffd2961bSNicholas Piggin 1059ffd2961bSNicholas Piggin fini_irq_for_idle_irqsoff(); 1060ffd2961bSNicholas Piggin 1061ffd2961bSNicholas Piggin irq_set_pending_from_srr1(srr1); 1062ffd2961bSNicholas Piggin } 1063ffd2961bSNicholas Piggin 1064ffd2961bSNicholas Piggin /* 1065ffd2961bSNicholas Piggin * Used for ppc_md.power_save which needs a function with no parameters 1066ffd2961bSNicholas Piggin */ 1067ffd2961bSNicholas Piggin static void arch300_idle(void) 1068ffd2961bSNicholas Piggin { 1069ffd2961bSNicholas Piggin arch300_idle_type(pnv_default_stop_val, pnv_default_stop_mask); 1070ffd2961bSNicholas Piggin } 1071ffd2961bSNicholas Piggin 107267d20418SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 107319f8a5b5SPaul Mackerras 107419f8a5b5SPaul Mackerras void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val) 107524be85a2SGautham R. Shenoy { 107624be85a2SGautham R. Shenoy u64 pir = get_hard_smp_processor_id(cpu); 107724be85a2SGautham R. Shenoy 107824be85a2SGautham R. Shenoy mtspr(SPRN_LPCR, lpcr_val); 10795d298baaSGautham R. Shenoy 10805d298baaSGautham R. Shenoy /* 10815d298baaSGautham R. Shenoy * Program the LPCR via stop-api only if the deepest stop state 10825d298baaSGautham R. Shenoy * can lose hypervisor context. 10835d298baaSGautham R. Shenoy */ 10845d298baaSGautham R. Shenoy if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) 108524be85a2SGautham R. Shenoy opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 108624be85a2SGautham R. Shenoy } 108724be85a2SGautham R. Shenoy 1088c0691f9dSShreyas B. Prabhu /* 1089a7cd88daSGautham R. Shenoy * pnv_cpu_offline: A function that puts the CPU into the deepest 1090a7cd88daSGautham R. Shenoy * available platform idle state on a CPU-Offline. 10912525db04SNicholas Piggin * interrupts hard disabled and no lazy irq pending. 1092a7cd88daSGautham R. Shenoy */ 1093a7cd88daSGautham R. Shenoy unsigned long pnv_cpu_offline(unsigned int cpu) 1094a7cd88daSGautham R. Shenoy { 1095a7cd88daSGautham R. Shenoy unsigned long srr1; 1096a7cd88daSGautham R. Shenoy 109740d24343SNicholas Piggin __ppc64_runlatch_off(); 10982525db04SNicholas Piggin 1099f3b3f284SGautham R. Shenoy if (cpu_has_feature(CPU_FTR_ARCH_300) && deepest_stop_found) { 11002525db04SNicholas Piggin unsigned long psscr; 11012525db04SNicholas Piggin 11022525db04SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 11032525db04SNicholas Piggin psscr = (psscr & ~pnv_deepest_stop_psscr_mask) | 11042525db04SNicholas Piggin pnv_deepest_stop_psscr_val; 1105ffd2961bSNicholas Piggin srr1 = arch300_offline_stop(psscr); 110610d91611SNicholas Piggin } else if (cpu_has_feature(CPU_FTR_ARCH_206) && power7_offline_type) { 110710d91611SNicholas Piggin srr1 = power7_offline(); 110890061231SGautham R. Shenoy } else { 110990061231SGautham R. Shenoy /* This is the fallback method. We emulate snooze */ 111090061231SGautham R. Shenoy while (!generic_check_cpu_restart(cpu)) { 111190061231SGautham R. Shenoy HMT_low(); 111290061231SGautham R. Shenoy HMT_very_low(); 111390061231SGautham R. Shenoy } 111490061231SGautham R. Shenoy srr1 = 0; 111590061231SGautham R. Shenoy HMT_medium(); 1116a7cd88daSGautham R. Shenoy } 1117a7cd88daSGautham R. Shenoy 111840d24343SNicholas Piggin __ppc64_runlatch_on(); 11192525db04SNicholas Piggin 1120a7cd88daSGautham R. Shenoy return srr1; 1121a7cd88daSGautham R. Shenoy } 112267d20418SNicholas Piggin #endif 1123a7cd88daSGautham R. Shenoy 1124a7cd88daSGautham R. Shenoy /* 1125bcef83a0SShreyas B. Prabhu * Power ISA 3.0 idle initialization. 1126bcef83a0SShreyas B. Prabhu * 1127bcef83a0SShreyas B. Prabhu * POWER ISA 3.0 defines a new SPR Processor stop Status and Control 1128bcef83a0SShreyas B. Prabhu * Register (PSSCR) to control idle behavior. 1129bcef83a0SShreyas B. Prabhu * 1130bcef83a0SShreyas B. Prabhu * PSSCR layout: 1131bcef83a0SShreyas B. Prabhu * ---------------------------------------------------------- 1132bcef83a0SShreyas B. Prabhu * | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | 1133bcef83a0SShreyas B. Prabhu * ---------------------------------------------------------- 1134bcef83a0SShreyas B. Prabhu * 0 4 41 42 43 44 48 54 56 60 1135bcef83a0SShreyas B. Prabhu * 1136bcef83a0SShreyas B. Prabhu * PSSCR key fields: 1137bcef83a0SShreyas B. Prabhu * Bits 0:3 - Power-Saving Level Status (PLS). This field indicates the 1138bcef83a0SShreyas B. Prabhu * lowest power-saving state the thread entered since stop instruction was 1139bcef83a0SShreyas B. Prabhu * last executed. 1140bcef83a0SShreyas B. Prabhu * 1141bcef83a0SShreyas B. Prabhu * Bit 41 - Status Disable(SD) 1142bcef83a0SShreyas B. Prabhu * 0 - Shows PLS entries 1143bcef83a0SShreyas B. Prabhu * 1 - PLS entries are all 0 1144bcef83a0SShreyas B. Prabhu * 1145bcef83a0SShreyas B. Prabhu * Bit 42 - Enable State Loss 1146bcef83a0SShreyas B. Prabhu * 0 - No state is lost irrespective of other fields 1147bcef83a0SShreyas B. Prabhu * 1 - Allows state loss 1148bcef83a0SShreyas B. Prabhu * 1149bcef83a0SShreyas B. Prabhu * Bit 43 - Exit Criterion 1150bcef83a0SShreyas B. Prabhu * 0 - Exit from power-save mode on any interrupt 1151bcef83a0SShreyas B. Prabhu * 1 - Exit from power-save mode controlled by LPCR's PECE bits 1152bcef83a0SShreyas B. Prabhu * 1153bcef83a0SShreyas B. Prabhu * Bits 44:47 - Power-Saving Level Limit 1154bcef83a0SShreyas B. Prabhu * This limits the power-saving level that can be entered into. 1155bcef83a0SShreyas B. Prabhu * 1156bcef83a0SShreyas B. Prabhu * Bits 60:63 - Requested Level 1157bcef83a0SShreyas B. Prabhu * Used to specify which power-saving level must be entered on executing 1158bcef83a0SShreyas B. Prabhu * stop instruction 115909206b60SGautham R. Shenoy */ 116009206b60SGautham R. Shenoy 116109206b60SGautham R. Shenoy int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags) 116209206b60SGautham R. Shenoy { 116309206b60SGautham R. Shenoy int err = 0; 116409206b60SGautham R. Shenoy 116509206b60SGautham R. Shenoy /* 116609206b60SGautham R. Shenoy * psscr_mask == 0xf indicates an older firmware. 116709206b60SGautham R. Shenoy * Set remaining fields of psscr to the default values. 116809206b60SGautham R. Shenoy * See NOTE above definition of PSSCR_HV_DEFAULT_VAL 116909206b60SGautham R. Shenoy */ 117009206b60SGautham R. Shenoy if (*psscr_mask == 0xf) { 117109206b60SGautham R. Shenoy *psscr_val = *psscr_val | PSSCR_HV_DEFAULT_VAL; 117209206b60SGautham R. Shenoy *psscr_mask = PSSCR_HV_DEFAULT_MASK; 117309206b60SGautham R. Shenoy return err; 117409206b60SGautham R. Shenoy } 117509206b60SGautham R. Shenoy 117609206b60SGautham R. Shenoy /* 117709206b60SGautham R. Shenoy * New firmware is expected to set the psscr_val bits correctly. 117809206b60SGautham R. Shenoy * Validate that the following invariants are correctly maintained by 117909206b60SGautham R. Shenoy * the new firmware. 118009206b60SGautham R. Shenoy * - ESL bit value matches the EC bit value. 118109206b60SGautham R. Shenoy * - ESL bit is set for all the deep stop states. 118209206b60SGautham R. Shenoy */ 118309206b60SGautham R. Shenoy if (GET_PSSCR_ESL(*psscr_val) != GET_PSSCR_EC(*psscr_val)) { 118409206b60SGautham R. Shenoy err = ERR_EC_ESL_MISMATCH; 118509206b60SGautham R. Shenoy } else if ((flags & OPAL_PM_LOSE_FULL_CONTEXT) && 118609206b60SGautham R. Shenoy GET_PSSCR_ESL(*psscr_val) == 0) { 118709206b60SGautham R. Shenoy err = ERR_DEEP_STATE_ESL_MISMATCH; 118809206b60SGautham R. Shenoy } 118909206b60SGautham R. Shenoy 119009206b60SGautham R. Shenoy return err; 119109206b60SGautham R. Shenoy } 119209206b60SGautham R. Shenoy 119309206b60SGautham R. Shenoy /* 119409206b60SGautham R. Shenoy * pnv_arch300_idle_init: Initializes the default idle state, first 119509206b60SGautham R. Shenoy * deep idle state and deepest idle state on 119609206b60SGautham R. Shenoy * ISA 3.0 CPUs. 1197bcef83a0SShreyas B. Prabhu * 1198bcef83a0SShreyas B. Prabhu * @np: /ibm,opal/power-mgt device node 1199bcef83a0SShreyas B. Prabhu * @flags: cpu-idle-state-flags array 1200bcef83a0SShreyas B. Prabhu * @dt_idle_states: Number of idle state entries 1201bcef83a0SShreyas B. Prabhu * Returns 0 on success 1202bcef83a0SShreyas B. Prabhu */ 1203ffd2961bSNicholas Piggin static void __init pnv_arch300_idle_init(void) 1204bcef83a0SShreyas B. Prabhu { 120509206b60SGautham R. Shenoy u64 max_residency_ns = 0; 12069c7b185aSAkshay Adiga int i; 1207bcef83a0SShreyas B. Prabhu 1208ffd2961bSNicholas Piggin /* stop is not really architected, we only have p9,p10 drivers */ 1209ffd2961bSNicholas Piggin if (!pvr_version_is(PVR_POWER10) && !pvr_version_is(PVR_POWER9)) 1210ffd2961bSNicholas Piggin return; 1211ffd2961bSNicholas Piggin 1212bcef83a0SShreyas B. Prabhu /* 121309206b60SGautham R. Shenoy * pnv_deepest_stop_{val,mask} should be set to values corresponding to 121409206b60SGautham R. Shenoy * the deepest stop state. 121509206b60SGautham R. Shenoy * 121609206b60SGautham R. Shenoy * pnv_default_stop_{val,mask} should be set to values corresponding to 121710d91611SNicholas Piggin * the deepest loss-less (OPAL_PM_STOP_INST_FAST) stop state. 1218bcef83a0SShreyas B. Prabhu */ 121910d91611SNicholas Piggin pnv_first_tb_loss_level = MAX_STOP_STATE + 1; 1220dcbbfa6bSPratik Rajesh Sampat deep_spr_loss_state = MAX_STOP_STATE + 1; 12219c7b185aSAkshay Adiga for (i = 0; i < nr_pnv_idle_states; i++) { 122209206b60SGautham R. Shenoy int err; 12239c7b185aSAkshay Adiga struct pnv_idle_states_t *state = &pnv_idle_states[i]; 12249c7b185aSAkshay Adiga u64 psscr_rl = state->psscr_val & PSSCR_RL_MASK; 1225bcef83a0SShreyas B. Prabhu 1226ffd2961bSNicholas Piggin /* No deep loss driver implemented for POWER10 yet */ 1227ffd2961bSNicholas Piggin if (pvr_version_is(PVR_POWER10) && 1228ffd2961bSNicholas Piggin state->flags & (OPAL_PM_TIMEBASE_STOP|OPAL_PM_LOSE_FULL_CONTEXT)) 1229ffd2961bSNicholas Piggin continue; 1230ffd2961bSNicholas Piggin 123110d91611SNicholas Piggin if ((state->flags & OPAL_PM_TIMEBASE_STOP) && 123210d91611SNicholas Piggin (pnv_first_tb_loss_level > psscr_rl)) 123310d91611SNicholas Piggin pnv_first_tb_loss_level = psscr_rl; 123410d91611SNicholas Piggin 12359c7b185aSAkshay Adiga if ((state->flags & OPAL_PM_LOSE_FULL_CONTEXT) && 1236dcbbfa6bSPratik Rajesh Sampat (deep_spr_loss_state > psscr_rl)) 1237dcbbfa6bSPratik Rajesh Sampat deep_spr_loss_state = psscr_rl; 123810d91611SNicholas Piggin 123910d91611SNicholas Piggin /* 124010d91611SNicholas Piggin * The idle code does not deal with TB loss occurring 124110d91611SNicholas Piggin * in a shallower state than SPR loss, so force it to 124210d91611SNicholas Piggin * behave like SPRs are lost if TB is lost. POWER9 would 124310d91611SNicholas Piggin * never encouter this, but a POWER8 core would if it 124410d91611SNicholas Piggin * implemented the stop instruction. So this is for forward 124510d91611SNicholas Piggin * compatibility. 124610d91611SNicholas Piggin */ 124710d91611SNicholas Piggin if ((state->flags & OPAL_PM_TIMEBASE_STOP) && 1248dcbbfa6bSPratik Rajesh Sampat (deep_spr_loss_state > psscr_rl)) 1249dcbbfa6bSPratik Rajesh Sampat deep_spr_loss_state = psscr_rl; 1250c0691f9dSShreyas B. Prabhu 12519c7b185aSAkshay Adiga err = validate_psscr_val_mask(&state->psscr_val, 12529c7b185aSAkshay Adiga &state->psscr_mask, 12539c7b185aSAkshay Adiga state->flags); 125409206b60SGautham R. Shenoy if (err) { 12559c7b185aSAkshay Adiga report_invalid_psscr_val(state->psscr_val, err); 125609206b60SGautham R. Shenoy continue; 125709206b60SGautham R. Shenoy } 125809206b60SGautham R. Shenoy 12593127692dSNicholas Piggin state->valid = true; 12603127692dSNicholas Piggin 12619c7b185aSAkshay Adiga if (max_residency_ns < state->residency_ns) { 12629c7b185aSAkshay Adiga max_residency_ns = state->residency_ns; 12639c7b185aSAkshay Adiga pnv_deepest_stop_psscr_val = state->psscr_val; 12649c7b185aSAkshay Adiga pnv_deepest_stop_psscr_mask = state->psscr_mask; 12659c7b185aSAkshay Adiga pnv_deepest_stop_flag = state->flags; 126609206b60SGautham R. Shenoy deepest_stop_found = true; 126709206b60SGautham R. Shenoy } 126809206b60SGautham R. Shenoy 126909206b60SGautham R. Shenoy if (!default_stop_found && 12709c7b185aSAkshay Adiga (state->flags & OPAL_PM_STOP_INST_FAST)) { 12719c7b185aSAkshay Adiga pnv_default_stop_val = state->psscr_val; 12729c7b185aSAkshay Adiga pnv_default_stop_mask = state->psscr_mask; 127309206b60SGautham R. Shenoy default_stop_found = true; 127410d91611SNicholas Piggin WARN_ON(state->flags & OPAL_PM_LOSE_FULL_CONTEXT); 127509206b60SGautham R. Shenoy } 127609206b60SGautham R. Shenoy } 127709206b60SGautham R. Shenoy 1278f3b3f284SGautham R. Shenoy if (unlikely(!default_stop_found)) { 1279f3b3f284SGautham R. Shenoy pr_warn("cpuidle-powernv: No suitable default stop state found. Disabling platform idle.\n"); 1280f3b3f284SGautham R. Shenoy } else { 1281ffd2961bSNicholas Piggin ppc_md.power_save = arch300_idle; 1282f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Default stop: psscr = 0x%016llx,mask=0x%016llx\n", 128309206b60SGautham R. Shenoy pnv_default_stop_val, pnv_default_stop_mask); 128409206b60SGautham R. Shenoy } 128509206b60SGautham R. Shenoy 1286f3b3f284SGautham R. Shenoy if (unlikely(!deepest_stop_found)) { 1287f3b3f284SGautham R. Shenoy pr_warn("cpuidle-powernv: No suitable stop state for CPU-Hotplug. Offlined CPUs will busy wait"); 1288f3b3f284SGautham R. Shenoy } else { 1289f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Deepest stop: psscr = 0x%016llx,mask=0x%016llx\n", 129009206b60SGautham R. Shenoy pnv_deepest_stop_psscr_val, 129109206b60SGautham R. Shenoy pnv_deepest_stop_psscr_mask); 1292bcef83a0SShreyas B. Prabhu } 1293bcef83a0SShreyas B. Prabhu 129487997471SShaokun Zhang pr_info("cpuidle-powernv: First stop level that may lose SPRs = 0x%llx\n", 1295dcbbfa6bSPratik Rajesh Sampat deep_spr_loss_state); 12969c7b185aSAkshay Adiga 129787997471SShaokun Zhang pr_info("cpuidle-powernv: First stop level that may lose timebase = 0x%llx\n", 129810d91611SNicholas Piggin pnv_first_tb_loss_level); 129910d91611SNicholas Piggin } 130010d91611SNicholas Piggin 130110d91611SNicholas Piggin static void __init pnv_disable_deep_states(void) 130210d91611SNicholas Piggin { 130310d91611SNicholas Piggin /* 130410d91611SNicholas Piggin * The stop-api is unable to restore hypervisor 130510d91611SNicholas Piggin * resources on wakeup from platform idle states which 130610d91611SNicholas Piggin * lose full context. So disable such states. 130710d91611SNicholas Piggin */ 130810d91611SNicholas Piggin supported_cpuidle_states &= ~OPAL_PM_LOSE_FULL_CONTEXT; 130910d91611SNicholas Piggin pr_warn("cpuidle-powernv: Disabling idle states that lose full context\n"); 131010d91611SNicholas Piggin pr_warn("cpuidle-powernv: Idle power-savings, CPU-Hotplug affected\n"); 131110d91611SNicholas Piggin 131210d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_300) && 131310d91611SNicholas Piggin (pnv_deepest_stop_flag & OPAL_PM_LOSE_FULL_CONTEXT)) { 131410d91611SNicholas Piggin /* 131510d91611SNicholas Piggin * Use the default stop state for CPU-Hotplug 131610d91611SNicholas Piggin * if available. 131710d91611SNicholas Piggin */ 131810d91611SNicholas Piggin if (default_stop_found) { 131910d91611SNicholas Piggin pnv_deepest_stop_psscr_val = pnv_default_stop_val; 132010d91611SNicholas Piggin pnv_deepest_stop_psscr_mask = pnv_default_stop_mask; 132110d91611SNicholas Piggin pr_warn("cpuidle-powernv: Offlined CPUs will stop with psscr = 0x%016llx\n", 132210d91611SNicholas Piggin pnv_deepest_stop_psscr_val); 132310d91611SNicholas Piggin } else { /* Fallback to snooze loop for CPU-Hotplug */ 132410d91611SNicholas Piggin deepest_stop_found = false; 132510d91611SNicholas Piggin pr_warn("cpuidle-powernv: Offlined CPUs will busy wait\n"); 132610d91611SNicholas Piggin } 132710d91611SNicholas Piggin } 1328bcef83a0SShreyas B. Prabhu } 1329bcef83a0SShreyas B. Prabhu 1330bcef83a0SShreyas B. Prabhu /* 1331bcef83a0SShreyas B. Prabhu * Probe device tree for supported idle states 1332bcef83a0SShreyas B. Prabhu */ 1333bcef83a0SShreyas B. Prabhu static void __init pnv_probe_idle_states(void) 1334bcef83a0SShreyas B. Prabhu { 1335d405a98cSShreyas B. Prabhu int i; 1336d405a98cSShreyas B. Prabhu 13379c7b185aSAkshay Adiga if (nr_pnv_idle_states < 0) { 13389c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: no idle states found in the DT\n"); 13399c7b185aSAkshay Adiga return; 13409c7b185aSAkshay Adiga } 13419c7b185aSAkshay Adiga 134216d83a54SPratik Rajesh Sampat if (cpu_has_feature(CPU_FTR_ARCH_300)) 1343ffd2961bSNicholas Piggin pnv_arch300_idle_init(); 13449c7b185aSAkshay Adiga 13459c7b185aSAkshay Adiga for (i = 0; i < nr_pnv_idle_states; i++) 13469c7b185aSAkshay Adiga supported_cpuidle_states |= pnv_idle_states[i].flags; 13479c7b185aSAkshay Adiga } 13489c7b185aSAkshay Adiga 13499c7b185aSAkshay Adiga /* 13509c7b185aSAkshay Adiga * This function parses device-tree and populates all the information 13519c7b185aSAkshay Adiga * into pnv_idle_states structure. It also sets up nr_pnv_idle_states 13529c7b185aSAkshay Adiga * which is the number of cpuidle states discovered through device-tree. 13539c7b185aSAkshay Adiga */ 13549c7b185aSAkshay Adiga 13559c7b185aSAkshay Adiga static int pnv_parse_cpuidle_dt(void) 13569c7b185aSAkshay Adiga { 13579c7b185aSAkshay Adiga struct device_node *np; 13589c7b185aSAkshay Adiga int nr_idle_states, i; 13599c7b185aSAkshay Adiga int rc = 0; 13609c7b185aSAkshay Adiga u32 *temp_u32; 13619c7b185aSAkshay Adiga u64 *temp_u64; 13629c7b185aSAkshay Adiga const char **temp_string; 13639c7b185aSAkshay Adiga 1364bcef83a0SShreyas B. Prabhu np = of_find_node_by_path("/ibm,opal/power-mgt"); 1365bcef83a0SShreyas B. Prabhu if (!np) { 1366d405a98cSShreyas B. Prabhu pr_warn("opal: PowerMgmt Node not found\n"); 13679c7b185aSAkshay Adiga return -ENODEV; 1368d405a98cSShreyas B. Prabhu } 13699c7b185aSAkshay Adiga nr_idle_states = of_property_count_u32_elems(np, 1370d405a98cSShreyas B. Prabhu "ibm,cpu-idle-state-flags"); 13719c7b185aSAkshay Adiga 13729c7b185aSAkshay Adiga pnv_idle_states = kcalloc(nr_idle_states, sizeof(*pnv_idle_states), 13739c7b185aSAkshay Adiga GFP_KERNEL); 13749c7b185aSAkshay Adiga temp_u32 = kcalloc(nr_idle_states, sizeof(u32), GFP_KERNEL); 13759c7b185aSAkshay Adiga temp_u64 = kcalloc(nr_idle_states, sizeof(u64), GFP_KERNEL); 13769c7b185aSAkshay Adiga temp_string = kcalloc(nr_idle_states, sizeof(char *), GFP_KERNEL); 13779c7b185aSAkshay Adiga 13789c7b185aSAkshay Adiga if (!(pnv_idle_states && temp_u32 && temp_u64 && temp_string)) { 13799c7b185aSAkshay Adiga pr_err("Could not allocate memory for dt parsing\n"); 13809c7b185aSAkshay Adiga rc = -ENOMEM; 1381d405a98cSShreyas B. Prabhu goto out; 1382d405a98cSShreyas B. Prabhu } 1383d405a98cSShreyas B. Prabhu 13849c7b185aSAkshay Adiga /* Read flags */ 13859c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-flags", 13869c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 1387d405a98cSShreyas B. Prabhu pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n"); 13889c7b185aSAkshay Adiga rc = -EINVAL; 1389bcef83a0SShreyas B. Prabhu goto out; 1390bcef83a0SShreyas B. Prabhu } 13919c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 13929c7b185aSAkshay Adiga pnv_idle_states[i].flags = temp_u32[i]; 1393bcef83a0SShreyas B. Prabhu 13949c7b185aSAkshay Adiga /* Read latencies */ 13959c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-latencies-ns", 13969c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 13979c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-latencies-ns in DT\n"); 13989c7b185aSAkshay Adiga rc = -EINVAL; 13999c7b185aSAkshay Adiga goto out; 14009c7b185aSAkshay Adiga } 14019c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 14029c7b185aSAkshay Adiga pnv_idle_states[i].latency_ns = temp_u32[i]; 14039c7b185aSAkshay Adiga 14049c7b185aSAkshay Adiga /* Read residencies */ 14059c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-residency-ns", 14069c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 14072f62870cSChristophe JAILLET pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-residency-ns in DT\n"); 14089c7b185aSAkshay Adiga rc = -EINVAL; 14099c7b185aSAkshay Adiga goto out; 14109c7b185aSAkshay Adiga } 14119c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 14129c7b185aSAkshay Adiga pnv_idle_states[i].residency_ns = temp_u32[i]; 14139c7b185aSAkshay Adiga 1414ffd2961bSNicholas Piggin /* For power9 and later */ 1415bcef83a0SShreyas B. Prabhu if (cpu_has_feature(CPU_FTR_ARCH_300)) { 14169c7b185aSAkshay Adiga /* Read pm_crtl_val */ 14179c7b185aSAkshay Adiga if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr", 14189c7b185aSAkshay Adiga temp_u64, nr_idle_states)) { 14199c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n"); 14209c7b185aSAkshay Adiga rc = -EINVAL; 1421bcef83a0SShreyas B. Prabhu goto out; 1422d405a98cSShreyas B. Prabhu } 14239c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 14249c7b185aSAkshay Adiga pnv_idle_states[i].psscr_val = temp_u64[i]; 1425d405a98cSShreyas B. Prabhu 14269c7b185aSAkshay Adiga /* Read pm_crtl_mask */ 14279c7b185aSAkshay Adiga if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr-mask", 14289c7b185aSAkshay Adiga temp_u64, nr_idle_states)) { 14299c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n"); 14309c7b185aSAkshay Adiga rc = -EINVAL; 14319c7b185aSAkshay Adiga goto out; 1432bcef83a0SShreyas B. Prabhu } 14339c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 14349c7b185aSAkshay Adiga pnv_idle_states[i].psscr_mask = temp_u64[i]; 14359c7b185aSAkshay Adiga } 14369c7b185aSAkshay Adiga 14379c7b185aSAkshay Adiga /* 14389c7b185aSAkshay Adiga * power8 specific properties ibm,cpu-idle-state-pmicr-mask and 14399c7b185aSAkshay Adiga * ibm,cpu-idle-state-pmicr-val were never used and there is no 14409c7b185aSAkshay Adiga * plan to use it in near future. Hence, not parsing these properties 14419c7b185aSAkshay Adiga */ 14429c7b185aSAkshay Adiga 14439c7b185aSAkshay Adiga if (of_property_read_string_array(np, "ibm,cpu-idle-state-names", 14449c7b185aSAkshay Adiga temp_string, nr_idle_states) < 0) { 14459c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-names in DT\n"); 14469c7b185aSAkshay Adiga rc = -EINVAL; 14479c7b185aSAkshay Adiga goto out; 14489c7b185aSAkshay Adiga } 14499c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 1450ae24ce5eSAneesh Kumar K.V strlcpy(pnv_idle_states[i].name, temp_string[i], 14519c7b185aSAkshay Adiga PNV_IDLE_NAME_LEN); 14529c7b185aSAkshay Adiga nr_pnv_idle_states = nr_idle_states; 14539c7b185aSAkshay Adiga rc = 0; 14549c7b185aSAkshay Adiga out: 14559c7b185aSAkshay Adiga kfree(temp_u32); 14569c7b185aSAkshay Adiga kfree(temp_u64); 14579c7b185aSAkshay Adiga kfree(temp_string); 14589c7b185aSAkshay Adiga return rc; 14599c7b185aSAkshay Adiga } 14609c7b185aSAkshay Adiga 1461bcef83a0SShreyas B. Prabhu static int __init pnv_init_idle_states(void) 1462bcef83a0SShreyas B. Prabhu { 146310d91611SNicholas Piggin int cpu; 14649c7b185aSAkshay Adiga int rc = 0; 146510d91611SNicholas Piggin 146610d91611SNicholas Piggin /* Set up PACA fields */ 146710d91611SNicholas Piggin for_each_present_cpu(cpu) { 146810d91611SNicholas Piggin struct paca_struct *p = paca_ptrs[cpu]; 146910d91611SNicholas Piggin 147010d91611SNicholas Piggin p->idle_state = 0; 147110d91611SNicholas Piggin if (cpu == cpu_first_thread_sibling(cpu)) 147210d91611SNicholas Piggin p->idle_state = (1 << threads_per_core) - 1; 147310d91611SNicholas Piggin 147410d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 147510d91611SNicholas Piggin /* P7/P8 nap */ 147610d91611SNicholas Piggin p->thread_idle_state = PNV_THREAD_RUNNING; 1477ffd2961bSNicholas Piggin } else if (pvr_version_is(PVR_POWER9)) { 1478ffd2961bSNicholas Piggin /* P9 stop workarounds */ 147910d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 148010d91611SNicholas Piggin p->requested_psscr = 0; 148110d91611SNicholas Piggin atomic_set(&p->dont_stop, 0); 148210d91611SNicholas Piggin #endif 148310d91611SNicholas Piggin } 148410d91611SNicholas Piggin } 1485bcef83a0SShreyas B. Prabhu 14869c7b185aSAkshay Adiga /* In case we error out nr_pnv_idle_states will be zero */ 14879c7b185aSAkshay Adiga nr_pnv_idle_states = 0; 148810d91611SNicholas Piggin supported_cpuidle_states = 0; 148910d91611SNicholas Piggin 1490bcef83a0SShreyas B. Prabhu if (cpuidle_disable != IDLE_NO_OVERRIDE) 1491bcef83a0SShreyas B. Prabhu goto out; 14929c7b185aSAkshay Adiga rc = pnv_parse_cpuidle_dt(); 14939c7b185aSAkshay Adiga if (rc) 14949c7b185aSAkshay Adiga return rc; 1495bcef83a0SShreyas B. Prabhu pnv_probe_idle_states(); 1496bcef83a0SShreyas B. Prabhu 149710d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1498d405a98cSShreyas B. Prabhu if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { 149910d91611SNicholas Piggin power7_fastsleep_workaround_entry = false; 150010d91611SNicholas Piggin power7_fastsleep_workaround_exit = false; 15015703d2f4SShreyas B. Prabhu } else { 15025703d2f4SShreyas B. Prabhu /* 15035703d2f4SShreyas B. Prabhu * OPAL_PM_SLEEP_ENABLED_ER1 is set. It indicates that 15045703d2f4SShreyas B. Prabhu * workaround is needed to use fastsleep. Provide sysfs 150510d91611SNicholas Piggin * control to choose how this workaround has to be 150610d91611SNicholas Piggin * applied. 15075703d2f4SShreyas B. Prabhu */ 15085703d2f4SShreyas B. Prabhu device_create_file(cpu_subsys.dev_root, 15095703d2f4SShreyas B. Prabhu &dev_attr_fastsleep_workaround_applyonce); 1510d405a98cSShreyas B. Prabhu } 15115703d2f4SShreyas B. Prabhu 151210d91611SNicholas Piggin update_subcore_sibling_mask(); 15135593e303SShreyas B. Prabhu 151410d91611SNicholas Piggin if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED) { 15155593e303SShreyas B. Prabhu ppc_md.power_save = power7_idle; 151610d91611SNicholas Piggin power7_offline_type = PNV_THREAD_NAP; 151710d91611SNicholas Piggin } 151810d91611SNicholas Piggin 151910d91611SNicholas Piggin if ((supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED) && 152010d91611SNicholas Piggin (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT)) 152110d91611SNicholas Piggin power7_offline_type = PNV_THREAD_WINKLE; 152210d91611SNicholas Piggin else if ((supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED) || 152310d91611SNicholas Piggin (supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) 152410d91611SNicholas Piggin power7_offline_type = PNV_THREAD_SLEEP; 152510d91611SNicholas Piggin } 152610d91611SNicholas Piggin 152710d91611SNicholas Piggin if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) { 152810d91611SNicholas Piggin if (pnv_save_sprs_for_deep_states()) 152910d91611SNicholas Piggin pnv_disable_deep_states(); 153010d91611SNicholas Piggin } 1531bcef83a0SShreyas B. Prabhu 1532d405a98cSShreyas B. Prabhu out: 1533d405a98cSShreyas B. Prabhu return 0; 1534d405a98cSShreyas B. Prabhu } 15354bece972SMichael Ellerman machine_subsys_initcall(powernv, pnv_init_idle_states); 1536