1d405a98cSShreyas B. Prabhu /* 2d405a98cSShreyas B. Prabhu * PowerNV cpuidle code 3d405a98cSShreyas B. Prabhu * 4d405a98cSShreyas B. Prabhu * Copyright 2015 IBM Corp. 5d405a98cSShreyas B. Prabhu * 6d405a98cSShreyas B. Prabhu * This program is free software; you can redistribute it and/or 7d405a98cSShreyas B. Prabhu * modify it under the terms of the GNU General Public License 8d405a98cSShreyas B. Prabhu * as published by the Free Software Foundation; either version 9d405a98cSShreyas B. Prabhu * 2 of the License, or (at your option) any later version. 10d405a98cSShreyas B. Prabhu */ 11d405a98cSShreyas B. Prabhu 12d405a98cSShreyas B. Prabhu #include <linux/types.h> 13d405a98cSShreyas B. Prabhu #include <linux/mm.h> 14d405a98cSShreyas B. Prabhu #include <linux/slab.h> 15d405a98cSShreyas B. Prabhu #include <linux/of.h> 165703d2f4SShreyas B. Prabhu #include <linux/device.h> 175703d2f4SShreyas B. Prabhu #include <linux/cpu.h> 18d405a98cSShreyas B. Prabhu 1910d91611SNicholas Piggin #include <asm/asm-prototypes.h> 20d405a98cSShreyas B. Prabhu #include <asm/firmware.h> 214bece972SMichael Ellerman #include <asm/machdep.h> 22d405a98cSShreyas B. Prabhu #include <asm/opal.h> 23d405a98cSShreyas B. Prabhu #include <asm/cputhreads.h> 24d405a98cSShreyas B. Prabhu #include <asm/cpuidle.h> 25d405a98cSShreyas B. Prabhu #include <asm/code-patching.h> 26d405a98cSShreyas B. Prabhu #include <asm/smp.h> 272201f994SNicholas Piggin #include <asm/runlatch.h> 287672691aSPaul Mackerras #include <asm/dbell.h> 29d405a98cSShreyas B. Prabhu 30d405a98cSShreyas B. Prabhu #include "powernv.h" 31d405a98cSShreyas B. Prabhu #include "subcore.h" 32d405a98cSShreyas B. Prabhu 33bcef83a0SShreyas B. Prabhu /* Power ISA 3.0 allows for stop states 0x0 - 0xF */ 34bcef83a0SShreyas B. Prabhu #define MAX_STOP_STATE 0xF 35bcef83a0SShreyas B. Prabhu 361e1601b3SAkshay Adiga #define P9_STOP_SPR_MSR 2000 371e1601b3SAkshay Adiga #define P9_STOP_SPR_PSSCR 855 381e1601b3SAkshay Adiga 39d405a98cSShreyas B. Prabhu static u32 supported_cpuidle_states; 409c7b185aSAkshay Adiga struct pnv_idle_states_t *pnv_idle_states; 419c7b185aSAkshay Adiga int nr_pnv_idle_states; 42d405a98cSShreyas B. Prabhu 431e1601b3SAkshay Adiga /* 441e1601b3SAkshay Adiga * The default stop state that will be used by ppc_md.power_save 451e1601b3SAkshay Adiga * function on platforms that support stop instruction. 461e1601b3SAkshay Adiga */ 471e1601b3SAkshay Adiga static u64 pnv_default_stop_val; 481e1601b3SAkshay Adiga static u64 pnv_default_stop_mask; 491e1601b3SAkshay Adiga static bool default_stop_found; 501e1601b3SAkshay Adiga 511e1601b3SAkshay Adiga /* 5210d91611SNicholas Piggin * First stop state levels when SPR and TB loss can occur. 531e1601b3SAkshay Adiga */ 5410d91611SNicholas Piggin static u64 pnv_first_tb_loss_level = MAX_STOP_STATE + 1; 5510d91611SNicholas Piggin static u64 pnv_first_spr_loss_level = MAX_STOP_STATE + 1; 561e1601b3SAkshay Adiga 571e1601b3SAkshay Adiga /* 581e1601b3SAkshay Adiga * psscr value and mask of the deepest stop idle state. 591e1601b3SAkshay Adiga * Used when a cpu is offlined. 601e1601b3SAkshay Adiga */ 611e1601b3SAkshay Adiga static u64 pnv_deepest_stop_psscr_val; 621e1601b3SAkshay Adiga static u64 pnv_deepest_stop_psscr_mask; 63785a12afSGautham R. Shenoy static u64 pnv_deepest_stop_flag; 641e1601b3SAkshay Adiga static bool deepest_stop_found; 651e1601b3SAkshay Adiga 6610d91611SNicholas Piggin static unsigned long power7_offline_type; 6710d91611SNicholas Piggin 68bcef83a0SShreyas B. Prabhu static int pnv_save_sprs_for_deep_states(void) 69d405a98cSShreyas B. Prabhu { 70d405a98cSShreyas B. Prabhu int cpu; 71d405a98cSShreyas B. Prabhu int rc; 72d405a98cSShreyas B. Prabhu 73d405a98cSShreyas B. Prabhu /* 74446957baSAdam Buchbinder * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across 75d405a98cSShreyas B. Prabhu * all cpus at boot. Get these reg values of current cpu and use the 76446957baSAdam Buchbinder * same across all cpus. 77d405a98cSShreyas B. Prabhu */ 7824be85a2SGautham R. Shenoy uint64_t lpcr_val = mfspr(SPRN_LPCR); 79d405a98cSShreyas B. Prabhu uint64_t hid0_val = mfspr(SPRN_HID0); 80d405a98cSShreyas B. Prabhu uint64_t hid1_val = mfspr(SPRN_HID1); 81d405a98cSShreyas B. Prabhu uint64_t hid4_val = mfspr(SPRN_HID4); 82d405a98cSShreyas B. Prabhu uint64_t hid5_val = mfspr(SPRN_HID5); 83d405a98cSShreyas B. Prabhu uint64_t hmeer_val = mfspr(SPRN_HMEER); 841e1601b3SAkshay Adiga uint64_t msr_val = MSR_IDLE; 851e1601b3SAkshay Adiga uint64_t psscr_val = pnv_deepest_stop_psscr_val; 86d405a98cSShreyas B. Prabhu 87ac9816dcSAkshay Adiga for_each_present_cpu(cpu) { 88d405a98cSShreyas B. Prabhu uint64_t pir = get_hard_smp_processor_id(cpu); 89d2e60075SNicholas Piggin uint64_t hsprg0_val = (uint64_t)paca_ptrs[cpu]; 90d405a98cSShreyas B. Prabhu 91d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); 92d405a98cSShreyas B. Prabhu if (rc != 0) 93d405a98cSShreyas B. Prabhu return rc; 94d405a98cSShreyas B. Prabhu 95d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 96d405a98cSShreyas B. Prabhu if (rc != 0) 97d405a98cSShreyas B. Prabhu return rc; 98d405a98cSShreyas B. Prabhu 991e1601b3SAkshay Adiga if (cpu_has_feature(CPU_FTR_ARCH_300)) { 1001e1601b3SAkshay Adiga rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); 1011e1601b3SAkshay Adiga if (rc) 1021e1601b3SAkshay Adiga return rc; 1031e1601b3SAkshay Adiga 1041e1601b3SAkshay Adiga rc = opal_slw_set_reg(pir, 1051e1601b3SAkshay Adiga P9_STOP_SPR_PSSCR, psscr_val); 1061e1601b3SAkshay Adiga 1071e1601b3SAkshay Adiga if (rc) 1081e1601b3SAkshay Adiga return rc; 1091e1601b3SAkshay Adiga } 1101e1601b3SAkshay Adiga 111d405a98cSShreyas B. Prabhu /* HIDs are per core registers */ 112d405a98cSShreyas B. Prabhu if (cpu_thread_in_core(cpu) == 0) { 113d405a98cSShreyas B. Prabhu 114d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); 115d405a98cSShreyas B. Prabhu if (rc != 0) 116d405a98cSShreyas B. Prabhu return rc; 117d405a98cSShreyas B. Prabhu 118d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); 119d405a98cSShreyas B. Prabhu if (rc != 0) 120d405a98cSShreyas B. Prabhu return rc; 121d405a98cSShreyas B. Prabhu 1221e1601b3SAkshay Adiga /* Only p8 needs to set extra HID regiters */ 1231e1601b3SAkshay Adiga if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1241e1601b3SAkshay Adiga 125d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); 126d405a98cSShreyas B. Prabhu if (rc != 0) 127d405a98cSShreyas B. Prabhu return rc; 128d405a98cSShreyas B. Prabhu 129d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); 130d405a98cSShreyas B. Prabhu if (rc != 0) 131d405a98cSShreyas B. Prabhu return rc; 132d405a98cSShreyas B. Prabhu 133d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); 134d405a98cSShreyas B. Prabhu if (rc != 0) 135d405a98cSShreyas B. Prabhu return rc; 136d405a98cSShreyas B. Prabhu } 137d405a98cSShreyas B. Prabhu } 1381e1601b3SAkshay Adiga } 139d405a98cSShreyas B. Prabhu 140d405a98cSShreyas B. Prabhu return 0; 141d405a98cSShreyas B. Prabhu } 142d405a98cSShreyas B. Prabhu 143d405a98cSShreyas B. Prabhu u32 pnv_get_supported_cpuidle_states(void) 144d405a98cSShreyas B. Prabhu { 145d405a98cSShreyas B. Prabhu return supported_cpuidle_states; 146d405a98cSShreyas B. Prabhu } 147d405a98cSShreyas B. Prabhu EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states); 148d405a98cSShreyas B. Prabhu 1495703d2f4SShreyas B. Prabhu static void pnv_fastsleep_workaround_apply(void *info) 1505703d2f4SShreyas B. Prabhu 1515703d2f4SShreyas B. Prabhu { 1525703d2f4SShreyas B. Prabhu int rc; 1535703d2f4SShreyas B. Prabhu int *err = info; 1545703d2f4SShreyas B. Prabhu 1555703d2f4SShreyas B. Prabhu rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 1565703d2f4SShreyas B. Prabhu OPAL_CONFIG_IDLE_APPLY); 1575703d2f4SShreyas B. Prabhu if (rc) 1585703d2f4SShreyas B. Prabhu *err = 1; 1595703d2f4SShreyas B. Prabhu } 1605703d2f4SShreyas B. Prabhu 16110d91611SNicholas Piggin static bool power7_fastsleep_workaround_entry = true; 16210d91611SNicholas Piggin static bool power7_fastsleep_workaround_exit = true; 16310d91611SNicholas Piggin 1645703d2f4SShreyas B. Prabhu /* 1655703d2f4SShreyas B. Prabhu * Used to store fastsleep workaround state 1665703d2f4SShreyas B. Prabhu * 0 - Workaround applied/undone at fastsleep entry/exit path (Default) 1675703d2f4SShreyas B. Prabhu * 1 - Workaround applied once, never undone. 1685703d2f4SShreyas B. Prabhu */ 1695703d2f4SShreyas B. Prabhu static u8 fastsleep_workaround_applyonce; 1705703d2f4SShreyas B. Prabhu 1715703d2f4SShreyas B. Prabhu static ssize_t show_fastsleep_workaround_applyonce(struct device *dev, 1725703d2f4SShreyas B. Prabhu struct device_attribute *attr, char *buf) 1735703d2f4SShreyas B. Prabhu { 1745703d2f4SShreyas B. Prabhu return sprintf(buf, "%u\n", fastsleep_workaround_applyonce); 1755703d2f4SShreyas B. Prabhu } 1765703d2f4SShreyas B. Prabhu 1775703d2f4SShreyas B. Prabhu static ssize_t store_fastsleep_workaround_applyonce(struct device *dev, 1785703d2f4SShreyas B. Prabhu struct device_attribute *attr, const char *buf, 1795703d2f4SShreyas B. Prabhu size_t count) 1805703d2f4SShreyas B. Prabhu { 1815703d2f4SShreyas B. Prabhu cpumask_t primary_thread_mask; 1825703d2f4SShreyas B. Prabhu int err; 1835703d2f4SShreyas B. Prabhu u8 val; 1845703d2f4SShreyas B. Prabhu 1855703d2f4SShreyas B. Prabhu if (kstrtou8(buf, 0, &val) || val != 1) 1865703d2f4SShreyas B. Prabhu return -EINVAL; 1875703d2f4SShreyas B. Prabhu 1885703d2f4SShreyas B. Prabhu if (fastsleep_workaround_applyonce == 1) 1895703d2f4SShreyas B. Prabhu return count; 1905703d2f4SShreyas B. Prabhu 1915703d2f4SShreyas B. Prabhu /* 1925703d2f4SShreyas B. Prabhu * fastsleep_workaround_applyonce = 1 implies 1935703d2f4SShreyas B. Prabhu * fastsleep workaround needs to be left in 'applied' state on all 1945703d2f4SShreyas B. Prabhu * the cores. Do this by- 19510d91611SNicholas Piggin * 1. Disable the 'undo' workaround in fastsleep exit path 19610d91611SNicholas Piggin * 2. Sendi IPIs to all the cores which have at least one online thread 19710d91611SNicholas Piggin * 3. Disable the 'apply' workaround in fastsleep entry path 19810d91611SNicholas Piggin * 1995703d2f4SShreyas B. Prabhu * There is no need to send ipi to cores which have all threads 2005703d2f4SShreyas B. Prabhu * offlined, as last thread of the core entering fastsleep or deeper 2015703d2f4SShreyas B. Prabhu * state would have applied workaround. 2025703d2f4SShreyas B. Prabhu */ 20310d91611SNicholas Piggin power7_fastsleep_workaround_exit = false; 2045703d2f4SShreyas B. Prabhu 2055703d2f4SShreyas B. Prabhu get_online_cpus(); 2065703d2f4SShreyas B. Prabhu primary_thread_mask = cpu_online_cores_map(); 2075703d2f4SShreyas B. Prabhu on_each_cpu_mask(&primary_thread_mask, 2085703d2f4SShreyas B. Prabhu pnv_fastsleep_workaround_apply, 2095703d2f4SShreyas B. Prabhu &err, 1); 2105703d2f4SShreyas B. Prabhu put_online_cpus(); 2115703d2f4SShreyas B. Prabhu if (err) { 2125703d2f4SShreyas B. Prabhu pr_err("fastsleep_workaround_applyonce change failed while running pnv_fastsleep_workaround_apply"); 2135703d2f4SShreyas B. Prabhu goto fail; 2145703d2f4SShreyas B. Prabhu } 2155703d2f4SShreyas B. Prabhu 21610d91611SNicholas Piggin power7_fastsleep_workaround_entry = false; 2175703d2f4SShreyas B. Prabhu 2185703d2f4SShreyas B. Prabhu fastsleep_workaround_applyonce = 1; 2195703d2f4SShreyas B. Prabhu 2205703d2f4SShreyas B. Prabhu return count; 2215703d2f4SShreyas B. Prabhu fail: 2225703d2f4SShreyas B. Prabhu return -EIO; 2235703d2f4SShreyas B. Prabhu } 2245703d2f4SShreyas B. Prabhu 2255703d2f4SShreyas B. Prabhu static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600, 2265703d2f4SShreyas B. Prabhu show_fastsleep_workaround_applyonce, 2275703d2f4SShreyas B. Prabhu store_fastsleep_workaround_applyonce); 2285703d2f4SShreyas B. Prabhu 22910d91611SNicholas Piggin static inline void atomic_start_thread_idle(void) 2302201f994SNicholas Piggin { 23110d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 23210d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 23310d91611SNicholas Piggin int thread_nr = cpu_thread_in_core(cpu); 23410d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 23510d91611SNicholas Piggin 23610d91611SNicholas Piggin clear_bit(thread_nr, state); 23710d91611SNicholas Piggin } 23810d91611SNicholas Piggin 23910d91611SNicholas Piggin static inline void atomic_stop_thread_idle(void) 24010d91611SNicholas Piggin { 24110d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 24210d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 24310d91611SNicholas Piggin int thread_nr = cpu_thread_in_core(cpu); 24410d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 24510d91611SNicholas Piggin 24610d91611SNicholas Piggin set_bit(thread_nr, state); 24710d91611SNicholas Piggin } 24810d91611SNicholas Piggin 24910d91611SNicholas Piggin static inline void atomic_lock_thread_idle(void) 25010d91611SNicholas Piggin { 25110d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 25210d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 25310d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 25410d91611SNicholas Piggin 25510d91611SNicholas Piggin while (unlikely(test_and_set_bit_lock(NR_PNV_CORE_IDLE_LOCK_BIT, state))) 25610d91611SNicholas Piggin barrier(); 25710d91611SNicholas Piggin } 25810d91611SNicholas Piggin 25910d91611SNicholas Piggin static inline void atomic_unlock_and_stop_thread_idle(void) 26010d91611SNicholas Piggin { 26110d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 26210d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 26310d91611SNicholas Piggin unsigned long thread = 1UL << cpu_thread_in_core(cpu); 26410d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 26510d91611SNicholas Piggin u64 s = READ_ONCE(*state); 26610d91611SNicholas Piggin u64 new, tmp; 26710d91611SNicholas Piggin 26810d91611SNicholas Piggin BUG_ON(!(s & PNV_CORE_IDLE_LOCK_BIT)); 26910d91611SNicholas Piggin BUG_ON(s & thread); 27010d91611SNicholas Piggin 27110d91611SNicholas Piggin again: 27210d91611SNicholas Piggin new = (s | thread) & ~PNV_CORE_IDLE_LOCK_BIT; 27310d91611SNicholas Piggin tmp = cmpxchg(state, s, new); 27410d91611SNicholas Piggin if (unlikely(tmp != s)) { 27510d91611SNicholas Piggin s = tmp; 27610d91611SNicholas Piggin goto again; 27710d91611SNicholas Piggin } 27810d91611SNicholas Piggin } 27910d91611SNicholas Piggin 28010d91611SNicholas Piggin static inline void atomic_unlock_thread_idle(void) 28110d91611SNicholas Piggin { 28210d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 28310d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 28410d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 28510d91611SNicholas Piggin 28610d91611SNicholas Piggin BUG_ON(!test_bit(NR_PNV_CORE_IDLE_LOCK_BIT, state)); 28710d91611SNicholas Piggin clear_bit_unlock(NR_PNV_CORE_IDLE_LOCK_BIT, state); 28810d91611SNicholas Piggin } 28910d91611SNicholas Piggin 29010d91611SNicholas Piggin /* P7 and P8 */ 29110d91611SNicholas Piggin struct p7_sprs { 29210d91611SNicholas Piggin /* per core */ 29310d91611SNicholas Piggin u64 tscr; 29410d91611SNicholas Piggin u64 worc; 29510d91611SNicholas Piggin 29610d91611SNicholas Piggin /* per subcore */ 29710d91611SNicholas Piggin u64 sdr1; 29810d91611SNicholas Piggin u64 rpr; 29910d91611SNicholas Piggin 30010d91611SNicholas Piggin /* per thread */ 30110d91611SNicholas Piggin u64 lpcr; 30210d91611SNicholas Piggin u64 hfscr; 30310d91611SNicholas Piggin u64 fscr; 30410d91611SNicholas Piggin u64 purr; 30510d91611SNicholas Piggin u64 spurr; 30610d91611SNicholas Piggin u64 dscr; 30710d91611SNicholas Piggin u64 wort; 308e9cef018SMichael Ellerman 309e9cef018SMichael Ellerman /* per thread SPRs that get lost in shallow states */ 310e9cef018SMichael Ellerman u64 amr; 311e9cef018SMichael Ellerman u64 iamr; 312e9cef018SMichael Ellerman u64 amor; 313e9cef018SMichael Ellerman u64 uamor; 31410d91611SNicholas Piggin }; 31510d91611SNicholas Piggin 31610d91611SNicholas Piggin static unsigned long power7_idle_insn(unsigned long type) 31710d91611SNicholas Piggin { 31810d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 31910d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 32010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 32110d91611SNicholas Piggin unsigned long thread = 1UL << cpu_thread_in_core(cpu); 32210d91611SNicholas Piggin unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 3232201f994SNicholas Piggin unsigned long srr1; 32410d91611SNicholas Piggin bool full_winkle; 32510d91611SNicholas Piggin struct p7_sprs sprs = {}; /* avoid false use-uninitialised */ 32610d91611SNicholas Piggin bool sprs_saved = false; 32710d91611SNicholas Piggin int rc; 3282201f994SNicholas Piggin 32910d91611SNicholas Piggin if (unlikely(type != PNV_THREAD_NAP)) { 33010d91611SNicholas Piggin atomic_lock_thread_idle(); 3312201f994SNicholas Piggin 33210d91611SNicholas Piggin BUG_ON(!(*state & thread)); 33310d91611SNicholas Piggin *state &= ~thread; 3342201f994SNicholas Piggin 33510d91611SNicholas Piggin if (power7_fastsleep_workaround_entry) { 33610d91611SNicholas Piggin if ((*state & core_thread_mask) == 0) { 33710d91611SNicholas Piggin rc = opal_config_cpu_idle_state( 33810d91611SNicholas Piggin OPAL_CONFIG_IDLE_FASTSLEEP, 33910d91611SNicholas Piggin OPAL_CONFIG_IDLE_APPLY); 34010d91611SNicholas Piggin BUG_ON(rc); 34110d91611SNicholas Piggin } 34210d91611SNicholas Piggin } 34310d91611SNicholas Piggin 34410d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 34510d91611SNicholas Piggin sprs.tscr = mfspr(SPRN_TSCR); 34610d91611SNicholas Piggin sprs.worc = mfspr(SPRN_WORC); 34710d91611SNicholas Piggin 34810d91611SNicholas Piggin sprs.sdr1 = mfspr(SPRN_SDR1); 34910d91611SNicholas Piggin sprs.rpr = mfspr(SPRN_RPR); 35010d91611SNicholas Piggin 35110d91611SNicholas Piggin sprs.lpcr = mfspr(SPRN_LPCR); 35210d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 35310d91611SNicholas Piggin sprs.hfscr = mfspr(SPRN_HFSCR); 35410d91611SNicholas Piggin sprs.fscr = mfspr(SPRN_FSCR); 35510d91611SNicholas Piggin } 35610d91611SNicholas Piggin sprs.purr = mfspr(SPRN_PURR); 35710d91611SNicholas Piggin sprs.spurr = mfspr(SPRN_SPURR); 35810d91611SNicholas Piggin sprs.dscr = mfspr(SPRN_DSCR); 35910d91611SNicholas Piggin sprs.wort = mfspr(SPRN_WORT); 36010d91611SNicholas Piggin 36110d91611SNicholas Piggin sprs_saved = true; 36210d91611SNicholas Piggin 36310d91611SNicholas Piggin /* 36410d91611SNicholas Piggin * Increment winkle counter and set all winkle bits if 36510d91611SNicholas Piggin * all threads are winkling. This allows wakeup side to 36610d91611SNicholas Piggin * distinguish between fast sleep and winkle state 36710d91611SNicholas Piggin * loss. Fast sleep still has to resync the timebase so 36810d91611SNicholas Piggin * this may not be a really big win. 36910d91611SNicholas Piggin */ 37010d91611SNicholas Piggin *state += 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 37110d91611SNicholas Piggin if ((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) 37210d91611SNicholas Piggin >> PNV_CORE_IDLE_WINKLE_COUNT_SHIFT 37310d91611SNicholas Piggin == threads_per_core) 37410d91611SNicholas Piggin *state |= PNV_CORE_IDLE_THREAD_WINKLE_BITS; 37510d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 37610d91611SNicholas Piggin } 37710d91611SNicholas Piggin 37810d91611SNicholas Piggin atomic_unlock_thread_idle(); 37910d91611SNicholas Piggin } 38010d91611SNicholas Piggin 381e9cef018SMichael Ellerman if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 382e9cef018SMichael Ellerman sprs.amr = mfspr(SPRN_AMR); 383e9cef018SMichael Ellerman sprs.iamr = mfspr(SPRN_IAMR); 384e9cef018SMichael Ellerman sprs.amor = mfspr(SPRN_AMOR); 385e9cef018SMichael Ellerman sprs.uamor = mfspr(SPRN_UAMOR); 386e9cef018SMichael Ellerman } 387e9cef018SMichael Ellerman 38810d91611SNicholas Piggin local_paca->thread_idle_state = type; 38910d91611SNicholas Piggin srr1 = isa206_idle_insn_mayloss(type); /* go idle */ 39010d91611SNicholas Piggin local_paca->thread_idle_state = PNV_THREAD_RUNNING; 39110d91611SNicholas Piggin 39210d91611SNicholas Piggin WARN_ON_ONCE(!srr1); 39310d91611SNicholas Piggin WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 39410d91611SNicholas Piggin 395e9cef018SMichael Ellerman if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 396e9cef018SMichael Ellerman if ((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS) { 397e9cef018SMichael Ellerman /* 398e9cef018SMichael Ellerman * We don't need an isync after the mtsprs here because 399e9cef018SMichael Ellerman * the upcoming mtmsrd is execution synchronizing. 400e9cef018SMichael Ellerman */ 401e9cef018SMichael Ellerman mtspr(SPRN_AMR, sprs.amr); 402e9cef018SMichael Ellerman mtspr(SPRN_IAMR, sprs.iamr); 403e9cef018SMichael Ellerman mtspr(SPRN_AMOR, sprs.amor); 404e9cef018SMichael Ellerman mtspr(SPRN_UAMOR, sprs.uamor); 405e9cef018SMichael Ellerman } 406e9cef018SMichael Ellerman } 407e9cef018SMichael Ellerman 40810d91611SNicholas Piggin if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 40910d91611SNicholas Piggin hmi_exception_realmode(NULL); 41010d91611SNicholas Piggin 41110d91611SNicholas Piggin if (likely((srr1 & SRR1_WAKESTATE) != SRR1_WS_HVLOSS)) { 41210d91611SNicholas Piggin if (unlikely(type != PNV_THREAD_NAP)) { 41310d91611SNicholas Piggin atomic_lock_thread_idle(); 41410d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 41510d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 41610d91611SNicholas Piggin *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 41710d91611SNicholas Piggin *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); 41810d91611SNicholas Piggin } 41910d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 42010d91611SNicholas Piggin } 42110d91611SNicholas Piggin return srr1; 42210d91611SNicholas Piggin } 42310d91611SNicholas Piggin 42410d91611SNicholas Piggin /* HV state loss */ 42510d91611SNicholas Piggin BUG_ON(type == PNV_THREAD_NAP); 42610d91611SNicholas Piggin 42710d91611SNicholas Piggin atomic_lock_thread_idle(); 42810d91611SNicholas Piggin 42910d91611SNicholas Piggin full_winkle = false; 43010d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 43110d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 43210d91611SNicholas Piggin *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 43310d91611SNicholas Piggin if (*state & (thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT)) { 43410d91611SNicholas Piggin *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); 43510d91611SNicholas Piggin full_winkle = true; 43610d91611SNicholas Piggin BUG_ON(!sprs_saved); 43710d91611SNicholas Piggin } 43810d91611SNicholas Piggin } 43910d91611SNicholas Piggin 44010d91611SNicholas Piggin WARN_ON(*state & thread); 44110d91611SNicholas Piggin 44210d91611SNicholas Piggin if ((*state & core_thread_mask) != 0) 44310d91611SNicholas Piggin goto core_woken; 44410d91611SNicholas Piggin 44510d91611SNicholas Piggin /* Per-core SPRs */ 44610d91611SNicholas Piggin if (full_winkle) { 44710d91611SNicholas Piggin mtspr(SPRN_TSCR, sprs.tscr); 44810d91611SNicholas Piggin mtspr(SPRN_WORC, sprs.worc); 44910d91611SNicholas Piggin } 45010d91611SNicholas Piggin 45110d91611SNicholas Piggin if (power7_fastsleep_workaround_exit) { 45210d91611SNicholas Piggin rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 45310d91611SNicholas Piggin OPAL_CONFIG_IDLE_UNDO); 45410d91611SNicholas Piggin BUG_ON(rc); 45510d91611SNicholas Piggin } 45610d91611SNicholas Piggin 45710d91611SNicholas Piggin /* TB */ 45810d91611SNicholas Piggin if (opal_resync_timebase() != OPAL_SUCCESS) 45910d91611SNicholas Piggin BUG(); 46010d91611SNicholas Piggin 46110d91611SNicholas Piggin core_woken: 46210d91611SNicholas Piggin if (!full_winkle) 46310d91611SNicholas Piggin goto subcore_woken; 46410d91611SNicholas Piggin 46510d91611SNicholas Piggin if ((*state & local_paca->subcore_sibling_mask) != 0) 46610d91611SNicholas Piggin goto subcore_woken; 46710d91611SNicholas Piggin 46810d91611SNicholas Piggin /* Per-subcore SPRs */ 46910d91611SNicholas Piggin mtspr(SPRN_SDR1, sprs.sdr1); 47010d91611SNicholas Piggin mtspr(SPRN_RPR, sprs.rpr); 47110d91611SNicholas Piggin 47210d91611SNicholas Piggin subcore_woken: 47310d91611SNicholas Piggin /* 47410d91611SNicholas Piggin * isync after restoring shared SPRs and before unlocking. Unlock 47510d91611SNicholas Piggin * only contains hwsync which does not necessarily do the right 47610d91611SNicholas Piggin * thing for SPRs. 47710d91611SNicholas Piggin */ 47810d91611SNicholas Piggin isync(); 47910d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 48010d91611SNicholas Piggin 48110d91611SNicholas Piggin /* Fast sleep does not lose SPRs */ 48210d91611SNicholas Piggin if (!full_winkle) 48310d91611SNicholas Piggin return srr1; 48410d91611SNicholas Piggin 48510d91611SNicholas Piggin /* Per-thread SPRs */ 48610d91611SNicholas Piggin mtspr(SPRN_LPCR, sprs.lpcr); 48710d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 48810d91611SNicholas Piggin mtspr(SPRN_HFSCR, sprs.hfscr); 48910d91611SNicholas Piggin mtspr(SPRN_FSCR, sprs.fscr); 49010d91611SNicholas Piggin } 49110d91611SNicholas Piggin mtspr(SPRN_PURR, sprs.purr); 49210d91611SNicholas Piggin mtspr(SPRN_SPURR, sprs.spurr); 49310d91611SNicholas Piggin mtspr(SPRN_DSCR, sprs.dscr); 49410d91611SNicholas Piggin mtspr(SPRN_WORT, sprs.wort); 49510d91611SNicholas Piggin 49610d91611SNicholas Piggin mtspr(SPRN_SPRG3, local_paca->sprg_vdso); 49710d91611SNicholas Piggin 49810d91611SNicholas Piggin /* 49910d91611SNicholas Piggin * The SLB has to be restored here, but it sometimes still 50010d91611SNicholas Piggin * contains entries, so the __ variant must be used to prevent 50110d91611SNicholas Piggin * multi hits. 50210d91611SNicholas Piggin */ 50310d91611SNicholas Piggin __slb_restore_bolted_realmode(); 5042201f994SNicholas Piggin 5052201f994SNicholas Piggin return srr1; 5062201f994SNicholas Piggin } 5072201f994SNicholas Piggin 50810d91611SNicholas Piggin extern unsigned long idle_kvm_start_guest(unsigned long srr1); 50910d91611SNicholas Piggin 51010d91611SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 51110d91611SNicholas Piggin static unsigned long power7_offline(void) 51210d91611SNicholas Piggin { 51310d91611SNicholas Piggin unsigned long srr1; 51410d91611SNicholas Piggin 51510d91611SNicholas Piggin mtmsr(MSR_IDLE); 51610d91611SNicholas Piggin 51710d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 51810d91611SNicholas Piggin /* Tell KVM we're entering idle. */ 51910d91611SNicholas Piggin /******************************************************/ 52010d91611SNicholas Piggin /* N O T E W E L L ! ! ! N O T E W E L L */ 52110d91611SNicholas Piggin /* The following store to HSTATE_HWTHREAD_STATE(r13) */ 52210d91611SNicholas Piggin /* MUST occur in real mode, i.e. with the MMU off, */ 52310d91611SNicholas Piggin /* and the MMU must stay off until we clear this flag */ 52410d91611SNicholas Piggin /* and test HSTATE_HWTHREAD_REQ(r13) in */ 52510d91611SNicholas Piggin /* pnv_powersave_wakeup in this file. */ 52610d91611SNicholas Piggin /* The reason is that another thread can switch the */ 52710d91611SNicholas Piggin /* MMU to a guest context whenever this flag is set */ 52810d91611SNicholas Piggin /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ 52910d91611SNicholas Piggin /* that would potentially cause this thread to start */ 53010d91611SNicholas Piggin /* executing instructions from guest memory in */ 53110d91611SNicholas Piggin /* hypervisor mode, leading to a host crash or data */ 53210d91611SNicholas Piggin /* corruption, or worse. */ 53310d91611SNicholas Piggin /******************************************************/ 53410d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_IDLE; 53510d91611SNicholas Piggin #endif 53610d91611SNicholas Piggin 53710d91611SNicholas Piggin __ppc64_runlatch_off(); 53810d91611SNicholas Piggin srr1 = power7_idle_insn(power7_offline_type); 53910d91611SNicholas Piggin __ppc64_runlatch_on(); 54010d91611SNicholas Piggin 54110d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 54210d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_KERNEL; 54310d91611SNicholas Piggin /* Order setting hwthread_state vs. testing hwthread_req */ 54410d91611SNicholas Piggin smp_mb(); 54510d91611SNicholas Piggin if (local_paca->kvm_hstate.hwthread_req) 54610d91611SNicholas Piggin srr1 = idle_kvm_start_guest(srr1); 54710d91611SNicholas Piggin #endif 54810d91611SNicholas Piggin 54910d91611SNicholas Piggin mtmsr(MSR_KERNEL); 55010d91611SNicholas Piggin 55110d91611SNicholas Piggin return srr1; 55210d91611SNicholas Piggin } 55310d91611SNicholas Piggin #endif 55410d91611SNicholas Piggin 5552201f994SNicholas Piggin void power7_idle_type(unsigned long type) 5562201f994SNicholas Piggin { 557771d4304SNicholas Piggin unsigned long srr1; 558771d4304SNicholas Piggin 55910d91611SNicholas Piggin if (!prep_irq_for_idle_irqsoff()) 56010d91611SNicholas Piggin return; 56110d91611SNicholas Piggin 56210d91611SNicholas Piggin mtmsr(MSR_IDLE); 56310d91611SNicholas Piggin __ppc64_runlatch_off(); 56410d91611SNicholas Piggin srr1 = power7_idle_insn(type); 56510d91611SNicholas Piggin __ppc64_runlatch_on(); 56610d91611SNicholas Piggin mtmsr(MSR_KERNEL); 56710d91611SNicholas Piggin 56810d91611SNicholas Piggin fini_irq_for_idle_irqsoff(); 569771d4304SNicholas Piggin irq_set_pending_from_srr1(srr1); 5702201f994SNicholas Piggin } 5712201f994SNicholas Piggin 5722201f994SNicholas Piggin void power7_idle(void) 5732201f994SNicholas Piggin { 5742201f994SNicholas Piggin if (!powersave_nap) 5752201f994SNicholas Piggin return; 5762201f994SNicholas Piggin 5772201f994SNicholas Piggin power7_idle_type(PNV_THREAD_NAP); 5782201f994SNicholas Piggin } 5792201f994SNicholas Piggin 58010d91611SNicholas Piggin struct p9_sprs { 58110d91611SNicholas Piggin /* per core */ 58210d91611SNicholas Piggin u64 ptcr; 58310d91611SNicholas Piggin u64 rpr; 58410d91611SNicholas Piggin u64 tscr; 58510d91611SNicholas Piggin u64 ldbar; 58610d91611SNicholas Piggin 58710d91611SNicholas Piggin /* per thread */ 58810d91611SNicholas Piggin u64 lpcr; 58910d91611SNicholas Piggin u64 hfscr; 59010d91611SNicholas Piggin u64 fscr; 59110d91611SNicholas Piggin u64 pid; 59210d91611SNicholas Piggin u64 purr; 59310d91611SNicholas Piggin u64 spurr; 59410d91611SNicholas Piggin u64 dscr; 59510d91611SNicholas Piggin u64 wort; 59610d91611SNicholas Piggin 59710d91611SNicholas Piggin u64 mmcra; 59810d91611SNicholas Piggin u32 mmcr0; 59910d91611SNicholas Piggin u32 mmcr1; 60010d91611SNicholas Piggin u64 mmcr2; 601e9cef018SMichael Ellerman 602e9cef018SMichael Ellerman /* per thread SPRs that get lost in shallow states */ 603e9cef018SMichael Ellerman u64 amr; 604e9cef018SMichael Ellerman u64 iamr; 605e9cef018SMichael Ellerman u64 amor; 606e9cef018SMichael Ellerman u64 uamor; 60710d91611SNicholas Piggin }; 60810d91611SNicholas Piggin 60910d91611SNicholas Piggin static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on) 61010d91611SNicholas Piggin { 61110d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 61210d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 61310d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 61410d91611SNicholas Piggin unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 61510d91611SNicholas Piggin unsigned long srr1; 61610d91611SNicholas Piggin unsigned long pls; 61710d91611SNicholas Piggin unsigned long mmcr0 = 0; 61810d91611SNicholas Piggin struct p9_sprs sprs = {}; /* avoid false used-uninitialised */ 61910d91611SNicholas Piggin bool sprs_saved = false; 62010d91611SNicholas Piggin 62110d91611SNicholas Piggin if (!(psscr & (PSSCR_EC|PSSCR_ESL))) { 62210d91611SNicholas Piggin /* EC=ESL=0 case */ 62310d91611SNicholas Piggin 62410d91611SNicholas Piggin BUG_ON(!mmu_on); 62510d91611SNicholas Piggin 62610d91611SNicholas Piggin /* 62710d91611SNicholas Piggin * Wake synchronously. SRESET via xscom may still cause 62810d91611SNicholas Piggin * a 0x100 powersave wakeup with SRR1 reason! 62910d91611SNicholas Piggin */ 63010d91611SNicholas Piggin srr1 = isa300_idle_stop_noloss(psscr); /* go idle */ 63110d91611SNicholas Piggin if (likely(!srr1)) 63210d91611SNicholas Piggin return 0; 63310d91611SNicholas Piggin 63410d91611SNicholas Piggin /* 63510d91611SNicholas Piggin * Registers not saved, can't recover! 63610d91611SNicholas Piggin * This would be a hardware bug 63710d91611SNicholas Piggin */ 63810d91611SNicholas Piggin BUG_ON((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS); 63910d91611SNicholas Piggin 64010d91611SNicholas Piggin goto out; 64110d91611SNicholas Piggin } 64210d91611SNicholas Piggin 64310d91611SNicholas Piggin /* EC=ESL=1 case */ 64410d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 64510d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_P9_TM_XER_SO_BUG)) { 64610d91611SNicholas Piggin local_paca->requested_psscr = psscr; 64710d91611SNicholas Piggin /* order setting requested_psscr vs testing dont_stop */ 64810d91611SNicholas Piggin smp_mb(); 64910d91611SNicholas Piggin if (atomic_read(&local_paca->dont_stop)) { 65010d91611SNicholas Piggin local_paca->requested_psscr = 0; 65110d91611SNicholas Piggin return 0; 65210d91611SNicholas Piggin } 65310d91611SNicholas Piggin } 65410d91611SNicholas Piggin #endif 65510d91611SNicholas Piggin 65610d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { 65710d91611SNicholas Piggin /* 65810d91611SNicholas Piggin * POWER9 DD2 can incorrectly set PMAO when waking up 65910d91611SNicholas Piggin * after a state-loss idle. Saving and restoring MMCR0 66010d91611SNicholas Piggin * over idle is a workaround. 66110d91611SNicholas Piggin */ 66210d91611SNicholas Piggin mmcr0 = mfspr(SPRN_MMCR0); 66310d91611SNicholas Piggin } 66410d91611SNicholas Piggin if ((psscr & PSSCR_RL_MASK) >= pnv_first_spr_loss_level) { 66510d91611SNicholas Piggin sprs.lpcr = mfspr(SPRN_LPCR); 66610d91611SNicholas Piggin sprs.hfscr = mfspr(SPRN_HFSCR); 66710d91611SNicholas Piggin sprs.fscr = mfspr(SPRN_FSCR); 66810d91611SNicholas Piggin sprs.pid = mfspr(SPRN_PID); 66910d91611SNicholas Piggin sprs.purr = mfspr(SPRN_PURR); 67010d91611SNicholas Piggin sprs.spurr = mfspr(SPRN_SPURR); 67110d91611SNicholas Piggin sprs.dscr = mfspr(SPRN_DSCR); 67210d91611SNicholas Piggin sprs.wort = mfspr(SPRN_WORT); 67310d91611SNicholas Piggin 67410d91611SNicholas Piggin sprs.mmcra = mfspr(SPRN_MMCRA); 67510d91611SNicholas Piggin sprs.mmcr0 = mfspr(SPRN_MMCR0); 67610d91611SNicholas Piggin sprs.mmcr1 = mfspr(SPRN_MMCR1); 67710d91611SNicholas Piggin sprs.mmcr2 = mfspr(SPRN_MMCR2); 67810d91611SNicholas Piggin 67910d91611SNicholas Piggin sprs.ptcr = mfspr(SPRN_PTCR); 68010d91611SNicholas Piggin sprs.rpr = mfspr(SPRN_RPR); 68110d91611SNicholas Piggin sprs.tscr = mfspr(SPRN_TSCR); 68210d91611SNicholas Piggin sprs.ldbar = mfspr(SPRN_LDBAR); 68310d91611SNicholas Piggin 68410d91611SNicholas Piggin sprs_saved = true; 68510d91611SNicholas Piggin 68610d91611SNicholas Piggin atomic_start_thread_idle(); 68710d91611SNicholas Piggin } 68810d91611SNicholas Piggin 689e9cef018SMichael Ellerman sprs.amr = mfspr(SPRN_AMR); 690e9cef018SMichael Ellerman sprs.iamr = mfspr(SPRN_IAMR); 691e9cef018SMichael Ellerman sprs.amor = mfspr(SPRN_AMOR); 692e9cef018SMichael Ellerman sprs.uamor = mfspr(SPRN_UAMOR); 693e9cef018SMichael Ellerman 69410d91611SNicholas Piggin srr1 = isa300_idle_stop_mayloss(psscr); /* go idle */ 69510d91611SNicholas Piggin 69610d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 69710d91611SNicholas Piggin local_paca->requested_psscr = 0; 69810d91611SNicholas Piggin #endif 69910d91611SNicholas Piggin 70010d91611SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 70110d91611SNicholas Piggin 70210d91611SNicholas Piggin WARN_ON_ONCE(!srr1); 70310d91611SNicholas Piggin WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 70410d91611SNicholas Piggin 70510d91611SNicholas Piggin if ((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS) { 70610d91611SNicholas Piggin unsigned long mmcra; 70710d91611SNicholas Piggin 70810d91611SNicholas Piggin /* 709e9cef018SMichael Ellerman * We don't need an isync after the mtsprs here because the 710e9cef018SMichael Ellerman * upcoming mtmsrd is execution synchronizing. 711e9cef018SMichael Ellerman */ 712e9cef018SMichael Ellerman mtspr(SPRN_AMR, sprs.amr); 713e9cef018SMichael Ellerman mtspr(SPRN_IAMR, sprs.iamr); 714e9cef018SMichael Ellerman mtspr(SPRN_AMOR, sprs.amor); 715e9cef018SMichael Ellerman mtspr(SPRN_UAMOR, sprs.uamor); 716e9cef018SMichael Ellerman 717e9cef018SMichael Ellerman /* 71810d91611SNicholas Piggin * Workaround for POWER9 DD2.0, if we lost resources, the ERAT 71910d91611SNicholas Piggin * might have been corrupted and needs flushing. We also need 72010d91611SNicholas Piggin * to reload MMCR0 (see mmcr0 comment above). 72110d91611SNicholas Piggin */ 72210d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { 723fe7946ceSNicholas Piggin asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT); 72410d91611SNicholas Piggin mtspr(SPRN_MMCR0, mmcr0); 72510d91611SNicholas Piggin } 72610d91611SNicholas Piggin 72710d91611SNicholas Piggin /* 72810d91611SNicholas Piggin * DD2.2 and earlier need to set then clear bit 60 in MMCRA 72910d91611SNicholas Piggin * to ensure the PMU starts running. 73010d91611SNicholas Piggin */ 73110d91611SNicholas Piggin mmcra = mfspr(SPRN_MMCRA); 73210d91611SNicholas Piggin mmcra |= PPC_BIT(60); 73310d91611SNicholas Piggin mtspr(SPRN_MMCRA, mmcra); 73410d91611SNicholas Piggin mmcra &= ~PPC_BIT(60); 73510d91611SNicholas Piggin mtspr(SPRN_MMCRA, mmcra); 73610d91611SNicholas Piggin } 73710d91611SNicholas Piggin 73810d91611SNicholas Piggin if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 73910d91611SNicholas Piggin hmi_exception_realmode(NULL); 74010d91611SNicholas Piggin 74110d91611SNicholas Piggin /* 74210d91611SNicholas Piggin * On POWER9, SRR1 bits do not match exactly as expected. 74310d91611SNicholas Piggin * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so 74410d91611SNicholas Piggin * just always test PSSCR for SPR/TB state loss. 74510d91611SNicholas Piggin */ 74610d91611SNicholas Piggin pls = (psscr & PSSCR_PLS) >> PSSCR_PLS_SHIFT; 74710d91611SNicholas Piggin if (likely(pls < pnv_first_spr_loss_level)) { 74810d91611SNicholas Piggin if (sprs_saved) 74910d91611SNicholas Piggin atomic_stop_thread_idle(); 75010d91611SNicholas Piggin goto out; 75110d91611SNicholas Piggin } 75210d91611SNicholas Piggin 75310d91611SNicholas Piggin /* HV state loss */ 75410d91611SNicholas Piggin BUG_ON(!sprs_saved); 75510d91611SNicholas Piggin 75610d91611SNicholas Piggin atomic_lock_thread_idle(); 75710d91611SNicholas Piggin 75810d91611SNicholas Piggin if ((*state & core_thread_mask) != 0) 75910d91611SNicholas Piggin goto core_woken; 76010d91611SNicholas Piggin 76110d91611SNicholas Piggin /* Per-core SPRs */ 76210d91611SNicholas Piggin mtspr(SPRN_PTCR, sprs.ptcr); 76310d91611SNicholas Piggin mtspr(SPRN_RPR, sprs.rpr); 76410d91611SNicholas Piggin mtspr(SPRN_TSCR, sprs.tscr); 76510d91611SNicholas Piggin mtspr(SPRN_LDBAR, sprs.ldbar); 76610d91611SNicholas Piggin 76710d91611SNicholas Piggin if (pls >= pnv_first_tb_loss_level) { 76810d91611SNicholas Piggin /* TB loss */ 76910d91611SNicholas Piggin if (opal_resync_timebase() != OPAL_SUCCESS) 77010d91611SNicholas Piggin BUG(); 77110d91611SNicholas Piggin } 77210d91611SNicholas Piggin 77310d91611SNicholas Piggin /* 77410d91611SNicholas Piggin * isync after restoring shared SPRs and before unlocking. Unlock 77510d91611SNicholas Piggin * only contains hwsync which does not necessarily do the right 77610d91611SNicholas Piggin * thing for SPRs. 77710d91611SNicholas Piggin */ 77810d91611SNicholas Piggin isync(); 77910d91611SNicholas Piggin 78010d91611SNicholas Piggin core_woken: 78110d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 78210d91611SNicholas Piggin 78310d91611SNicholas Piggin /* Per-thread SPRs */ 78410d91611SNicholas Piggin mtspr(SPRN_LPCR, sprs.lpcr); 78510d91611SNicholas Piggin mtspr(SPRN_HFSCR, sprs.hfscr); 78610d91611SNicholas Piggin mtspr(SPRN_FSCR, sprs.fscr); 78710d91611SNicholas Piggin mtspr(SPRN_PID, sprs.pid); 78810d91611SNicholas Piggin mtspr(SPRN_PURR, sprs.purr); 78910d91611SNicholas Piggin mtspr(SPRN_SPURR, sprs.spurr); 79010d91611SNicholas Piggin mtspr(SPRN_DSCR, sprs.dscr); 79110d91611SNicholas Piggin mtspr(SPRN_WORT, sprs.wort); 79210d91611SNicholas Piggin 79310d91611SNicholas Piggin mtspr(SPRN_MMCRA, sprs.mmcra); 79410d91611SNicholas Piggin mtspr(SPRN_MMCR0, sprs.mmcr0); 79510d91611SNicholas Piggin mtspr(SPRN_MMCR1, sprs.mmcr1); 79610d91611SNicholas Piggin mtspr(SPRN_MMCR2, sprs.mmcr2); 79710d91611SNicholas Piggin 79810d91611SNicholas Piggin mtspr(SPRN_SPRG3, local_paca->sprg_vdso); 79910d91611SNicholas Piggin 80010d91611SNicholas Piggin if (!radix_enabled()) 80110d91611SNicholas Piggin __slb_restore_bolted_realmode(); 80210d91611SNicholas Piggin 80310d91611SNicholas Piggin out: 80410d91611SNicholas Piggin if (mmu_on) 80510d91611SNicholas Piggin mtmsr(MSR_KERNEL); 80610d91611SNicholas Piggin 80710d91611SNicholas Piggin return srr1; 80810d91611SNicholas Piggin } 80910d91611SNicholas Piggin 81010d91611SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 81110d91611SNicholas Piggin static unsigned long power9_offline_stop(unsigned long psscr) 81210d91611SNicholas Piggin { 81310d91611SNicholas Piggin unsigned long srr1; 81410d91611SNicholas Piggin 81510d91611SNicholas Piggin #ifndef CONFIG_KVM_BOOK3S_HV_POSSIBLE 81610d91611SNicholas Piggin __ppc64_runlatch_off(); 81710d91611SNicholas Piggin srr1 = power9_idle_stop(psscr, true); 81810d91611SNicholas Piggin __ppc64_runlatch_on(); 81910d91611SNicholas Piggin #else 82010d91611SNicholas Piggin /* 82110d91611SNicholas Piggin * Tell KVM we're entering idle. 82210d91611SNicholas Piggin * This does not have to be done in real mode because the P9 MMU 82310d91611SNicholas Piggin * is independent per-thread. Some steppings share radix/hash mode 82410d91611SNicholas Piggin * between threads, but in that case KVM has a barrier sync in real 82510d91611SNicholas Piggin * mode before and after switching between radix and hash. 82610d91611SNicholas Piggin * 82710d91611SNicholas Piggin * kvm_start_guest must still be called in real mode though, hence 82810d91611SNicholas Piggin * the false argument. 82910d91611SNicholas Piggin */ 83010d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_IDLE; 83110d91611SNicholas Piggin 83210d91611SNicholas Piggin __ppc64_runlatch_off(); 83310d91611SNicholas Piggin srr1 = power9_idle_stop(psscr, false); 83410d91611SNicholas Piggin __ppc64_runlatch_on(); 83510d91611SNicholas Piggin 83610d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_KERNEL; 83710d91611SNicholas Piggin /* Order setting hwthread_state vs. testing hwthread_req */ 83810d91611SNicholas Piggin smp_mb(); 83910d91611SNicholas Piggin if (local_paca->kvm_hstate.hwthread_req) 84010d91611SNicholas Piggin srr1 = idle_kvm_start_guest(srr1); 84110d91611SNicholas Piggin mtmsr(MSR_KERNEL); 84210d91611SNicholas Piggin #endif 84310d91611SNicholas Piggin 84410d91611SNicholas Piggin return srr1; 84510d91611SNicholas Piggin } 84610d91611SNicholas Piggin #endif 84710d91611SNicholas Piggin 84810d91611SNicholas Piggin void power9_idle_type(unsigned long stop_psscr_val, 8492201f994SNicholas Piggin unsigned long stop_psscr_mask) 8502201f994SNicholas Piggin { 8512201f994SNicholas Piggin unsigned long psscr; 8522201f994SNicholas Piggin unsigned long srr1; 8532201f994SNicholas Piggin 8542201f994SNicholas Piggin if (!prep_irq_for_idle_irqsoff()) 85510d91611SNicholas Piggin return; 8562201f994SNicholas Piggin 8572201f994SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 8582201f994SNicholas Piggin psscr = (psscr & ~stop_psscr_mask) | stop_psscr_val; 8592201f994SNicholas Piggin 86040d24343SNicholas Piggin __ppc64_runlatch_off(); 86110d91611SNicholas Piggin srr1 = power9_idle_stop(psscr, true); 86240d24343SNicholas Piggin __ppc64_runlatch_on(); 8632201f994SNicholas Piggin 8642201f994SNicholas Piggin fini_irq_for_idle_irqsoff(); 8652201f994SNicholas Piggin 866771d4304SNicholas Piggin irq_set_pending_from_srr1(srr1); 8672201f994SNicholas Piggin } 8682201f994SNicholas Piggin 86909206b60SGautham R. Shenoy /* 870bcef83a0SShreyas B. Prabhu * Used for ppc_md.power_save which needs a function with no parameters 871bcef83a0SShreyas B. Prabhu */ 8722201f994SNicholas Piggin void power9_idle(void) 873d405a98cSShreyas B. Prabhu { 8742201f994SNicholas Piggin power9_idle_type(pnv_default_stop_val, pnv_default_stop_mask); 875bcef83a0SShreyas B. Prabhu } 87609206b60SGautham R. Shenoy 8777672691aSPaul Mackerras #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 8787672691aSPaul Mackerras /* 8797672691aSPaul Mackerras * This is used in working around bugs in thread reconfiguration 8807672691aSPaul Mackerras * on POWER9 (at least up to Nimbus DD2.2) relating to transactional 8817672691aSPaul Mackerras * memory and the way that XER[SO] is checkpointed. 8827672691aSPaul Mackerras * This function forces the core into SMT4 in order by asking 8837672691aSPaul Mackerras * all other threads not to stop, and sending a message to any 8847672691aSPaul Mackerras * that are in a stop state. 8857672691aSPaul Mackerras * Must be called with preemption disabled. 8867672691aSPaul Mackerras */ 8877672691aSPaul Mackerras void pnv_power9_force_smt4_catch(void) 8887672691aSPaul Mackerras { 8897672691aSPaul Mackerras int cpu, cpu0, thr; 8907672691aSPaul Mackerras int awake_threads = 1; /* this thread is awake */ 8917672691aSPaul Mackerras int poke_threads = 0; 8927672691aSPaul Mackerras int need_awake = threads_per_core; 8937672691aSPaul Mackerras 8947672691aSPaul Mackerras cpu = smp_processor_id(); 8957672691aSPaul Mackerras cpu0 = cpu & ~(threads_per_core - 1); 8967672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 8977672691aSPaul Mackerras if (cpu != cpu0 + thr) 898f437c517SMichael Ellerman atomic_inc(&paca_ptrs[cpu0+thr]->dont_stop); 8997672691aSPaul Mackerras } 9007672691aSPaul Mackerras /* order setting dont_stop vs testing requested_psscr */ 90110d91611SNicholas Piggin smp_mb(); 9027672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 903f437c517SMichael Ellerman if (!paca_ptrs[cpu0+thr]->requested_psscr) 9047672691aSPaul Mackerras ++awake_threads; 9057672691aSPaul Mackerras else 9067672691aSPaul Mackerras poke_threads |= (1 << thr); 9077672691aSPaul Mackerras } 9087672691aSPaul Mackerras 9097672691aSPaul Mackerras /* If at least 3 threads are awake, the core is in SMT4 already */ 9107672691aSPaul Mackerras if (awake_threads < need_awake) { 9117672691aSPaul Mackerras /* We have to wake some threads; we'll use msgsnd */ 9127672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 9137672691aSPaul Mackerras if (poke_threads & (1 << thr)) { 9147672691aSPaul Mackerras ppc_msgsnd_sync(); 9157672691aSPaul Mackerras ppc_msgsnd(PPC_DBELL_MSGTYPE, 0, 916f437c517SMichael Ellerman paca_ptrs[cpu0+thr]->hw_cpu_id); 9177672691aSPaul Mackerras } 9187672691aSPaul Mackerras } 9197672691aSPaul Mackerras /* now spin until at least 3 threads are awake */ 9207672691aSPaul Mackerras do { 9217672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 9227672691aSPaul Mackerras if ((poke_threads & (1 << thr)) && 923f437c517SMichael Ellerman !paca_ptrs[cpu0+thr]->requested_psscr) { 9247672691aSPaul Mackerras ++awake_threads; 9257672691aSPaul Mackerras poke_threads &= ~(1 << thr); 9267672691aSPaul Mackerras } 9277672691aSPaul Mackerras } 9287672691aSPaul Mackerras } while (awake_threads < need_awake); 9297672691aSPaul Mackerras } 9307672691aSPaul Mackerras } 9317672691aSPaul Mackerras EXPORT_SYMBOL_GPL(pnv_power9_force_smt4_catch); 9327672691aSPaul Mackerras 9337672691aSPaul Mackerras void pnv_power9_force_smt4_release(void) 9347672691aSPaul Mackerras { 9357672691aSPaul Mackerras int cpu, cpu0, thr; 9367672691aSPaul Mackerras 9377672691aSPaul Mackerras cpu = smp_processor_id(); 9387672691aSPaul Mackerras cpu0 = cpu & ~(threads_per_core - 1); 9397672691aSPaul Mackerras 9407672691aSPaul Mackerras /* clear all the dont_stop flags */ 9417672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 9427672691aSPaul Mackerras if (cpu != cpu0 + thr) 943f437c517SMichael Ellerman atomic_dec(&paca_ptrs[cpu0+thr]->dont_stop); 9447672691aSPaul Mackerras } 9457672691aSPaul Mackerras } 9467672691aSPaul Mackerras EXPORT_SYMBOL_GPL(pnv_power9_force_smt4_release); 9477672691aSPaul Mackerras #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 9487672691aSPaul Mackerras 94967d20418SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 95019f8a5b5SPaul Mackerras 95119f8a5b5SPaul Mackerras void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val) 95224be85a2SGautham R. Shenoy { 95324be85a2SGautham R. Shenoy u64 pir = get_hard_smp_processor_id(cpu); 95424be85a2SGautham R. Shenoy 95524be85a2SGautham R. Shenoy mtspr(SPRN_LPCR, lpcr_val); 9565d298baaSGautham R. Shenoy 9575d298baaSGautham R. Shenoy /* 9585d298baaSGautham R. Shenoy * Program the LPCR via stop-api only if the deepest stop state 9595d298baaSGautham R. Shenoy * can lose hypervisor context. 9605d298baaSGautham R. Shenoy */ 9615d298baaSGautham R. Shenoy if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) 96224be85a2SGautham R. Shenoy opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 96324be85a2SGautham R. Shenoy } 96424be85a2SGautham R. Shenoy 965c0691f9dSShreyas B. Prabhu /* 966a7cd88daSGautham R. Shenoy * pnv_cpu_offline: A function that puts the CPU into the deepest 967a7cd88daSGautham R. Shenoy * available platform idle state on a CPU-Offline. 9682525db04SNicholas Piggin * interrupts hard disabled and no lazy irq pending. 969a7cd88daSGautham R. Shenoy */ 970a7cd88daSGautham R. Shenoy unsigned long pnv_cpu_offline(unsigned int cpu) 971a7cd88daSGautham R. Shenoy { 972a7cd88daSGautham R. Shenoy unsigned long srr1; 973a7cd88daSGautham R. Shenoy 97440d24343SNicholas Piggin __ppc64_runlatch_off(); 9752525db04SNicholas Piggin 976f3b3f284SGautham R. Shenoy if (cpu_has_feature(CPU_FTR_ARCH_300) && deepest_stop_found) { 9772525db04SNicholas Piggin unsigned long psscr; 9782525db04SNicholas Piggin 9792525db04SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 9802525db04SNicholas Piggin psscr = (psscr & ~pnv_deepest_stop_psscr_mask) | 9812525db04SNicholas Piggin pnv_deepest_stop_psscr_val; 9823d4fbffdSNicholas Piggin srr1 = power9_offline_stop(psscr); 98310d91611SNicholas Piggin } else if (cpu_has_feature(CPU_FTR_ARCH_206) && power7_offline_type) { 98410d91611SNicholas Piggin srr1 = power7_offline(); 98590061231SGautham R. Shenoy } else { 98690061231SGautham R. Shenoy /* This is the fallback method. We emulate snooze */ 98790061231SGautham R. Shenoy while (!generic_check_cpu_restart(cpu)) { 98890061231SGautham R. Shenoy HMT_low(); 98990061231SGautham R. Shenoy HMT_very_low(); 99090061231SGautham R. Shenoy } 99190061231SGautham R. Shenoy srr1 = 0; 99290061231SGautham R. Shenoy HMT_medium(); 993a7cd88daSGautham R. Shenoy } 994a7cd88daSGautham R. Shenoy 99540d24343SNicholas Piggin __ppc64_runlatch_on(); 9962525db04SNicholas Piggin 997a7cd88daSGautham R. Shenoy return srr1; 998a7cd88daSGautham R. Shenoy } 99967d20418SNicholas Piggin #endif 1000a7cd88daSGautham R. Shenoy 1001a7cd88daSGautham R. Shenoy /* 1002bcef83a0SShreyas B. Prabhu * Power ISA 3.0 idle initialization. 1003bcef83a0SShreyas B. Prabhu * 1004bcef83a0SShreyas B. Prabhu * POWER ISA 3.0 defines a new SPR Processor stop Status and Control 1005bcef83a0SShreyas B. Prabhu * Register (PSSCR) to control idle behavior. 1006bcef83a0SShreyas B. Prabhu * 1007bcef83a0SShreyas B. Prabhu * PSSCR layout: 1008bcef83a0SShreyas B. Prabhu * ---------------------------------------------------------- 1009bcef83a0SShreyas B. Prabhu * | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | 1010bcef83a0SShreyas B. Prabhu * ---------------------------------------------------------- 1011bcef83a0SShreyas B. Prabhu * 0 4 41 42 43 44 48 54 56 60 1012bcef83a0SShreyas B. Prabhu * 1013bcef83a0SShreyas B. Prabhu * PSSCR key fields: 1014bcef83a0SShreyas B. Prabhu * Bits 0:3 - Power-Saving Level Status (PLS). This field indicates the 1015bcef83a0SShreyas B. Prabhu * lowest power-saving state the thread entered since stop instruction was 1016bcef83a0SShreyas B. Prabhu * last executed. 1017bcef83a0SShreyas B. Prabhu * 1018bcef83a0SShreyas B. Prabhu * Bit 41 - Status Disable(SD) 1019bcef83a0SShreyas B. Prabhu * 0 - Shows PLS entries 1020bcef83a0SShreyas B. Prabhu * 1 - PLS entries are all 0 1021bcef83a0SShreyas B. Prabhu * 1022bcef83a0SShreyas B. Prabhu * Bit 42 - Enable State Loss 1023bcef83a0SShreyas B. Prabhu * 0 - No state is lost irrespective of other fields 1024bcef83a0SShreyas B. Prabhu * 1 - Allows state loss 1025bcef83a0SShreyas B. Prabhu * 1026bcef83a0SShreyas B. Prabhu * Bit 43 - Exit Criterion 1027bcef83a0SShreyas B. Prabhu * 0 - Exit from power-save mode on any interrupt 1028bcef83a0SShreyas B. Prabhu * 1 - Exit from power-save mode controlled by LPCR's PECE bits 1029bcef83a0SShreyas B. Prabhu * 1030bcef83a0SShreyas B. Prabhu * Bits 44:47 - Power-Saving Level Limit 1031bcef83a0SShreyas B. Prabhu * This limits the power-saving level that can be entered into. 1032bcef83a0SShreyas B. Prabhu * 1033bcef83a0SShreyas B. Prabhu * Bits 60:63 - Requested Level 1034bcef83a0SShreyas B. Prabhu * Used to specify which power-saving level must be entered on executing 1035bcef83a0SShreyas B. Prabhu * stop instruction 103609206b60SGautham R. Shenoy */ 103709206b60SGautham R. Shenoy 103809206b60SGautham R. Shenoy int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags) 103909206b60SGautham R. Shenoy { 104009206b60SGautham R. Shenoy int err = 0; 104109206b60SGautham R. Shenoy 104209206b60SGautham R. Shenoy /* 104309206b60SGautham R. Shenoy * psscr_mask == 0xf indicates an older firmware. 104409206b60SGautham R. Shenoy * Set remaining fields of psscr to the default values. 104509206b60SGautham R. Shenoy * See NOTE above definition of PSSCR_HV_DEFAULT_VAL 104609206b60SGautham R. Shenoy */ 104709206b60SGautham R. Shenoy if (*psscr_mask == 0xf) { 104809206b60SGautham R. Shenoy *psscr_val = *psscr_val | PSSCR_HV_DEFAULT_VAL; 104909206b60SGautham R. Shenoy *psscr_mask = PSSCR_HV_DEFAULT_MASK; 105009206b60SGautham R. Shenoy return err; 105109206b60SGautham R. Shenoy } 105209206b60SGautham R. Shenoy 105309206b60SGautham R. Shenoy /* 105409206b60SGautham R. Shenoy * New firmware is expected to set the psscr_val bits correctly. 105509206b60SGautham R. Shenoy * Validate that the following invariants are correctly maintained by 105609206b60SGautham R. Shenoy * the new firmware. 105709206b60SGautham R. Shenoy * - ESL bit value matches the EC bit value. 105809206b60SGautham R. Shenoy * - ESL bit is set for all the deep stop states. 105909206b60SGautham R. Shenoy */ 106009206b60SGautham R. Shenoy if (GET_PSSCR_ESL(*psscr_val) != GET_PSSCR_EC(*psscr_val)) { 106109206b60SGautham R. Shenoy err = ERR_EC_ESL_MISMATCH; 106209206b60SGautham R. Shenoy } else if ((flags & OPAL_PM_LOSE_FULL_CONTEXT) && 106309206b60SGautham R. Shenoy GET_PSSCR_ESL(*psscr_val) == 0) { 106409206b60SGautham R. Shenoy err = ERR_DEEP_STATE_ESL_MISMATCH; 106509206b60SGautham R. Shenoy } 106609206b60SGautham R. Shenoy 106709206b60SGautham R. Shenoy return err; 106809206b60SGautham R. Shenoy } 106909206b60SGautham R. Shenoy 107009206b60SGautham R. Shenoy /* 107109206b60SGautham R. Shenoy * pnv_arch300_idle_init: Initializes the default idle state, first 107209206b60SGautham R. Shenoy * deep idle state and deepest idle state on 107309206b60SGautham R. Shenoy * ISA 3.0 CPUs. 1074bcef83a0SShreyas B. Prabhu * 1075bcef83a0SShreyas B. Prabhu * @np: /ibm,opal/power-mgt device node 1076bcef83a0SShreyas B. Prabhu * @flags: cpu-idle-state-flags array 1077bcef83a0SShreyas B. Prabhu * @dt_idle_states: Number of idle state entries 1078bcef83a0SShreyas B. Prabhu * Returns 0 on success 1079bcef83a0SShreyas B. Prabhu */ 108010d91611SNicholas Piggin static void __init pnv_power9_idle_init(void) 1081bcef83a0SShreyas B. Prabhu { 108209206b60SGautham R. Shenoy u64 max_residency_ns = 0; 10839c7b185aSAkshay Adiga int i; 1084bcef83a0SShreyas B. Prabhu 1085bcef83a0SShreyas B. Prabhu /* 108609206b60SGautham R. Shenoy * pnv_deepest_stop_{val,mask} should be set to values corresponding to 108709206b60SGautham R. Shenoy * the deepest stop state. 108809206b60SGautham R. Shenoy * 108909206b60SGautham R. Shenoy * pnv_default_stop_{val,mask} should be set to values corresponding to 109010d91611SNicholas Piggin * the deepest loss-less (OPAL_PM_STOP_INST_FAST) stop state. 1091bcef83a0SShreyas B. Prabhu */ 109210d91611SNicholas Piggin pnv_first_tb_loss_level = MAX_STOP_STATE + 1; 109310d91611SNicholas Piggin pnv_first_spr_loss_level = MAX_STOP_STATE + 1; 10949c7b185aSAkshay Adiga for (i = 0; i < nr_pnv_idle_states; i++) { 109509206b60SGautham R. Shenoy int err; 10969c7b185aSAkshay Adiga struct pnv_idle_states_t *state = &pnv_idle_states[i]; 10979c7b185aSAkshay Adiga u64 psscr_rl = state->psscr_val & PSSCR_RL_MASK; 1098bcef83a0SShreyas B. Prabhu 109910d91611SNicholas Piggin if ((state->flags & OPAL_PM_TIMEBASE_STOP) && 110010d91611SNicholas Piggin (pnv_first_tb_loss_level > psscr_rl)) 110110d91611SNicholas Piggin pnv_first_tb_loss_level = psscr_rl; 110210d91611SNicholas Piggin 11039c7b185aSAkshay Adiga if ((state->flags & OPAL_PM_LOSE_FULL_CONTEXT) && 110410d91611SNicholas Piggin (pnv_first_spr_loss_level > psscr_rl)) 110510d91611SNicholas Piggin pnv_first_spr_loss_level = psscr_rl; 110610d91611SNicholas Piggin 110710d91611SNicholas Piggin /* 110810d91611SNicholas Piggin * The idle code does not deal with TB loss occurring 110910d91611SNicholas Piggin * in a shallower state than SPR loss, so force it to 111010d91611SNicholas Piggin * behave like SPRs are lost if TB is lost. POWER9 would 111110d91611SNicholas Piggin * never encouter this, but a POWER8 core would if it 111210d91611SNicholas Piggin * implemented the stop instruction. So this is for forward 111310d91611SNicholas Piggin * compatibility. 111410d91611SNicholas Piggin */ 111510d91611SNicholas Piggin if ((state->flags & OPAL_PM_TIMEBASE_STOP) && 111610d91611SNicholas Piggin (pnv_first_spr_loss_level > psscr_rl)) 111710d91611SNicholas Piggin pnv_first_spr_loss_level = psscr_rl; 1118c0691f9dSShreyas B. Prabhu 11199c7b185aSAkshay Adiga err = validate_psscr_val_mask(&state->psscr_val, 11209c7b185aSAkshay Adiga &state->psscr_mask, 11219c7b185aSAkshay Adiga state->flags); 112209206b60SGautham R. Shenoy if (err) { 11239c7b185aSAkshay Adiga report_invalid_psscr_val(state->psscr_val, err); 112409206b60SGautham R. Shenoy continue; 112509206b60SGautham R. Shenoy } 112609206b60SGautham R. Shenoy 11273127692dSNicholas Piggin state->valid = true; 11283127692dSNicholas Piggin 11299c7b185aSAkshay Adiga if (max_residency_ns < state->residency_ns) { 11309c7b185aSAkshay Adiga max_residency_ns = state->residency_ns; 11319c7b185aSAkshay Adiga pnv_deepest_stop_psscr_val = state->psscr_val; 11329c7b185aSAkshay Adiga pnv_deepest_stop_psscr_mask = state->psscr_mask; 11339c7b185aSAkshay Adiga pnv_deepest_stop_flag = state->flags; 113409206b60SGautham R. Shenoy deepest_stop_found = true; 113509206b60SGautham R. Shenoy } 113609206b60SGautham R. Shenoy 113709206b60SGautham R. Shenoy if (!default_stop_found && 11389c7b185aSAkshay Adiga (state->flags & OPAL_PM_STOP_INST_FAST)) { 11399c7b185aSAkshay Adiga pnv_default_stop_val = state->psscr_val; 11409c7b185aSAkshay Adiga pnv_default_stop_mask = state->psscr_mask; 114109206b60SGautham R. Shenoy default_stop_found = true; 114210d91611SNicholas Piggin WARN_ON(state->flags & OPAL_PM_LOSE_FULL_CONTEXT); 114309206b60SGautham R. Shenoy } 114409206b60SGautham R. Shenoy } 114509206b60SGautham R. Shenoy 1146f3b3f284SGautham R. Shenoy if (unlikely(!default_stop_found)) { 1147f3b3f284SGautham R. Shenoy pr_warn("cpuidle-powernv: No suitable default stop state found. Disabling platform idle.\n"); 1148f3b3f284SGautham R. Shenoy } else { 1149f3b3f284SGautham R. Shenoy ppc_md.power_save = power9_idle; 1150f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Default stop: psscr = 0x%016llx,mask=0x%016llx\n", 115109206b60SGautham R. Shenoy pnv_default_stop_val, pnv_default_stop_mask); 115209206b60SGautham R. Shenoy } 115309206b60SGautham R. Shenoy 1154f3b3f284SGautham R. Shenoy if (unlikely(!deepest_stop_found)) { 1155f3b3f284SGautham R. Shenoy pr_warn("cpuidle-powernv: No suitable stop state for CPU-Hotplug. Offlined CPUs will busy wait"); 1156f3b3f284SGautham R. Shenoy } else { 1157f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Deepest stop: psscr = 0x%016llx,mask=0x%016llx\n", 115809206b60SGautham R. Shenoy pnv_deepest_stop_psscr_val, 115909206b60SGautham R. Shenoy pnv_deepest_stop_psscr_mask); 1160bcef83a0SShreyas B. Prabhu } 1161bcef83a0SShreyas B. Prabhu 116287997471SShaokun Zhang pr_info("cpuidle-powernv: First stop level that may lose SPRs = 0x%llx\n", 116310d91611SNicholas Piggin pnv_first_spr_loss_level); 11649c7b185aSAkshay Adiga 116587997471SShaokun Zhang pr_info("cpuidle-powernv: First stop level that may lose timebase = 0x%llx\n", 116610d91611SNicholas Piggin pnv_first_tb_loss_level); 116710d91611SNicholas Piggin } 116810d91611SNicholas Piggin 116910d91611SNicholas Piggin static void __init pnv_disable_deep_states(void) 117010d91611SNicholas Piggin { 117110d91611SNicholas Piggin /* 117210d91611SNicholas Piggin * The stop-api is unable to restore hypervisor 117310d91611SNicholas Piggin * resources on wakeup from platform idle states which 117410d91611SNicholas Piggin * lose full context. So disable such states. 117510d91611SNicholas Piggin */ 117610d91611SNicholas Piggin supported_cpuidle_states &= ~OPAL_PM_LOSE_FULL_CONTEXT; 117710d91611SNicholas Piggin pr_warn("cpuidle-powernv: Disabling idle states that lose full context\n"); 117810d91611SNicholas Piggin pr_warn("cpuidle-powernv: Idle power-savings, CPU-Hotplug affected\n"); 117910d91611SNicholas Piggin 118010d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_300) && 118110d91611SNicholas Piggin (pnv_deepest_stop_flag & OPAL_PM_LOSE_FULL_CONTEXT)) { 118210d91611SNicholas Piggin /* 118310d91611SNicholas Piggin * Use the default stop state for CPU-Hotplug 118410d91611SNicholas Piggin * if available. 118510d91611SNicholas Piggin */ 118610d91611SNicholas Piggin if (default_stop_found) { 118710d91611SNicholas Piggin pnv_deepest_stop_psscr_val = pnv_default_stop_val; 118810d91611SNicholas Piggin pnv_deepest_stop_psscr_mask = pnv_default_stop_mask; 118910d91611SNicholas Piggin pr_warn("cpuidle-powernv: Offlined CPUs will stop with psscr = 0x%016llx\n", 119010d91611SNicholas Piggin pnv_deepest_stop_psscr_val); 119110d91611SNicholas Piggin } else { /* Fallback to snooze loop for CPU-Hotplug */ 119210d91611SNicholas Piggin deepest_stop_found = false; 119310d91611SNicholas Piggin pr_warn("cpuidle-powernv: Offlined CPUs will busy wait\n"); 119410d91611SNicholas Piggin } 119510d91611SNicholas Piggin } 1196bcef83a0SShreyas B. Prabhu } 1197bcef83a0SShreyas B. Prabhu 1198bcef83a0SShreyas B. Prabhu /* 1199bcef83a0SShreyas B. Prabhu * Probe device tree for supported idle states 1200bcef83a0SShreyas B. Prabhu */ 1201bcef83a0SShreyas B. Prabhu static void __init pnv_probe_idle_states(void) 1202bcef83a0SShreyas B. Prabhu { 1203d405a98cSShreyas B. Prabhu int i; 1204d405a98cSShreyas B. Prabhu 12059c7b185aSAkshay Adiga if (nr_pnv_idle_states < 0) { 12069c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: no idle states found in the DT\n"); 12079c7b185aSAkshay Adiga return; 12089c7b185aSAkshay Adiga } 12099c7b185aSAkshay Adiga 121010d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_300)) 121110d91611SNicholas Piggin pnv_power9_idle_init(); 12129c7b185aSAkshay Adiga 12139c7b185aSAkshay Adiga for (i = 0; i < nr_pnv_idle_states; i++) 12149c7b185aSAkshay Adiga supported_cpuidle_states |= pnv_idle_states[i].flags; 12159c7b185aSAkshay Adiga } 12169c7b185aSAkshay Adiga 12179c7b185aSAkshay Adiga /* 12189c7b185aSAkshay Adiga * This function parses device-tree and populates all the information 12199c7b185aSAkshay Adiga * into pnv_idle_states structure. It also sets up nr_pnv_idle_states 12209c7b185aSAkshay Adiga * which is the number of cpuidle states discovered through device-tree. 12219c7b185aSAkshay Adiga */ 12229c7b185aSAkshay Adiga 12239c7b185aSAkshay Adiga static int pnv_parse_cpuidle_dt(void) 12249c7b185aSAkshay Adiga { 12259c7b185aSAkshay Adiga struct device_node *np; 12269c7b185aSAkshay Adiga int nr_idle_states, i; 12279c7b185aSAkshay Adiga int rc = 0; 12289c7b185aSAkshay Adiga u32 *temp_u32; 12299c7b185aSAkshay Adiga u64 *temp_u64; 12309c7b185aSAkshay Adiga const char **temp_string; 12319c7b185aSAkshay Adiga 1232bcef83a0SShreyas B. Prabhu np = of_find_node_by_path("/ibm,opal/power-mgt"); 1233bcef83a0SShreyas B. Prabhu if (!np) { 1234d405a98cSShreyas B. Prabhu pr_warn("opal: PowerMgmt Node not found\n"); 12359c7b185aSAkshay Adiga return -ENODEV; 1236d405a98cSShreyas B. Prabhu } 12379c7b185aSAkshay Adiga nr_idle_states = of_property_count_u32_elems(np, 1238d405a98cSShreyas B. Prabhu "ibm,cpu-idle-state-flags"); 12399c7b185aSAkshay Adiga 12409c7b185aSAkshay Adiga pnv_idle_states = kcalloc(nr_idle_states, sizeof(*pnv_idle_states), 12419c7b185aSAkshay Adiga GFP_KERNEL); 12429c7b185aSAkshay Adiga temp_u32 = kcalloc(nr_idle_states, sizeof(u32), GFP_KERNEL); 12439c7b185aSAkshay Adiga temp_u64 = kcalloc(nr_idle_states, sizeof(u64), GFP_KERNEL); 12449c7b185aSAkshay Adiga temp_string = kcalloc(nr_idle_states, sizeof(char *), GFP_KERNEL); 12459c7b185aSAkshay Adiga 12469c7b185aSAkshay Adiga if (!(pnv_idle_states && temp_u32 && temp_u64 && temp_string)) { 12479c7b185aSAkshay Adiga pr_err("Could not allocate memory for dt parsing\n"); 12489c7b185aSAkshay Adiga rc = -ENOMEM; 1249d405a98cSShreyas B. Prabhu goto out; 1250d405a98cSShreyas B. Prabhu } 1251d405a98cSShreyas B. Prabhu 12529c7b185aSAkshay Adiga /* Read flags */ 12539c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-flags", 12549c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 1255d405a98cSShreyas B. Prabhu pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n"); 12569c7b185aSAkshay Adiga rc = -EINVAL; 1257bcef83a0SShreyas B. Prabhu goto out; 1258bcef83a0SShreyas B. Prabhu } 12599c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12609c7b185aSAkshay Adiga pnv_idle_states[i].flags = temp_u32[i]; 1261bcef83a0SShreyas B. Prabhu 12629c7b185aSAkshay Adiga /* Read latencies */ 12639c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-latencies-ns", 12649c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 12659c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-latencies-ns in DT\n"); 12669c7b185aSAkshay Adiga rc = -EINVAL; 12679c7b185aSAkshay Adiga goto out; 12689c7b185aSAkshay Adiga } 12699c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12709c7b185aSAkshay Adiga pnv_idle_states[i].latency_ns = temp_u32[i]; 12719c7b185aSAkshay Adiga 12729c7b185aSAkshay Adiga /* Read residencies */ 12739c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-residency-ns", 12749c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 12759c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-latencies-ns in DT\n"); 12769c7b185aSAkshay Adiga rc = -EINVAL; 12779c7b185aSAkshay Adiga goto out; 12789c7b185aSAkshay Adiga } 12799c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12809c7b185aSAkshay Adiga pnv_idle_states[i].residency_ns = temp_u32[i]; 12819c7b185aSAkshay Adiga 12829c7b185aSAkshay Adiga /* For power9 */ 1283bcef83a0SShreyas B. Prabhu if (cpu_has_feature(CPU_FTR_ARCH_300)) { 12849c7b185aSAkshay Adiga /* Read pm_crtl_val */ 12859c7b185aSAkshay Adiga if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr", 12869c7b185aSAkshay Adiga temp_u64, nr_idle_states)) { 12879c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n"); 12889c7b185aSAkshay Adiga rc = -EINVAL; 1289bcef83a0SShreyas B. Prabhu goto out; 1290d405a98cSShreyas B. Prabhu } 12919c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12929c7b185aSAkshay Adiga pnv_idle_states[i].psscr_val = temp_u64[i]; 1293d405a98cSShreyas B. Prabhu 12949c7b185aSAkshay Adiga /* Read pm_crtl_mask */ 12959c7b185aSAkshay Adiga if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr-mask", 12969c7b185aSAkshay Adiga temp_u64, nr_idle_states)) { 12979c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n"); 12989c7b185aSAkshay Adiga rc = -EINVAL; 12999c7b185aSAkshay Adiga goto out; 1300bcef83a0SShreyas B. Prabhu } 13019c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 13029c7b185aSAkshay Adiga pnv_idle_states[i].psscr_mask = temp_u64[i]; 13039c7b185aSAkshay Adiga } 13049c7b185aSAkshay Adiga 13059c7b185aSAkshay Adiga /* 13069c7b185aSAkshay Adiga * power8 specific properties ibm,cpu-idle-state-pmicr-mask and 13079c7b185aSAkshay Adiga * ibm,cpu-idle-state-pmicr-val were never used and there is no 13089c7b185aSAkshay Adiga * plan to use it in near future. Hence, not parsing these properties 13099c7b185aSAkshay Adiga */ 13109c7b185aSAkshay Adiga 13119c7b185aSAkshay Adiga if (of_property_read_string_array(np, "ibm,cpu-idle-state-names", 13129c7b185aSAkshay Adiga temp_string, nr_idle_states) < 0) { 13139c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-names in DT\n"); 13149c7b185aSAkshay Adiga rc = -EINVAL; 13159c7b185aSAkshay Adiga goto out; 13169c7b185aSAkshay Adiga } 13179c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 1318ae24ce5eSAneesh Kumar K.V strlcpy(pnv_idle_states[i].name, temp_string[i], 13199c7b185aSAkshay Adiga PNV_IDLE_NAME_LEN); 13209c7b185aSAkshay Adiga nr_pnv_idle_states = nr_idle_states; 13219c7b185aSAkshay Adiga rc = 0; 13229c7b185aSAkshay Adiga out: 13239c7b185aSAkshay Adiga kfree(temp_u32); 13249c7b185aSAkshay Adiga kfree(temp_u64); 13259c7b185aSAkshay Adiga kfree(temp_string); 13269c7b185aSAkshay Adiga return rc; 13279c7b185aSAkshay Adiga } 13289c7b185aSAkshay Adiga 1329bcef83a0SShreyas B. Prabhu static int __init pnv_init_idle_states(void) 1330bcef83a0SShreyas B. Prabhu { 133110d91611SNicholas Piggin int cpu; 13329c7b185aSAkshay Adiga int rc = 0; 133310d91611SNicholas Piggin 133410d91611SNicholas Piggin /* Set up PACA fields */ 133510d91611SNicholas Piggin for_each_present_cpu(cpu) { 133610d91611SNicholas Piggin struct paca_struct *p = paca_ptrs[cpu]; 133710d91611SNicholas Piggin 133810d91611SNicholas Piggin p->idle_state = 0; 133910d91611SNicholas Piggin if (cpu == cpu_first_thread_sibling(cpu)) 134010d91611SNicholas Piggin p->idle_state = (1 << threads_per_core) - 1; 134110d91611SNicholas Piggin 134210d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 134310d91611SNicholas Piggin /* P7/P8 nap */ 134410d91611SNicholas Piggin p->thread_idle_state = PNV_THREAD_RUNNING; 134510d91611SNicholas Piggin } else { 134610d91611SNicholas Piggin /* P9 stop */ 134710d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 134810d91611SNicholas Piggin p->requested_psscr = 0; 134910d91611SNicholas Piggin atomic_set(&p->dont_stop, 0); 135010d91611SNicholas Piggin #endif 135110d91611SNicholas Piggin } 135210d91611SNicholas Piggin } 1353bcef83a0SShreyas B. Prabhu 13549c7b185aSAkshay Adiga /* In case we error out nr_pnv_idle_states will be zero */ 13559c7b185aSAkshay Adiga nr_pnv_idle_states = 0; 135610d91611SNicholas Piggin supported_cpuidle_states = 0; 135710d91611SNicholas Piggin 1358bcef83a0SShreyas B. Prabhu if (cpuidle_disable != IDLE_NO_OVERRIDE) 1359bcef83a0SShreyas B. Prabhu goto out; 13609c7b185aSAkshay Adiga rc = pnv_parse_cpuidle_dt(); 13619c7b185aSAkshay Adiga if (rc) 13629c7b185aSAkshay Adiga return rc; 1363bcef83a0SShreyas B. Prabhu pnv_probe_idle_states(); 1364bcef83a0SShreyas B. Prabhu 136510d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1366d405a98cSShreyas B. Prabhu if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { 136710d91611SNicholas Piggin power7_fastsleep_workaround_entry = false; 136810d91611SNicholas Piggin power7_fastsleep_workaround_exit = false; 13695703d2f4SShreyas B. Prabhu } else { 13705703d2f4SShreyas B. Prabhu /* 13715703d2f4SShreyas B. Prabhu * OPAL_PM_SLEEP_ENABLED_ER1 is set. It indicates that 13725703d2f4SShreyas B. Prabhu * workaround is needed to use fastsleep. Provide sysfs 137310d91611SNicholas Piggin * control to choose how this workaround has to be 137410d91611SNicholas Piggin * applied. 13755703d2f4SShreyas B. Prabhu */ 13765703d2f4SShreyas B. Prabhu device_create_file(cpu_subsys.dev_root, 13775703d2f4SShreyas B. Prabhu &dev_attr_fastsleep_workaround_applyonce); 1378d405a98cSShreyas B. Prabhu } 13795703d2f4SShreyas B. Prabhu 138010d91611SNicholas Piggin update_subcore_sibling_mask(); 13815593e303SShreyas B. Prabhu 138210d91611SNicholas Piggin if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED) { 13835593e303SShreyas B. Prabhu ppc_md.power_save = power7_idle; 138410d91611SNicholas Piggin power7_offline_type = PNV_THREAD_NAP; 138510d91611SNicholas Piggin } 138610d91611SNicholas Piggin 138710d91611SNicholas Piggin if ((supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED) && 138810d91611SNicholas Piggin (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT)) 138910d91611SNicholas Piggin power7_offline_type = PNV_THREAD_WINKLE; 139010d91611SNicholas Piggin else if ((supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED) || 139110d91611SNicholas Piggin (supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) 139210d91611SNicholas Piggin power7_offline_type = PNV_THREAD_SLEEP; 139310d91611SNicholas Piggin } 139410d91611SNicholas Piggin 139510d91611SNicholas Piggin if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) { 139610d91611SNicholas Piggin if (pnv_save_sprs_for_deep_states()) 139710d91611SNicholas Piggin pnv_disable_deep_states(); 139810d91611SNicholas Piggin } 1399bcef83a0SShreyas B. Prabhu 1400d405a98cSShreyas B. Prabhu out: 1401d405a98cSShreyas B. Prabhu return 0; 1402d405a98cSShreyas B. Prabhu } 14034bece972SMichael Ellerman machine_subsys_initcall(powernv, pnv_init_idle_states); 1404