12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2d405a98cSShreyas B. Prabhu /* 3d405a98cSShreyas B. Prabhu * PowerNV cpuidle code 4d405a98cSShreyas B. Prabhu * 5d405a98cSShreyas B. Prabhu * Copyright 2015 IBM Corp. 6d405a98cSShreyas B. Prabhu */ 7d405a98cSShreyas B. Prabhu 8d405a98cSShreyas B. Prabhu #include <linux/types.h> 9d405a98cSShreyas B. Prabhu #include <linux/mm.h> 10d405a98cSShreyas B. Prabhu #include <linux/slab.h> 11d405a98cSShreyas B. Prabhu #include <linux/of.h> 125703d2f4SShreyas B. Prabhu #include <linux/device.h> 135703d2f4SShreyas B. Prabhu #include <linux/cpu.h> 14d405a98cSShreyas B. Prabhu 1510d91611SNicholas Piggin #include <asm/asm-prototypes.h> 16d405a98cSShreyas B. Prabhu #include <asm/firmware.h> 174bece972SMichael Ellerman #include <asm/machdep.h> 18d405a98cSShreyas B. Prabhu #include <asm/opal.h> 19d405a98cSShreyas B. Prabhu #include <asm/cputhreads.h> 20d405a98cSShreyas B. Prabhu #include <asm/cpuidle.h> 21d405a98cSShreyas B. Prabhu #include <asm/code-patching.h> 22d405a98cSShreyas B. Prabhu #include <asm/smp.h> 232201f994SNicholas Piggin #include <asm/runlatch.h> 247672691aSPaul Mackerras #include <asm/dbell.h> 25d405a98cSShreyas B. Prabhu 26d405a98cSShreyas B. Prabhu #include "powernv.h" 27d405a98cSShreyas B. Prabhu #include "subcore.h" 28d405a98cSShreyas B. Prabhu 29bcef83a0SShreyas B. Prabhu /* Power ISA 3.0 allows for stop states 0x0 - 0xF */ 30bcef83a0SShreyas B. Prabhu #define MAX_STOP_STATE 0xF 31bcef83a0SShreyas B. Prabhu 321e1601b3SAkshay Adiga #define P9_STOP_SPR_MSR 2000 331e1601b3SAkshay Adiga #define P9_STOP_SPR_PSSCR 855 341e1601b3SAkshay Adiga 35d405a98cSShreyas B. Prabhu static u32 supported_cpuidle_states; 369c7b185aSAkshay Adiga struct pnv_idle_states_t *pnv_idle_states; 379c7b185aSAkshay Adiga int nr_pnv_idle_states; 38d405a98cSShreyas B. Prabhu 391e1601b3SAkshay Adiga /* 401e1601b3SAkshay Adiga * The default stop state that will be used by ppc_md.power_save 411e1601b3SAkshay Adiga * function on platforms that support stop instruction. 421e1601b3SAkshay Adiga */ 431e1601b3SAkshay Adiga static u64 pnv_default_stop_val; 441e1601b3SAkshay Adiga static u64 pnv_default_stop_mask; 451e1601b3SAkshay Adiga static bool default_stop_found; 461e1601b3SAkshay Adiga 471e1601b3SAkshay Adiga /* 4810d91611SNicholas Piggin * First stop state levels when SPR and TB loss can occur. 491e1601b3SAkshay Adiga */ 5010d91611SNicholas Piggin static u64 pnv_first_tb_loss_level = MAX_STOP_STATE + 1; 5110d91611SNicholas Piggin static u64 pnv_first_spr_loss_level = MAX_STOP_STATE + 1; 521e1601b3SAkshay Adiga 531e1601b3SAkshay Adiga /* 541e1601b3SAkshay Adiga * psscr value and mask of the deepest stop idle state. 551e1601b3SAkshay Adiga * Used when a cpu is offlined. 561e1601b3SAkshay Adiga */ 571e1601b3SAkshay Adiga static u64 pnv_deepest_stop_psscr_val; 581e1601b3SAkshay Adiga static u64 pnv_deepest_stop_psscr_mask; 59785a12afSGautham R. Shenoy static u64 pnv_deepest_stop_flag; 601e1601b3SAkshay Adiga static bool deepest_stop_found; 611e1601b3SAkshay Adiga 6210d91611SNicholas Piggin static unsigned long power7_offline_type; 6310d91611SNicholas Piggin 64bcef83a0SShreyas B. Prabhu static int pnv_save_sprs_for_deep_states(void) 65d405a98cSShreyas B. Prabhu { 66d405a98cSShreyas B. Prabhu int cpu; 67d405a98cSShreyas B. Prabhu int rc; 68d405a98cSShreyas B. Prabhu 69d405a98cSShreyas B. Prabhu /* 70446957baSAdam Buchbinder * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across 71d405a98cSShreyas B. Prabhu * all cpus at boot. Get these reg values of current cpu and use the 72446957baSAdam Buchbinder * same across all cpus. 73d405a98cSShreyas B. Prabhu */ 7424be85a2SGautham R. Shenoy uint64_t lpcr_val = mfspr(SPRN_LPCR); 75d405a98cSShreyas B. Prabhu uint64_t hid0_val = mfspr(SPRN_HID0); 76d405a98cSShreyas B. Prabhu uint64_t hid1_val = mfspr(SPRN_HID1); 77d405a98cSShreyas B. Prabhu uint64_t hid4_val = mfspr(SPRN_HID4); 78d405a98cSShreyas B. Prabhu uint64_t hid5_val = mfspr(SPRN_HID5); 79d405a98cSShreyas B. Prabhu uint64_t hmeer_val = mfspr(SPRN_HMEER); 801e1601b3SAkshay Adiga uint64_t msr_val = MSR_IDLE; 811e1601b3SAkshay Adiga uint64_t psscr_val = pnv_deepest_stop_psscr_val; 82d405a98cSShreyas B. Prabhu 83ac9816dcSAkshay Adiga for_each_present_cpu(cpu) { 84d405a98cSShreyas B. Prabhu uint64_t pir = get_hard_smp_processor_id(cpu); 85d2e60075SNicholas Piggin uint64_t hsprg0_val = (uint64_t)paca_ptrs[cpu]; 86d405a98cSShreyas B. Prabhu 87d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); 88d405a98cSShreyas B. Prabhu if (rc != 0) 89d405a98cSShreyas B. Prabhu return rc; 90d405a98cSShreyas B. Prabhu 91d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 92d405a98cSShreyas B. Prabhu if (rc != 0) 93d405a98cSShreyas B. Prabhu return rc; 94d405a98cSShreyas B. Prabhu 951e1601b3SAkshay Adiga if (cpu_has_feature(CPU_FTR_ARCH_300)) { 961e1601b3SAkshay Adiga rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); 971e1601b3SAkshay Adiga if (rc) 981e1601b3SAkshay Adiga return rc; 991e1601b3SAkshay Adiga 1001e1601b3SAkshay Adiga rc = opal_slw_set_reg(pir, 1011e1601b3SAkshay Adiga P9_STOP_SPR_PSSCR, psscr_val); 1021e1601b3SAkshay Adiga 1031e1601b3SAkshay Adiga if (rc) 1041e1601b3SAkshay Adiga return rc; 1051e1601b3SAkshay Adiga } 1061e1601b3SAkshay Adiga 107d405a98cSShreyas B. Prabhu /* HIDs are per core registers */ 108d405a98cSShreyas B. Prabhu if (cpu_thread_in_core(cpu) == 0) { 109d405a98cSShreyas B. Prabhu 110d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); 111d405a98cSShreyas B. Prabhu if (rc != 0) 112d405a98cSShreyas B. Prabhu return rc; 113d405a98cSShreyas B. Prabhu 114d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); 115d405a98cSShreyas B. Prabhu if (rc != 0) 116d405a98cSShreyas B. Prabhu return rc; 117d405a98cSShreyas B. Prabhu 1181e1601b3SAkshay Adiga /* Only p8 needs to set extra HID regiters */ 1191e1601b3SAkshay Adiga if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1201e1601b3SAkshay Adiga 121d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); 122d405a98cSShreyas B. Prabhu if (rc != 0) 123d405a98cSShreyas B. Prabhu return rc; 124d405a98cSShreyas B. Prabhu 125d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); 126d405a98cSShreyas B. Prabhu if (rc != 0) 127d405a98cSShreyas B. Prabhu return rc; 128d405a98cSShreyas B. Prabhu 129d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); 130d405a98cSShreyas B. Prabhu if (rc != 0) 131d405a98cSShreyas B. Prabhu return rc; 132d405a98cSShreyas B. Prabhu } 133d405a98cSShreyas B. Prabhu } 1341e1601b3SAkshay Adiga } 135d405a98cSShreyas B. Prabhu 136d405a98cSShreyas B. Prabhu return 0; 137d405a98cSShreyas B. Prabhu } 138d405a98cSShreyas B. Prabhu 139d405a98cSShreyas B. Prabhu u32 pnv_get_supported_cpuidle_states(void) 140d405a98cSShreyas B. Prabhu { 141d405a98cSShreyas B. Prabhu return supported_cpuidle_states; 142d405a98cSShreyas B. Prabhu } 143d405a98cSShreyas B. Prabhu EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states); 144d405a98cSShreyas B. Prabhu 1455703d2f4SShreyas B. Prabhu static void pnv_fastsleep_workaround_apply(void *info) 1465703d2f4SShreyas B. Prabhu 1475703d2f4SShreyas B. Prabhu { 1485703d2f4SShreyas B. Prabhu int rc; 1495703d2f4SShreyas B. Prabhu int *err = info; 1505703d2f4SShreyas B. Prabhu 1515703d2f4SShreyas B. Prabhu rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 1525703d2f4SShreyas B. Prabhu OPAL_CONFIG_IDLE_APPLY); 1535703d2f4SShreyas B. Prabhu if (rc) 1545703d2f4SShreyas B. Prabhu *err = 1; 1555703d2f4SShreyas B. Prabhu } 1565703d2f4SShreyas B. Prabhu 15710d91611SNicholas Piggin static bool power7_fastsleep_workaround_entry = true; 15810d91611SNicholas Piggin static bool power7_fastsleep_workaround_exit = true; 15910d91611SNicholas Piggin 1605703d2f4SShreyas B. Prabhu /* 1615703d2f4SShreyas B. Prabhu * Used to store fastsleep workaround state 1625703d2f4SShreyas B. Prabhu * 0 - Workaround applied/undone at fastsleep entry/exit path (Default) 1635703d2f4SShreyas B. Prabhu * 1 - Workaround applied once, never undone. 1645703d2f4SShreyas B. Prabhu */ 1655703d2f4SShreyas B. Prabhu static u8 fastsleep_workaround_applyonce; 1665703d2f4SShreyas B. Prabhu 1675703d2f4SShreyas B. Prabhu static ssize_t show_fastsleep_workaround_applyonce(struct device *dev, 1685703d2f4SShreyas B. Prabhu struct device_attribute *attr, char *buf) 1695703d2f4SShreyas B. Prabhu { 1705703d2f4SShreyas B. Prabhu return sprintf(buf, "%u\n", fastsleep_workaround_applyonce); 1715703d2f4SShreyas B. Prabhu } 1725703d2f4SShreyas B. Prabhu 1735703d2f4SShreyas B. Prabhu static ssize_t store_fastsleep_workaround_applyonce(struct device *dev, 1745703d2f4SShreyas B. Prabhu struct device_attribute *attr, const char *buf, 1755703d2f4SShreyas B. Prabhu size_t count) 1765703d2f4SShreyas B. Prabhu { 1775703d2f4SShreyas B. Prabhu cpumask_t primary_thread_mask; 1785703d2f4SShreyas B. Prabhu int err; 1795703d2f4SShreyas B. Prabhu u8 val; 1805703d2f4SShreyas B. Prabhu 1815703d2f4SShreyas B. Prabhu if (kstrtou8(buf, 0, &val) || val != 1) 1825703d2f4SShreyas B. Prabhu return -EINVAL; 1835703d2f4SShreyas B. Prabhu 1845703d2f4SShreyas B. Prabhu if (fastsleep_workaround_applyonce == 1) 1855703d2f4SShreyas B. Prabhu return count; 1865703d2f4SShreyas B. Prabhu 1875703d2f4SShreyas B. Prabhu /* 1885703d2f4SShreyas B. Prabhu * fastsleep_workaround_applyonce = 1 implies 1895703d2f4SShreyas B. Prabhu * fastsleep workaround needs to be left in 'applied' state on all 1905703d2f4SShreyas B. Prabhu * the cores. Do this by- 19110d91611SNicholas Piggin * 1. Disable the 'undo' workaround in fastsleep exit path 19210d91611SNicholas Piggin * 2. Sendi IPIs to all the cores which have at least one online thread 19310d91611SNicholas Piggin * 3. Disable the 'apply' workaround in fastsleep entry path 19410d91611SNicholas Piggin * 1955703d2f4SShreyas B. Prabhu * There is no need to send ipi to cores which have all threads 1965703d2f4SShreyas B. Prabhu * offlined, as last thread of the core entering fastsleep or deeper 1975703d2f4SShreyas B. Prabhu * state would have applied workaround. 1985703d2f4SShreyas B. Prabhu */ 19910d91611SNicholas Piggin power7_fastsleep_workaround_exit = false; 2005703d2f4SShreyas B. Prabhu 2015703d2f4SShreyas B. Prabhu get_online_cpus(); 2025703d2f4SShreyas B. Prabhu primary_thread_mask = cpu_online_cores_map(); 2035703d2f4SShreyas B. Prabhu on_each_cpu_mask(&primary_thread_mask, 2045703d2f4SShreyas B. Prabhu pnv_fastsleep_workaround_apply, 2055703d2f4SShreyas B. Prabhu &err, 1); 2065703d2f4SShreyas B. Prabhu put_online_cpus(); 2075703d2f4SShreyas B. Prabhu if (err) { 2085703d2f4SShreyas B. Prabhu pr_err("fastsleep_workaround_applyonce change failed while running pnv_fastsleep_workaround_apply"); 2095703d2f4SShreyas B. Prabhu goto fail; 2105703d2f4SShreyas B. Prabhu } 2115703d2f4SShreyas B. Prabhu 21210d91611SNicholas Piggin power7_fastsleep_workaround_entry = false; 2135703d2f4SShreyas B. Prabhu 2145703d2f4SShreyas B. Prabhu fastsleep_workaround_applyonce = 1; 2155703d2f4SShreyas B. Prabhu 2165703d2f4SShreyas B. Prabhu return count; 2175703d2f4SShreyas B. Prabhu fail: 2185703d2f4SShreyas B. Prabhu return -EIO; 2195703d2f4SShreyas B. Prabhu } 2205703d2f4SShreyas B. Prabhu 2215703d2f4SShreyas B. Prabhu static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600, 2225703d2f4SShreyas B. Prabhu show_fastsleep_workaround_applyonce, 2235703d2f4SShreyas B. Prabhu store_fastsleep_workaround_applyonce); 2245703d2f4SShreyas B. Prabhu 22510d91611SNicholas Piggin static inline void atomic_start_thread_idle(void) 2262201f994SNicholas Piggin { 22710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 22810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 22910d91611SNicholas Piggin int thread_nr = cpu_thread_in_core(cpu); 23010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 23110d91611SNicholas Piggin 23210d91611SNicholas Piggin clear_bit(thread_nr, state); 23310d91611SNicholas Piggin } 23410d91611SNicholas Piggin 23510d91611SNicholas Piggin static inline void atomic_stop_thread_idle(void) 23610d91611SNicholas Piggin { 23710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 23810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 23910d91611SNicholas Piggin int thread_nr = cpu_thread_in_core(cpu); 24010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 24110d91611SNicholas Piggin 24210d91611SNicholas Piggin set_bit(thread_nr, state); 24310d91611SNicholas Piggin } 24410d91611SNicholas Piggin 24510d91611SNicholas Piggin static inline void atomic_lock_thread_idle(void) 24610d91611SNicholas Piggin { 24710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 24810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 24910d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 25010d91611SNicholas Piggin 25110d91611SNicholas Piggin while (unlikely(test_and_set_bit_lock(NR_PNV_CORE_IDLE_LOCK_BIT, state))) 25210d91611SNicholas Piggin barrier(); 25310d91611SNicholas Piggin } 25410d91611SNicholas Piggin 25510d91611SNicholas Piggin static inline void atomic_unlock_and_stop_thread_idle(void) 25610d91611SNicholas Piggin { 25710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 25810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 25910d91611SNicholas Piggin unsigned long thread = 1UL << cpu_thread_in_core(cpu); 26010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 26110d91611SNicholas Piggin u64 s = READ_ONCE(*state); 26210d91611SNicholas Piggin u64 new, tmp; 26310d91611SNicholas Piggin 26410d91611SNicholas Piggin BUG_ON(!(s & PNV_CORE_IDLE_LOCK_BIT)); 26510d91611SNicholas Piggin BUG_ON(s & thread); 26610d91611SNicholas Piggin 26710d91611SNicholas Piggin again: 26810d91611SNicholas Piggin new = (s | thread) & ~PNV_CORE_IDLE_LOCK_BIT; 26910d91611SNicholas Piggin tmp = cmpxchg(state, s, new); 27010d91611SNicholas Piggin if (unlikely(tmp != s)) { 27110d91611SNicholas Piggin s = tmp; 27210d91611SNicholas Piggin goto again; 27310d91611SNicholas Piggin } 27410d91611SNicholas Piggin } 27510d91611SNicholas Piggin 27610d91611SNicholas Piggin static inline void atomic_unlock_thread_idle(void) 27710d91611SNicholas Piggin { 27810d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 27910d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 28010d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 28110d91611SNicholas Piggin 28210d91611SNicholas Piggin BUG_ON(!test_bit(NR_PNV_CORE_IDLE_LOCK_BIT, state)); 28310d91611SNicholas Piggin clear_bit_unlock(NR_PNV_CORE_IDLE_LOCK_BIT, state); 28410d91611SNicholas Piggin } 28510d91611SNicholas Piggin 28610d91611SNicholas Piggin /* P7 and P8 */ 28710d91611SNicholas Piggin struct p7_sprs { 28810d91611SNicholas Piggin /* per core */ 28910d91611SNicholas Piggin u64 tscr; 29010d91611SNicholas Piggin u64 worc; 29110d91611SNicholas Piggin 29210d91611SNicholas Piggin /* per subcore */ 29310d91611SNicholas Piggin u64 sdr1; 29410d91611SNicholas Piggin u64 rpr; 29510d91611SNicholas Piggin 29610d91611SNicholas Piggin /* per thread */ 29710d91611SNicholas Piggin u64 lpcr; 29810d91611SNicholas Piggin u64 hfscr; 29910d91611SNicholas Piggin u64 fscr; 30010d91611SNicholas Piggin u64 purr; 30110d91611SNicholas Piggin u64 spurr; 30210d91611SNicholas Piggin u64 dscr; 30310d91611SNicholas Piggin u64 wort; 304e9cef018SMichael Ellerman 305e9cef018SMichael Ellerman /* per thread SPRs that get lost in shallow states */ 306e9cef018SMichael Ellerman u64 amr; 307e9cef018SMichael Ellerman u64 iamr; 308e9cef018SMichael Ellerman u64 amor; 309e9cef018SMichael Ellerman u64 uamor; 31010d91611SNicholas Piggin }; 31110d91611SNicholas Piggin 31210d91611SNicholas Piggin static unsigned long power7_idle_insn(unsigned long type) 31310d91611SNicholas Piggin { 31410d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 31510d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 31610d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 31710d91611SNicholas Piggin unsigned long thread = 1UL << cpu_thread_in_core(cpu); 31810d91611SNicholas Piggin unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 3192201f994SNicholas Piggin unsigned long srr1; 32010d91611SNicholas Piggin bool full_winkle; 32110d91611SNicholas Piggin struct p7_sprs sprs = {}; /* avoid false use-uninitialised */ 32210d91611SNicholas Piggin bool sprs_saved = false; 32310d91611SNicholas Piggin int rc; 3242201f994SNicholas Piggin 32510d91611SNicholas Piggin if (unlikely(type != PNV_THREAD_NAP)) { 32610d91611SNicholas Piggin atomic_lock_thread_idle(); 3272201f994SNicholas Piggin 32810d91611SNicholas Piggin BUG_ON(!(*state & thread)); 32910d91611SNicholas Piggin *state &= ~thread; 3302201f994SNicholas Piggin 33110d91611SNicholas Piggin if (power7_fastsleep_workaround_entry) { 33210d91611SNicholas Piggin if ((*state & core_thread_mask) == 0) { 33310d91611SNicholas Piggin rc = opal_config_cpu_idle_state( 33410d91611SNicholas Piggin OPAL_CONFIG_IDLE_FASTSLEEP, 33510d91611SNicholas Piggin OPAL_CONFIG_IDLE_APPLY); 33610d91611SNicholas Piggin BUG_ON(rc); 33710d91611SNicholas Piggin } 33810d91611SNicholas Piggin } 33910d91611SNicholas Piggin 34010d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 34110d91611SNicholas Piggin sprs.tscr = mfspr(SPRN_TSCR); 34210d91611SNicholas Piggin sprs.worc = mfspr(SPRN_WORC); 34310d91611SNicholas Piggin 34410d91611SNicholas Piggin sprs.sdr1 = mfspr(SPRN_SDR1); 34510d91611SNicholas Piggin sprs.rpr = mfspr(SPRN_RPR); 34610d91611SNicholas Piggin 34710d91611SNicholas Piggin sprs.lpcr = mfspr(SPRN_LPCR); 34810d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 34910d91611SNicholas Piggin sprs.hfscr = mfspr(SPRN_HFSCR); 35010d91611SNicholas Piggin sprs.fscr = mfspr(SPRN_FSCR); 35110d91611SNicholas Piggin } 35210d91611SNicholas Piggin sprs.purr = mfspr(SPRN_PURR); 35310d91611SNicholas Piggin sprs.spurr = mfspr(SPRN_SPURR); 35410d91611SNicholas Piggin sprs.dscr = mfspr(SPRN_DSCR); 35510d91611SNicholas Piggin sprs.wort = mfspr(SPRN_WORT); 35610d91611SNicholas Piggin 35710d91611SNicholas Piggin sprs_saved = true; 35810d91611SNicholas Piggin 35910d91611SNicholas Piggin /* 36010d91611SNicholas Piggin * Increment winkle counter and set all winkle bits if 36110d91611SNicholas Piggin * all threads are winkling. This allows wakeup side to 36210d91611SNicholas Piggin * distinguish between fast sleep and winkle state 36310d91611SNicholas Piggin * loss. Fast sleep still has to resync the timebase so 36410d91611SNicholas Piggin * this may not be a really big win. 36510d91611SNicholas Piggin */ 36610d91611SNicholas Piggin *state += 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 36710d91611SNicholas Piggin if ((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) 36810d91611SNicholas Piggin >> PNV_CORE_IDLE_WINKLE_COUNT_SHIFT 36910d91611SNicholas Piggin == threads_per_core) 37010d91611SNicholas Piggin *state |= PNV_CORE_IDLE_THREAD_WINKLE_BITS; 37110d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 37210d91611SNicholas Piggin } 37310d91611SNicholas Piggin 37410d91611SNicholas Piggin atomic_unlock_thread_idle(); 37510d91611SNicholas Piggin } 37610d91611SNicholas Piggin 377e9cef018SMichael Ellerman if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 378e9cef018SMichael Ellerman sprs.amr = mfspr(SPRN_AMR); 379e9cef018SMichael Ellerman sprs.iamr = mfspr(SPRN_IAMR); 380e9cef018SMichael Ellerman sprs.amor = mfspr(SPRN_AMOR); 381e9cef018SMichael Ellerman sprs.uamor = mfspr(SPRN_UAMOR); 382e9cef018SMichael Ellerman } 383e9cef018SMichael Ellerman 38410d91611SNicholas Piggin local_paca->thread_idle_state = type; 38510d91611SNicholas Piggin srr1 = isa206_idle_insn_mayloss(type); /* go idle */ 38610d91611SNicholas Piggin local_paca->thread_idle_state = PNV_THREAD_RUNNING; 38710d91611SNicholas Piggin 38810d91611SNicholas Piggin WARN_ON_ONCE(!srr1); 38910d91611SNicholas Piggin WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 39010d91611SNicholas Piggin 391e9cef018SMichael Ellerman if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 392e9cef018SMichael Ellerman if ((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS) { 393e9cef018SMichael Ellerman /* 394e9cef018SMichael Ellerman * We don't need an isync after the mtsprs here because 395e9cef018SMichael Ellerman * the upcoming mtmsrd is execution synchronizing. 396e9cef018SMichael Ellerman */ 397e9cef018SMichael Ellerman mtspr(SPRN_AMR, sprs.amr); 398e9cef018SMichael Ellerman mtspr(SPRN_IAMR, sprs.iamr); 399e9cef018SMichael Ellerman mtspr(SPRN_AMOR, sprs.amor); 400e9cef018SMichael Ellerman mtspr(SPRN_UAMOR, sprs.uamor); 401e9cef018SMichael Ellerman } 402e9cef018SMichael Ellerman } 403e9cef018SMichael Ellerman 40410d91611SNicholas Piggin if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 40510d91611SNicholas Piggin hmi_exception_realmode(NULL); 40610d91611SNicholas Piggin 40710d91611SNicholas Piggin if (likely((srr1 & SRR1_WAKESTATE) != SRR1_WS_HVLOSS)) { 40810d91611SNicholas Piggin if (unlikely(type != PNV_THREAD_NAP)) { 40910d91611SNicholas Piggin atomic_lock_thread_idle(); 41010d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 41110d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 41210d91611SNicholas Piggin *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 41310d91611SNicholas Piggin *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); 41410d91611SNicholas Piggin } 41510d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 41610d91611SNicholas Piggin } 41710d91611SNicholas Piggin return srr1; 41810d91611SNicholas Piggin } 41910d91611SNicholas Piggin 42010d91611SNicholas Piggin /* HV state loss */ 42110d91611SNicholas Piggin BUG_ON(type == PNV_THREAD_NAP); 42210d91611SNicholas Piggin 42310d91611SNicholas Piggin atomic_lock_thread_idle(); 42410d91611SNicholas Piggin 42510d91611SNicholas Piggin full_winkle = false; 42610d91611SNicholas Piggin if (type == PNV_THREAD_WINKLE) { 42710d91611SNicholas Piggin WARN_ON((*state & PNV_CORE_IDLE_WINKLE_COUNT_BITS) == 0); 42810d91611SNicholas Piggin *state -= 1 << PNV_CORE_IDLE_WINKLE_COUNT_SHIFT; 42910d91611SNicholas Piggin if (*state & (thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT)) { 43010d91611SNicholas Piggin *state &= ~(thread << PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT); 43110d91611SNicholas Piggin full_winkle = true; 43210d91611SNicholas Piggin BUG_ON(!sprs_saved); 43310d91611SNicholas Piggin } 43410d91611SNicholas Piggin } 43510d91611SNicholas Piggin 43610d91611SNicholas Piggin WARN_ON(*state & thread); 43710d91611SNicholas Piggin 43810d91611SNicholas Piggin if ((*state & core_thread_mask) != 0) 43910d91611SNicholas Piggin goto core_woken; 44010d91611SNicholas Piggin 44110d91611SNicholas Piggin /* Per-core SPRs */ 44210d91611SNicholas Piggin if (full_winkle) { 44310d91611SNicholas Piggin mtspr(SPRN_TSCR, sprs.tscr); 44410d91611SNicholas Piggin mtspr(SPRN_WORC, sprs.worc); 44510d91611SNicholas Piggin } 44610d91611SNicholas Piggin 44710d91611SNicholas Piggin if (power7_fastsleep_workaround_exit) { 44810d91611SNicholas Piggin rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 44910d91611SNicholas Piggin OPAL_CONFIG_IDLE_UNDO); 45010d91611SNicholas Piggin BUG_ON(rc); 45110d91611SNicholas Piggin } 45210d91611SNicholas Piggin 45310d91611SNicholas Piggin /* TB */ 45410d91611SNicholas Piggin if (opal_resync_timebase() != OPAL_SUCCESS) 45510d91611SNicholas Piggin BUG(); 45610d91611SNicholas Piggin 45710d91611SNicholas Piggin core_woken: 45810d91611SNicholas Piggin if (!full_winkle) 45910d91611SNicholas Piggin goto subcore_woken; 46010d91611SNicholas Piggin 46110d91611SNicholas Piggin if ((*state & local_paca->subcore_sibling_mask) != 0) 46210d91611SNicholas Piggin goto subcore_woken; 46310d91611SNicholas Piggin 46410d91611SNicholas Piggin /* Per-subcore SPRs */ 46510d91611SNicholas Piggin mtspr(SPRN_SDR1, sprs.sdr1); 46610d91611SNicholas Piggin mtspr(SPRN_RPR, sprs.rpr); 46710d91611SNicholas Piggin 46810d91611SNicholas Piggin subcore_woken: 46910d91611SNicholas Piggin /* 47010d91611SNicholas Piggin * isync after restoring shared SPRs and before unlocking. Unlock 47110d91611SNicholas Piggin * only contains hwsync which does not necessarily do the right 47210d91611SNicholas Piggin * thing for SPRs. 47310d91611SNicholas Piggin */ 47410d91611SNicholas Piggin isync(); 47510d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 47610d91611SNicholas Piggin 47710d91611SNicholas Piggin /* Fast sleep does not lose SPRs */ 47810d91611SNicholas Piggin if (!full_winkle) 47910d91611SNicholas Piggin return srr1; 48010d91611SNicholas Piggin 48110d91611SNicholas Piggin /* Per-thread SPRs */ 48210d91611SNicholas Piggin mtspr(SPRN_LPCR, sprs.lpcr); 48310d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_207S)) { 48410d91611SNicholas Piggin mtspr(SPRN_HFSCR, sprs.hfscr); 48510d91611SNicholas Piggin mtspr(SPRN_FSCR, sprs.fscr); 48610d91611SNicholas Piggin } 48710d91611SNicholas Piggin mtspr(SPRN_PURR, sprs.purr); 48810d91611SNicholas Piggin mtspr(SPRN_SPURR, sprs.spurr); 48910d91611SNicholas Piggin mtspr(SPRN_DSCR, sprs.dscr); 49010d91611SNicholas Piggin mtspr(SPRN_WORT, sprs.wort); 49110d91611SNicholas Piggin 49210d91611SNicholas Piggin mtspr(SPRN_SPRG3, local_paca->sprg_vdso); 49310d91611SNicholas Piggin 49410d91611SNicholas Piggin /* 49510d91611SNicholas Piggin * The SLB has to be restored here, but it sometimes still 49610d91611SNicholas Piggin * contains entries, so the __ variant must be used to prevent 49710d91611SNicholas Piggin * multi hits. 49810d91611SNicholas Piggin */ 49910d91611SNicholas Piggin __slb_restore_bolted_realmode(); 5002201f994SNicholas Piggin 5012201f994SNicholas Piggin return srr1; 5022201f994SNicholas Piggin } 5032201f994SNicholas Piggin 50410d91611SNicholas Piggin extern unsigned long idle_kvm_start_guest(unsigned long srr1); 50510d91611SNicholas Piggin 50610d91611SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 50710d91611SNicholas Piggin static unsigned long power7_offline(void) 50810d91611SNicholas Piggin { 50910d91611SNicholas Piggin unsigned long srr1; 51010d91611SNicholas Piggin 51110d91611SNicholas Piggin mtmsr(MSR_IDLE); 51210d91611SNicholas Piggin 51310d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 51410d91611SNicholas Piggin /* Tell KVM we're entering idle. */ 51510d91611SNicholas Piggin /******************************************************/ 51610d91611SNicholas Piggin /* N O T E W E L L ! ! ! N O T E W E L L */ 51710d91611SNicholas Piggin /* The following store to HSTATE_HWTHREAD_STATE(r13) */ 51810d91611SNicholas Piggin /* MUST occur in real mode, i.e. with the MMU off, */ 51910d91611SNicholas Piggin /* and the MMU must stay off until we clear this flag */ 52010d91611SNicholas Piggin /* and test HSTATE_HWTHREAD_REQ(r13) in */ 52110d91611SNicholas Piggin /* pnv_powersave_wakeup in this file. */ 52210d91611SNicholas Piggin /* The reason is that another thread can switch the */ 52310d91611SNicholas Piggin /* MMU to a guest context whenever this flag is set */ 52410d91611SNicholas Piggin /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ 52510d91611SNicholas Piggin /* that would potentially cause this thread to start */ 52610d91611SNicholas Piggin /* executing instructions from guest memory in */ 52710d91611SNicholas Piggin /* hypervisor mode, leading to a host crash or data */ 52810d91611SNicholas Piggin /* corruption, or worse. */ 52910d91611SNicholas Piggin /******************************************************/ 53010d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_IDLE; 53110d91611SNicholas Piggin #endif 53210d91611SNicholas Piggin 53310d91611SNicholas Piggin __ppc64_runlatch_off(); 53410d91611SNicholas Piggin srr1 = power7_idle_insn(power7_offline_type); 53510d91611SNicholas Piggin __ppc64_runlatch_on(); 53610d91611SNicholas Piggin 53710d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 53810d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_KERNEL; 53910d91611SNicholas Piggin /* Order setting hwthread_state vs. testing hwthread_req */ 54010d91611SNicholas Piggin smp_mb(); 54110d91611SNicholas Piggin if (local_paca->kvm_hstate.hwthread_req) 54210d91611SNicholas Piggin srr1 = idle_kvm_start_guest(srr1); 54310d91611SNicholas Piggin #endif 54410d91611SNicholas Piggin 54510d91611SNicholas Piggin mtmsr(MSR_KERNEL); 54610d91611SNicholas Piggin 54710d91611SNicholas Piggin return srr1; 54810d91611SNicholas Piggin } 54910d91611SNicholas Piggin #endif 55010d91611SNicholas Piggin 5512201f994SNicholas Piggin void power7_idle_type(unsigned long type) 5522201f994SNicholas Piggin { 553771d4304SNicholas Piggin unsigned long srr1; 554771d4304SNicholas Piggin 55510d91611SNicholas Piggin if (!prep_irq_for_idle_irqsoff()) 55610d91611SNicholas Piggin return; 55710d91611SNicholas Piggin 55810d91611SNicholas Piggin mtmsr(MSR_IDLE); 55910d91611SNicholas Piggin __ppc64_runlatch_off(); 56010d91611SNicholas Piggin srr1 = power7_idle_insn(type); 56110d91611SNicholas Piggin __ppc64_runlatch_on(); 56210d91611SNicholas Piggin mtmsr(MSR_KERNEL); 56310d91611SNicholas Piggin 56410d91611SNicholas Piggin fini_irq_for_idle_irqsoff(); 565771d4304SNicholas Piggin irq_set_pending_from_srr1(srr1); 5662201f994SNicholas Piggin } 5672201f994SNicholas Piggin 5682201f994SNicholas Piggin void power7_idle(void) 5692201f994SNicholas Piggin { 5702201f994SNicholas Piggin if (!powersave_nap) 5712201f994SNicholas Piggin return; 5722201f994SNicholas Piggin 5732201f994SNicholas Piggin power7_idle_type(PNV_THREAD_NAP); 5742201f994SNicholas Piggin } 5752201f994SNicholas Piggin 57610d91611SNicholas Piggin struct p9_sprs { 57710d91611SNicholas Piggin /* per core */ 57810d91611SNicholas Piggin u64 ptcr; 57910d91611SNicholas Piggin u64 rpr; 58010d91611SNicholas Piggin u64 tscr; 58110d91611SNicholas Piggin u64 ldbar; 58210d91611SNicholas Piggin 58310d91611SNicholas Piggin /* per thread */ 58410d91611SNicholas Piggin u64 lpcr; 58510d91611SNicholas Piggin u64 hfscr; 58610d91611SNicholas Piggin u64 fscr; 58710d91611SNicholas Piggin u64 pid; 58810d91611SNicholas Piggin u64 purr; 58910d91611SNicholas Piggin u64 spurr; 59010d91611SNicholas Piggin u64 dscr; 59110d91611SNicholas Piggin u64 wort; 59210d91611SNicholas Piggin 59310d91611SNicholas Piggin u64 mmcra; 59410d91611SNicholas Piggin u32 mmcr0; 59510d91611SNicholas Piggin u32 mmcr1; 59610d91611SNicholas Piggin u64 mmcr2; 597e9cef018SMichael Ellerman 598e9cef018SMichael Ellerman /* per thread SPRs that get lost in shallow states */ 599e9cef018SMichael Ellerman u64 amr; 600e9cef018SMichael Ellerman u64 iamr; 601e9cef018SMichael Ellerman u64 amor; 602e9cef018SMichael Ellerman u64 uamor; 60310d91611SNicholas Piggin }; 60410d91611SNicholas Piggin 60510d91611SNicholas Piggin static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on) 60610d91611SNicholas Piggin { 60710d91611SNicholas Piggin int cpu = raw_smp_processor_id(); 60810d91611SNicholas Piggin int first = cpu_first_thread_sibling(cpu); 60910d91611SNicholas Piggin unsigned long *state = &paca_ptrs[first]->idle_state; 61010d91611SNicholas Piggin unsigned long core_thread_mask = (1UL << threads_per_core) - 1; 61110d91611SNicholas Piggin unsigned long srr1; 61210d91611SNicholas Piggin unsigned long pls; 61310d91611SNicholas Piggin unsigned long mmcr0 = 0; 61410d91611SNicholas Piggin struct p9_sprs sprs = {}; /* avoid false used-uninitialised */ 61510d91611SNicholas Piggin bool sprs_saved = false; 61610d91611SNicholas Piggin 61710d91611SNicholas Piggin if (!(psscr & (PSSCR_EC|PSSCR_ESL))) { 61810d91611SNicholas Piggin /* EC=ESL=0 case */ 61910d91611SNicholas Piggin 62010d91611SNicholas Piggin BUG_ON(!mmu_on); 62110d91611SNicholas Piggin 62210d91611SNicholas Piggin /* 62310d91611SNicholas Piggin * Wake synchronously. SRESET via xscom may still cause 62410d91611SNicholas Piggin * a 0x100 powersave wakeup with SRR1 reason! 62510d91611SNicholas Piggin */ 62610d91611SNicholas Piggin srr1 = isa300_idle_stop_noloss(psscr); /* go idle */ 62710d91611SNicholas Piggin if (likely(!srr1)) 62810d91611SNicholas Piggin return 0; 62910d91611SNicholas Piggin 63010d91611SNicholas Piggin /* 63110d91611SNicholas Piggin * Registers not saved, can't recover! 63210d91611SNicholas Piggin * This would be a hardware bug 63310d91611SNicholas Piggin */ 63410d91611SNicholas Piggin BUG_ON((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS); 63510d91611SNicholas Piggin 63610d91611SNicholas Piggin goto out; 63710d91611SNicholas Piggin } 63810d91611SNicholas Piggin 63910d91611SNicholas Piggin /* EC=ESL=1 case */ 64010d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 64110d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_P9_TM_XER_SO_BUG)) { 64210d91611SNicholas Piggin local_paca->requested_psscr = psscr; 64310d91611SNicholas Piggin /* order setting requested_psscr vs testing dont_stop */ 64410d91611SNicholas Piggin smp_mb(); 64510d91611SNicholas Piggin if (atomic_read(&local_paca->dont_stop)) { 64610d91611SNicholas Piggin local_paca->requested_psscr = 0; 64710d91611SNicholas Piggin return 0; 64810d91611SNicholas Piggin } 64910d91611SNicholas Piggin } 65010d91611SNicholas Piggin #endif 65110d91611SNicholas Piggin 65210d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { 65310d91611SNicholas Piggin /* 65410d91611SNicholas Piggin * POWER9 DD2 can incorrectly set PMAO when waking up 65510d91611SNicholas Piggin * after a state-loss idle. Saving and restoring MMCR0 65610d91611SNicholas Piggin * over idle is a workaround. 65710d91611SNicholas Piggin */ 65810d91611SNicholas Piggin mmcr0 = mfspr(SPRN_MMCR0); 65910d91611SNicholas Piggin } 66010d91611SNicholas Piggin if ((psscr & PSSCR_RL_MASK) >= pnv_first_spr_loss_level) { 66110d91611SNicholas Piggin sprs.lpcr = mfspr(SPRN_LPCR); 66210d91611SNicholas Piggin sprs.hfscr = mfspr(SPRN_HFSCR); 66310d91611SNicholas Piggin sprs.fscr = mfspr(SPRN_FSCR); 66410d91611SNicholas Piggin sprs.pid = mfspr(SPRN_PID); 66510d91611SNicholas Piggin sprs.purr = mfspr(SPRN_PURR); 66610d91611SNicholas Piggin sprs.spurr = mfspr(SPRN_SPURR); 66710d91611SNicholas Piggin sprs.dscr = mfspr(SPRN_DSCR); 66810d91611SNicholas Piggin sprs.wort = mfspr(SPRN_WORT); 66910d91611SNicholas Piggin 67010d91611SNicholas Piggin sprs.mmcra = mfspr(SPRN_MMCRA); 67110d91611SNicholas Piggin sprs.mmcr0 = mfspr(SPRN_MMCR0); 67210d91611SNicholas Piggin sprs.mmcr1 = mfspr(SPRN_MMCR1); 67310d91611SNicholas Piggin sprs.mmcr2 = mfspr(SPRN_MMCR2); 67410d91611SNicholas Piggin 67510d91611SNicholas Piggin sprs.ptcr = mfspr(SPRN_PTCR); 67610d91611SNicholas Piggin sprs.rpr = mfspr(SPRN_RPR); 67710d91611SNicholas Piggin sprs.tscr = mfspr(SPRN_TSCR); 67810d91611SNicholas Piggin sprs.ldbar = mfspr(SPRN_LDBAR); 67910d91611SNicholas Piggin 68010d91611SNicholas Piggin sprs_saved = true; 68110d91611SNicholas Piggin 68210d91611SNicholas Piggin atomic_start_thread_idle(); 68310d91611SNicholas Piggin } 68410d91611SNicholas Piggin 685e9cef018SMichael Ellerman sprs.amr = mfspr(SPRN_AMR); 686e9cef018SMichael Ellerman sprs.iamr = mfspr(SPRN_IAMR); 687e9cef018SMichael Ellerman sprs.amor = mfspr(SPRN_AMOR); 688e9cef018SMichael Ellerman sprs.uamor = mfspr(SPRN_UAMOR); 689e9cef018SMichael Ellerman 69010d91611SNicholas Piggin srr1 = isa300_idle_stop_mayloss(psscr); /* go idle */ 69110d91611SNicholas Piggin 69210d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 69310d91611SNicholas Piggin local_paca->requested_psscr = 0; 69410d91611SNicholas Piggin #endif 69510d91611SNicholas Piggin 69610d91611SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 69710d91611SNicholas Piggin 69810d91611SNicholas Piggin WARN_ON_ONCE(!srr1); 69910d91611SNicholas Piggin WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); 70010d91611SNicholas Piggin 70110d91611SNicholas Piggin if ((srr1 & SRR1_WAKESTATE) != SRR1_WS_NOLOSS) { 70210d91611SNicholas Piggin unsigned long mmcra; 70310d91611SNicholas Piggin 70410d91611SNicholas Piggin /* 705e9cef018SMichael Ellerman * We don't need an isync after the mtsprs here because the 706e9cef018SMichael Ellerman * upcoming mtmsrd is execution synchronizing. 707e9cef018SMichael Ellerman */ 708e9cef018SMichael Ellerman mtspr(SPRN_AMR, sprs.amr); 709e9cef018SMichael Ellerman mtspr(SPRN_IAMR, sprs.iamr); 710e9cef018SMichael Ellerman mtspr(SPRN_AMOR, sprs.amor); 711e9cef018SMichael Ellerman mtspr(SPRN_UAMOR, sprs.uamor); 712e9cef018SMichael Ellerman 713e9cef018SMichael Ellerman /* 71410d91611SNicholas Piggin * Workaround for POWER9 DD2.0, if we lost resources, the ERAT 71510d91611SNicholas Piggin * might have been corrupted and needs flushing. We also need 71610d91611SNicholas Piggin * to reload MMCR0 (see mmcr0 comment above). 71710d91611SNicholas Piggin */ 71810d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { 71910d91611SNicholas Piggin asm volatile(PPC_INVALIDATE_ERAT); 72010d91611SNicholas Piggin mtspr(SPRN_MMCR0, mmcr0); 72110d91611SNicholas Piggin } 72210d91611SNicholas Piggin 72310d91611SNicholas Piggin /* 72410d91611SNicholas Piggin * DD2.2 and earlier need to set then clear bit 60 in MMCRA 72510d91611SNicholas Piggin * to ensure the PMU starts running. 72610d91611SNicholas Piggin */ 72710d91611SNicholas Piggin mmcra = mfspr(SPRN_MMCRA); 72810d91611SNicholas Piggin mmcra |= PPC_BIT(60); 72910d91611SNicholas Piggin mtspr(SPRN_MMCRA, mmcra); 73010d91611SNicholas Piggin mmcra &= ~PPC_BIT(60); 73110d91611SNicholas Piggin mtspr(SPRN_MMCRA, mmcra); 73210d91611SNicholas Piggin } 73310d91611SNicholas Piggin 73410d91611SNicholas Piggin if (unlikely((srr1 & SRR1_WAKEMASK_P8) == SRR1_WAKEHMI)) 73510d91611SNicholas Piggin hmi_exception_realmode(NULL); 73610d91611SNicholas Piggin 73710d91611SNicholas Piggin /* 73810d91611SNicholas Piggin * On POWER9, SRR1 bits do not match exactly as expected. 73910d91611SNicholas Piggin * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so 74010d91611SNicholas Piggin * just always test PSSCR for SPR/TB state loss. 74110d91611SNicholas Piggin */ 74210d91611SNicholas Piggin pls = (psscr & PSSCR_PLS) >> PSSCR_PLS_SHIFT; 74310d91611SNicholas Piggin if (likely(pls < pnv_first_spr_loss_level)) { 74410d91611SNicholas Piggin if (sprs_saved) 74510d91611SNicholas Piggin atomic_stop_thread_idle(); 74610d91611SNicholas Piggin goto out; 74710d91611SNicholas Piggin } 74810d91611SNicholas Piggin 74910d91611SNicholas Piggin /* HV state loss */ 75010d91611SNicholas Piggin BUG_ON(!sprs_saved); 75110d91611SNicholas Piggin 75210d91611SNicholas Piggin atomic_lock_thread_idle(); 75310d91611SNicholas Piggin 75410d91611SNicholas Piggin if ((*state & core_thread_mask) != 0) 75510d91611SNicholas Piggin goto core_woken; 75610d91611SNicholas Piggin 75710d91611SNicholas Piggin /* Per-core SPRs */ 75810d91611SNicholas Piggin mtspr(SPRN_PTCR, sprs.ptcr); 75910d91611SNicholas Piggin mtspr(SPRN_RPR, sprs.rpr); 76010d91611SNicholas Piggin mtspr(SPRN_TSCR, sprs.tscr); 76110d91611SNicholas Piggin mtspr(SPRN_LDBAR, sprs.ldbar); 76210d91611SNicholas Piggin 76310d91611SNicholas Piggin if (pls >= pnv_first_tb_loss_level) { 76410d91611SNicholas Piggin /* TB loss */ 76510d91611SNicholas Piggin if (opal_resync_timebase() != OPAL_SUCCESS) 76610d91611SNicholas Piggin BUG(); 76710d91611SNicholas Piggin } 76810d91611SNicholas Piggin 76910d91611SNicholas Piggin /* 77010d91611SNicholas Piggin * isync after restoring shared SPRs and before unlocking. Unlock 77110d91611SNicholas Piggin * only contains hwsync which does not necessarily do the right 77210d91611SNicholas Piggin * thing for SPRs. 77310d91611SNicholas Piggin */ 77410d91611SNicholas Piggin isync(); 77510d91611SNicholas Piggin 77610d91611SNicholas Piggin core_woken: 77710d91611SNicholas Piggin atomic_unlock_and_stop_thread_idle(); 77810d91611SNicholas Piggin 77910d91611SNicholas Piggin /* Per-thread SPRs */ 78010d91611SNicholas Piggin mtspr(SPRN_LPCR, sprs.lpcr); 78110d91611SNicholas Piggin mtspr(SPRN_HFSCR, sprs.hfscr); 78210d91611SNicholas Piggin mtspr(SPRN_FSCR, sprs.fscr); 78310d91611SNicholas Piggin mtspr(SPRN_PID, sprs.pid); 78410d91611SNicholas Piggin mtspr(SPRN_PURR, sprs.purr); 78510d91611SNicholas Piggin mtspr(SPRN_SPURR, sprs.spurr); 78610d91611SNicholas Piggin mtspr(SPRN_DSCR, sprs.dscr); 78710d91611SNicholas Piggin mtspr(SPRN_WORT, sprs.wort); 78810d91611SNicholas Piggin 78910d91611SNicholas Piggin mtspr(SPRN_MMCRA, sprs.mmcra); 79010d91611SNicholas Piggin mtspr(SPRN_MMCR0, sprs.mmcr0); 79110d91611SNicholas Piggin mtspr(SPRN_MMCR1, sprs.mmcr1); 79210d91611SNicholas Piggin mtspr(SPRN_MMCR2, sprs.mmcr2); 79310d91611SNicholas Piggin 79410d91611SNicholas Piggin mtspr(SPRN_SPRG3, local_paca->sprg_vdso); 79510d91611SNicholas Piggin 79610d91611SNicholas Piggin if (!radix_enabled()) 79710d91611SNicholas Piggin __slb_restore_bolted_realmode(); 79810d91611SNicholas Piggin 79910d91611SNicholas Piggin out: 80010d91611SNicholas Piggin if (mmu_on) 80110d91611SNicholas Piggin mtmsr(MSR_KERNEL); 80210d91611SNicholas Piggin 80310d91611SNicholas Piggin return srr1; 80410d91611SNicholas Piggin } 80510d91611SNicholas Piggin 80610d91611SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 80710d91611SNicholas Piggin static unsigned long power9_offline_stop(unsigned long psscr) 80810d91611SNicholas Piggin { 80910d91611SNicholas Piggin unsigned long srr1; 81010d91611SNicholas Piggin 81110d91611SNicholas Piggin #ifndef CONFIG_KVM_BOOK3S_HV_POSSIBLE 81210d91611SNicholas Piggin __ppc64_runlatch_off(); 81310d91611SNicholas Piggin srr1 = power9_idle_stop(psscr, true); 81410d91611SNicholas Piggin __ppc64_runlatch_on(); 81510d91611SNicholas Piggin #else 81610d91611SNicholas Piggin /* 81710d91611SNicholas Piggin * Tell KVM we're entering idle. 81810d91611SNicholas Piggin * This does not have to be done in real mode because the P9 MMU 81910d91611SNicholas Piggin * is independent per-thread. Some steppings share radix/hash mode 82010d91611SNicholas Piggin * between threads, but in that case KVM has a barrier sync in real 82110d91611SNicholas Piggin * mode before and after switching between radix and hash. 82210d91611SNicholas Piggin * 82310d91611SNicholas Piggin * kvm_start_guest must still be called in real mode though, hence 82410d91611SNicholas Piggin * the false argument. 82510d91611SNicholas Piggin */ 82610d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_IDLE; 82710d91611SNicholas Piggin 82810d91611SNicholas Piggin __ppc64_runlatch_off(); 82910d91611SNicholas Piggin srr1 = power9_idle_stop(psscr, false); 83010d91611SNicholas Piggin __ppc64_runlatch_on(); 83110d91611SNicholas Piggin 83210d91611SNicholas Piggin local_paca->kvm_hstate.hwthread_state = KVM_HWTHREAD_IN_KERNEL; 83310d91611SNicholas Piggin /* Order setting hwthread_state vs. testing hwthread_req */ 83410d91611SNicholas Piggin smp_mb(); 83510d91611SNicholas Piggin if (local_paca->kvm_hstate.hwthread_req) 83610d91611SNicholas Piggin srr1 = idle_kvm_start_guest(srr1); 83710d91611SNicholas Piggin mtmsr(MSR_KERNEL); 83810d91611SNicholas Piggin #endif 83910d91611SNicholas Piggin 84010d91611SNicholas Piggin return srr1; 84110d91611SNicholas Piggin } 84210d91611SNicholas Piggin #endif 84310d91611SNicholas Piggin 84410d91611SNicholas Piggin void power9_idle_type(unsigned long stop_psscr_val, 8452201f994SNicholas Piggin unsigned long stop_psscr_mask) 8462201f994SNicholas Piggin { 8472201f994SNicholas Piggin unsigned long psscr; 8482201f994SNicholas Piggin unsigned long srr1; 8492201f994SNicholas Piggin 8502201f994SNicholas Piggin if (!prep_irq_for_idle_irqsoff()) 85110d91611SNicholas Piggin return; 8522201f994SNicholas Piggin 8532201f994SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 8542201f994SNicholas Piggin psscr = (psscr & ~stop_psscr_mask) | stop_psscr_val; 8552201f994SNicholas Piggin 85640d24343SNicholas Piggin __ppc64_runlatch_off(); 85710d91611SNicholas Piggin srr1 = power9_idle_stop(psscr, true); 85840d24343SNicholas Piggin __ppc64_runlatch_on(); 8592201f994SNicholas Piggin 8602201f994SNicholas Piggin fini_irq_for_idle_irqsoff(); 8612201f994SNicholas Piggin 862771d4304SNicholas Piggin irq_set_pending_from_srr1(srr1); 8632201f994SNicholas Piggin } 8642201f994SNicholas Piggin 86509206b60SGautham R. Shenoy /* 866bcef83a0SShreyas B. Prabhu * Used for ppc_md.power_save which needs a function with no parameters 867bcef83a0SShreyas B. Prabhu */ 8682201f994SNicholas Piggin void power9_idle(void) 869d405a98cSShreyas B. Prabhu { 8702201f994SNicholas Piggin power9_idle_type(pnv_default_stop_val, pnv_default_stop_mask); 871bcef83a0SShreyas B. Prabhu } 87209206b60SGautham R. Shenoy 8737672691aSPaul Mackerras #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 8747672691aSPaul Mackerras /* 8757672691aSPaul Mackerras * This is used in working around bugs in thread reconfiguration 8767672691aSPaul Mackerras * on POWER9 (at least up to Nimbus DD2.2) relating to transactional 8777672691aSPaul Mackerras * memory and the way that XER[SO] is checkpointed. 8787672691aSPaul Mackerras * This function forces the core into SMT4 in order by asking 8797672691aSPaul Mackerras * all other threads not to stop, and sending a message to any 8807672691aSPaul Mackerras * that are in a stop state. 8817672691aSPaul Mackerras * Must be called with preemption disabled. 8827672691aSPaul Mackerras */ 8837672691aSPaul Mackerras void pnv_power9_force_smt4_catch(void) 8847672691aSPaul Mackerras { 8857672691aSPaul Mackerras int cpu, cpu0, thr; 8867672691aSPaul Mackerras int awake_threads = 1; /* this thread is awake */ 8877672691aSPaul Mackerras int poke_threads = 0; 8887672691aSPaul Mackerras int need_awake = threads_per_core; 8897672691aSPaul Mackerras 8907672691aSPaul Mackerras cpu = smp_processor_id(); 8917672691aSPaul Mackerras cpu0 = cpu & ~(threads_per_core - 1); 8927672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 8937672691aSPaul Mackerras if (cpu != cpu0 + thr) 894f437c517SMichael Ellerman atomic_inc(&paca_ptrs[cpu0+thr]->dont_stop); 8957672691aSPaul Mackerras } 8967672691aSPaul Mackerras /* order setting dont_stop vs testing requested_psscr */ 89710d91611SNicholas Piggin smp_mb(); 8987672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 899f437c517SMichael Ellerman if (!paca_ptrs[cpu0+thr]->requested_psscr) 9007672691aSPaul Mackerras ++awake_threads; 9017672691aSPaul Mackerras else 9027672691aSPaul Mackerras poke_threads |= (1 << thr); 9037672691aSPaul Mackerras } 9047672691aSPaul Mackerras 9057672691aSPaul Mackerras /* If at least 3 threads are awake, the core is in SMT4 already */ 9067672691aSPaul Mackerras if (awake_threads < need_awake) { 9077672691aSPaul Mackerras /* We have to wake some threads; we'll use msgsnd */ 9087672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 9097672691aSPaul Mackerras if (poke_threads & (1 << thr)) { 9107672691aSPaul Mackerras ppc_msgsnd_sync(); 9117672691aSPaul Mackerras ppc_msgsnd(PPC_DBELL_MSGTYPE, 0, 912f437c517SMichael Ellerman paca_ptrs[cpu0+thr]->hw_cpu_id); 9137672691aSPaul Mackerras } 9147672691aSPaul Mackerras } 9157672691aSPaul Mackerras /* now spin until at least 3 threads are awake */ 9167672691aSPaul Mackerras do { 9177672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 9187672691aSPaul Mackerras if ((poke_threads & (1 << thr)) && 919f437c517SMichael Ellerman !paca_ptrs[cpu0+thr]->requested_psscr) { 9207672691aSPaul Mackerras ++awake_threads; 9217672691aSPaul Mackerras poke_threads &= ~(1 << thr); 9227672691aSPaul Mackerras } 9237672691aSPaul Mackerras } 9247672691aSPaul Mackerras } while (awake_threads < need_awake); 9257672691aSPaul Mackerras } 9267672691aSPaul Mackerras } 9277672691aSPaul Mackerras EXPORT_SYMBOL_GPL(pnv_power9_force_smt4_catch); 9287672691aSPaul Mackerras 9297672691aSPaul Mackerras void pnv_power9_force_smt4_release(void) 9307672691aSPaul Mackerras { 9317672691aSPaul Mackerras int cpu, cpu0, thr; 9327672691aSPaul Mackerras 9337672691aSPaul Mackerras cpu = smp_processor_id(); 9347672691aSPaul Mackerras cpu0 = cpu & ~(threads_per_core - 1); 9357672691aSPaul Mackerras 9367672691aSPaul Mackerras /* clear all the dont_stop flags */ 9377672691aSPaul Mackerras for (thr = 0; thr < threads_per_core; ++thr) { 9387672691aSPaul Mackerras if (cpu != cpu0 + thr) 939f437c517SMichael Ellerman atomic_dec(&paca_ptrs[cpu0+thr]->dont_stop); 9407672691aSPaul Mackerras } 9417672691aSPaul Mackerras } 9427672691aSPaul Mackerras EXPORT_SYMBOL_GPL(pnv_power9_force_smt4_release); 9437672691aSPaul Mackerras #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 9447672691aSPaul Mackerras 94567d20418SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 94619f8a5b5SPaul Mackerras 94719f8a5b5SPaul Mackerras void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val) 94824be85a2SGautham R. Shenoy { 94924be85a2SGautham R. Shenoy u64 pir = get_hard_smp_processor_id(cpu); 95024be85a2SGautham R. Shenoy 95124be85a2SGautham R. Shenoy mtspr(SPRN_LPCR, lpcr_val); 9525d298baaSGautham R. Shenoy 9535d298baaSGautham R. Shenoy /* 9545d298baaSGautham R. Shenoy * Program the LPCR via stop-api only if the deepest stop state 9555d298baaSGautham R. Shenoy * can lose hypervisor context. 9565d298baaSGautham R. Shenoy */ 9575d298baaSGautham R. Shenoy if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) 95824be85a2SGautham R. Shenoy opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 95924be85a2SGautham R. Shenoy } 96024be85a2SGautham R. Shenoy 961c0691f9dSShreyas B. Prabhu /* 962a7cd88daSGautham R. Shenoy * pnv_cpu_offline: A function that puts the CPU into the deepest 963a7cd88daSGautham R. Shenoy * available platform idle state on a CPU-Offline. 9642525db04SNicholas Piggin * interrupts hard disabled and no lazy irq pending. 965a7cd88daSGautham R. Shenoy */ 966a7cd88daSGautham R. Shenoy unsigned long pnv_cpu_offline(unsigned int cpu) 967a7cd88daSGautham R. Shenoy { 968a7cd88daSGautham R. Shenoy unsigned long srr1; 969a7cd88daSGautham R. Shenoy 97040d24343SNicholas Piggin __ppc64_runlatch_off(); 9712525db04SNicholas Piggin 972f3b3f284SGautham R. Shenoy if (cpu_has_feature(CPU_FTR_ARCH_300) && deepest_stop_found) { 9732525db04SNicholas Piggin unsigned long psscr; 9742525db04SNicholas Piggin 9752525db04SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 9762525db04SNicholas Piggin psscr = (psscr & ~pnv_deepest_stop_psscr_mask) | 9772525db04SNicholas Piggin pnv_deepest_stop_psscr_val; 9783d4fbffdSNicholas Piggin srr1 = power9_offline_stop(psscr); 97910d91611SNicholas Piggin } else if (cpu_has_feature(CPU_FTR_ARCH_206) && power7_offline_type) { 98010d91611SNicholas Piggin srr1 = power7_offline(); 98190061231SGautham R. Shenoy } else { 98290061231SGautham R. Shenoy /* This is the fallback method. We emulate snooze */ 98390061231SGautham R. Shenoy while (!generic_check_cpu_restart(cpu)) { 98490061231SGautham R. Shenoy HMT_low(); 98590061231SGautham R. Shenoy HMT_very_low(); 98690061231SGautham R. Shenoy } 98790061231SGautham R. Shenoy srr1 = 0; 98890061231SGautham R. Shenoy HMT_medium(); 989a7cd88daSGautham R. Shenoy } 990a7cd88daSGautham R. Shenoy 99140d24343SNicholas Piggin __ppc64_runlatch_on(); 9922525db04SNicholas Piggin 993a7cd88daSGautham R. Shenoy return srr1; 994a7cd88daSGautham R. Shenoy } 99567d20418SNicholas Piggin #endif 996a7cd88daSGautham R. Shenoy 997a7cd88daSGautham R. Shenoy /* 998bcef83a0SShreyas B. Prabhu * Power ISA 3.0 idle initialization. 999bcef83a0SShreyas B. Prabhu * 1000bcef83a0SShreyas B. Prabhu * POWER ISA 3.0 defines a new SPR Processor stop Status and Control 1001bcef83a0SShreyas B. Prabhu * Register (PSSCR) to control idle behavior. 1002bcef83a0SShreyas B. Prabhu * 1003bcef83a0SShreyas B. Prabhu * PSSCR layout: 1004bcef83a0SShreyas B. Prabhu * ---------------------------------------------------------- 1005bcef83a0SShreyas B. Prabhu * | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | 1006bcef83a0SShreyas B. Prabhu * ---------------------------------------------------------- 1007bcef83a0SShreyas B. Prabhu * 0 4 41 42 43 44 48 54 56 60 1008bcef83a0SShreyas B. Prabhu * 1009bcef83a0SShreyas B. Prabhu * PSSCR key fields: 1010bcef83a0SShreyas B. Prabhu * Bits 0:3 - Power-Saving Level Status (PLS). This field indicates the 1011bcef83a0SShreyas B. Prabhu * lowest power-saving state the thread entered since stop instruction was 1012bcef83a0SShreyas B. Prabhu * last executed. 1013bcef83a0SShreyas B. Prabhu * 1014bcef83a0SShreyas B. Prabhu * Bit 41 - Status Disable(SD) 1015bcef83a0SShreyas B. Prabhu * 0 - Shows PLS entries 1016bcef83a0SShreyas B. Prabhu * 1 - PLS entries are all 0 1017bcef83a0SShreyas B. Prabhu * 1018bcef83a0SShreyas B. Prabhu * Bit 42 - Enable State Loss 1019bcef83a0SShreyas B. Prabhu * 0 - No state is lost irrespective of other fields 1020bcef83a0SShreyas B. Prabhu * 1 - Allows state loss 1021bcef83a0SShreyas B. Prabhu * 1022bcef83a0SShreyas B. Prabhu * Bit 43 - Exit Criterion 1023bcef83a0SShreyas B. Prabhu * 0 - Exit from power-save mode on any interrupt 1024bcef83a0SShreyas B. Prabhu * 1 - Exit from power-save mode controlled by LPCR's PECE bits 1025bcef83a0SShreyas B. Prabhu * 1026bcef83a0SShreyas B. Prabhu * Bits 44:47 - Power-Saving Level Limit 1027bcef83a0SShreyas B. Prabhu * This limits the power-saving level that can be entered into. 1028bcef83a0SShreyas B. Prabhu * 1029bcef83a0SShreyas B. Prabhu * Bits 60:63 - Requested Level 1030bcef83a0SShreyas B. Prabhu * Used to specify which power-saving level must be entered on executing 1031bcef83a0SShreyas B. Prabhu * stop instruction 103209206b60SGautham R. Shenoy */ 103309206b60SGautham R. Shenoy 103409206b60SGautham R. Shenoy int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags) 103509206b60SGautham R. Shenoy { 103609206b60SGautham R. Shenoy int err = 0; 103709206b60SGautham R. Shenoy 103809206b60SGautham R. Shenoy /* 103909206b60SGautham R. Shenoy * psscr_mask == 0xf indicates an older firmware. 104009206b60SGautham R. Shenoy * Set remaining fields of psscr to the default values. 104109206b60SGautham R. Shenoy * See NOTE above definition of PSSCR_HV_DEFAULT_VAL 104209206b60SGautham R. Shenoy */ 104309206b60SGautham R. Shenoy if (*psscr_mask == 0xf) { 104409206b60SGautham R. Shenoy *psscr_val = *psscr_val | PSSCR_HV_DEFAULT_VAL; 104509206b60SGautham R. Shenoy *psscr_mask = PSSCR_HV_DEFAULT_MASK; 104609206b60SGautham R. Shenoy return err; 104709206b60SGautham R. Shenoy } 104809206b60SGautham R. Shenoy 104909206b60SGautham R. Shenoy /* 105009206b60SGautham R. Shenoy * New firmware is expected to set the psscr_val bits correctly. 105109206b60SGautham R. Shenoy * Validate that the following invariants are correctly maintained by 105209206b60SGautham R. Shenoy * the new firmware. 105309206b60SGautham R. Shenoy * - ESL bit value matches the EC bit value. 105409206b60SGautham R. Shenoy * - ESL bit is set for all the deep stop states. 105509206b60SGautham R. Shenoy */ 105609206b60SGautham R. Shenoy if (GET_PSSCR_ESL(*psscr_val) != GET_PSSCR_EC(*psscr_val)) { 105709206b60SGautham R. Shenoy err = ERR_EC_ESL_MISMATCH; 105809206b60SGautham R. Shenoy } else if ((flags & OPAL_PM_LOSE_FULL_CONTEXT) && 105909206b60SGautham R. Shenoy GET_PSSCR_ESL(*psscr_val) == 0) { 106009206b60SGautham R. Shenoy err = ERR_DEEP_STATE_ESL_MISMATCH; 106109206b60SGautham R. Shenoy } 106209206b60SGautham R. Shenoy 106309206b60SGautham R. Shenoy return err; 106409206b60SGautham R. Shenoy } 106509206b60SGautham R. Shenoy 106609206b60SGautham R. Shenoy /* 106709206b60SGautham R. Shenoy * pnv_arch300_idle_init: Initializes the default idle state, first 106809206b60SGautham R. Shenoy * deep idle state and deepest idle state on 106909206b60SGautham R. Shenoy * ISA 3.0 CPUs. 1070bcef83a0SShreyas B. Prabhu * 1071bcef83a0SShreyas B. Prabhu * @np: /ibm,opal/power-mgt device node 1072bcef83a0SShreyas B. Prabhu * @flags: cpu-idle-state-flags array 1073bcef83a0SShreyas B. Prabhu * @dt_idle_states: Number of idle state entries 1074bcef83a0SShreyas B. Prabhu * Returns 0 on success 1075bcef83a0SShreyas B. Prabhu */ 107610d91611SNicholas Piggin static void __init pnv_power9_idle_init(void) 1077bcef83a0SShreyas B. Prabhu { 107809206b60SGautham R. Shenoy u64 max_residency_ns = 0; 10799c7b185aSAkshay Adiga int i; 1080bcef83a0SShreyas B. Prabhu 1081bcef83a0SShreyas B. Prabhu /* 108209206b60SGautham R. Shenoy * pnv_deepest_stop_{val,mask} should be set to values corresponding to 108309206b60SGautham R. Shenoy * the deepest stop state. 108409206b60SGautham R. Shenoy * 108509206b60SGautham R. Shenoy * pnv_default_stop_{val,mask} should be set to values corresponding to 108610d91611SNicholas Piggin * the deepest loss-less (OPAL_PM_STOP_INST_FAST) stop state. 1087bcef83a0SShreyas B. Prabhu */ 108810d91611SNicholas Piggin pnv_first_tb_loss_level = MAX_STOP_STATE + 1; 108910d91611SNicholas Piggin pnv_first_spr_loss_level = MAX_STOP_STATE + 1; 10909c7b185aSAkshay Adiga for (i = 0; i < nr_pnv_idle_states; i++) { 109109206b60SGautham R. Shenoy int err; 10929c7b185aSAkshay Adiga struct pnv_idle_states_t *state = &pnv_idle_states[i]; 10939c7b185aSAkshay Adiga u64 psscr_rl = state->psscr_val & PSSCR_RL_MASK; 1094bcef83a0SShreyas B. Prabhu 109510d91611SNicholas Piggin if ((state->flags & OPAL_PM_TIMEBASE_STOP) && 109610d91611SNicholas Piggin (pnv_first_tb_loss_level > psscr_rl)) 109710d91611SNicholas Piggin pnv_first_tb_loss_level = psscr_rl; 109810d91611SNicholas Piggin 10999c7b185aSAkshay Adiga if ((state->flags & OPAL_PM_LOSE_FULL_CONTEXT) && 110010d91611SNicholas Piggin (pnv_first_spr_loss_level > psscr_rl)) 110110d91611SNicholas Piggin pnv_first_spr_loss_level = psscr_rl; 110210d91611SNicholas Piggin 110310d91611SNicholas Piggin /* 110410d91611SNicholas Piggin * The idle code does not deal with TB loss occurring 110510d91611SNicholas Piggin * in a shallower state than SPR loss, so force it to 110610d91611SNicholas Piggin * behave like SPRs are lost if TB is lost. POWER9 would 110710d91611SNicholas Piggin * never encouter this, but a POWER8 core would if it 110810d91611SNicholas Piggin * implemented the stop instruction. So this is for forward 110910d91611SNicholas Piggin * compatibility. 111010d91611SNicholas Piggin */ 111110d91611SNicholas Piggin if ((state->flags & OPAL_PM_TIMEBASE_STOP) && 111210d91611SNicholas Piggin (pnv_first_spr_loss_level > psscr_rl)) 111310d91611SNicholas Piggin pnv_first_spr_loss_level = psscr_rl; 1114c0691f9dSShreyas B. Prabhu 11159c7b185aSAkshay Adiga err = validate_psscr_val_mask(&state->psscr_val, 11169c7b185aSAkshay Adiga &state->psscr_mask, 11179c7b185aSAkshay Adiga state->flags); 111809206b60SGautham R. Shenoy if (err) { 11199c7b185aSAkshay Adiga report_invalid_psscr_val(state->psscr_val, err); 112009206b60SGautham R. Shenoy continue; 112109206b60SGautham R. Shenoy } 112209206b60SGautham R. Shenoy 11233127692dSNicholas Piggin state->valid = true; 11243127692dSNicholas Piggin 11259c7b185aSAkshay Adiga if (max_residency_ns < state->residency_ns) { 11269c7b185aSAkshay Adiga max_residency_ns = state->residency_ns; 11279c7b185aSAkshay Adiga pnv_deepest_stop_psscr_val = state->psscr_val; 11289c7b185aSAkshay Adiga pnv_deepest_stop_psscr_mask = state->psscr_mask; 11299c7b185aSAkshay Adiga pnv_deepest_stop_flag = state->flags; 113009206b60SGautham R. Shenoy deepest_stop_found = true; 113109206b60SGautham R. Shenoy } 113209206b60SGautham R. Shenoy 113309206b60SGautham R. Shenoy if (!default_stop_found && 11349c7b185aSAkshay Adiga (state->flags & OPAL_PM_STOP_INST_FAST)) { 11359c7b185aSAkshay Adiga pnv_default_stop_val = state->psscr_val; 11369c7b185aSAkshay Adiga pnv_default_stop_mask = state->psscr_mask; 113709206b60SGautham R. Shenoy default_stop_found = true; 113810d91611SNicholas Piggin WARN_ON(state->flags & OPAL_PM_LOSE_FULL_CONTEXT); 113909206b60SGautham R. Shenoy } 114009206b60SGautham R. Shenoy } 114109206b60SGautham R. Shenoy 1142f3b3f284SGautham R. Shenoy if (unlikely(!default_stop_found)) { 1143f3b3f284SGautham R. Shenoy pr_warn("cpuidle-powernv: No suitable default stop state found. Disabling platform idle.\n"); 1144f3b3f284SGautham R. Shenoy } else { 1145f3b3f284SGautham R. Shenoy ppc_md.power_save = power9_idle; 1146f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Default stop: psscr = 0x%016llx,mask=0x%016llx\n", 114709206b60SGautham R. Shenoy pnv_default_stop_val, pnv_default_stop_mask); 114809206b60SGautham R. Shenoy } 114909206b60SGautham R. Shenoy 1150f3b3f284SGautham R. Shenoy if (unlikely(!deepest_stop_found)) { 1151f3b3f284SGautham R. Shenoy pr_warn("cpuidle-powernv: No suitable stop state for CPU-Hotplug. Offlined CPUs will busy wait"); 1152f3b3f284SGautham R. Shenoy } else { 1153f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Deepest stop: psscr = 0x%016llx,mask=0x%016llx\n", 115409206b60SGautham R. Shenoy pnv_deepest_stop_psscr_val, 115509206b60SGautham R. Shenoy pnv_deepest_stop_psscr_mask); 1156bcef83a0SShreyas B. Prabhu } 1157bcef83a0SShreyas B. Prabhu 115810d91611SNicholas Piggin pr_info("cpuidle-powernv: First stop level that may lose SPRs = 0x%lld\n", 115910d91611SNicholas Piggin pnv_first_spr_loss_level); 11609c7b185aSAkshay Adiga 116110d91611SNicholas Piggin pr_info("cpuidle-powernv: First stop level that may lose timebase = 0x%lld\n", 116210d91611SNicholas Piggin pnv_first_tb_loss_level); 116310d91611SNicholas Piggin } 116410d91611SNicholas Piggin 116510d91611SNicholas Piggin static void __init pnv_disable_deep_states(void) 116610d91611SNicholas Piggin { 116710d91611SNicholas Piggin /* 116810d91611SNicholas Piggin * The stop-api is unable to restore hypervisor 116910d91611SNicholas Piggin * resources on wakeup from platform idle states which 117010d91611SNicholas Piggin * lose full context. So disable such states. 117110d91611SNicholas Piggin */ 117210d91611SNicholas Piggin supported_cpuidle_states &= ~OPAL_PM_LOSE_FULL_CONTEXT; 117310d91611SNicholas Piggin pr_warn("cpuidle-powernv: Disabling idle states that lose full context\n"); 117410d91611SNicholas Piggin pr_warn("cpuidle-powernv: Idle power-savings, CPU-Hotplug affected\n"); 117510d91611SNicholas Piggin 117610d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_300) && 117710d91611SNicholas Piggin (pnv_deepest_stop_flag & OPAL_PM_LOSE_FULL_CONTEXT)) { 117810d91611SNicholas Piggin /* 117910d91611SNicholas Piggin * Use the default stop state for CPU-Hotplug 118010d91611SNicholas Piggin * if available. 118110d91611SNicholas Piggin */ 118210d91611SNicholas Piggin if (default_stop_found) { 118310d91611SNicholas Piggin pnv_deepest_stop_psscr_val = pnv_default_stop_val; 118410d91611SNicholas Piggin pnv_deepest_stop_psscr_mask = pnv_default_stop_mask; 118510d91611SNicholas Piggin pr_warn("cpuidle-powernv: Offlined CPUs will stop with psscr = 0x%016llx\n", 118610d91611SNicholas Piggin pnv_deepest_stop_psscr_val); 118710d91611SNicholas Piggin } else { /* Fallback to snooze loop for CPU-Hotplug */ 118810d91611SNicholas Piggin deepest_stop_found = false; 118910d91611SNicholas Piggin pr_warn("cpuidle-powernv: Offlined CPUs will busy wait\n"); 119010d91611SNicholas Piggin } 119110d91611SNicholas Piggin } 1192bcef83a0SShreyas B. Prabhu } 1193bcef83a0SShreyas B. Prabhu 1194bcef83a0SShreyas B. Prabhu /* 1195bcef83a0SShreyas B. Prabhu * Probe device tree for supported idle states 1196bcef83a0SShreyas B. Prabhu */ 1197bcef83a0SShreyas B. Prabhu static void __init pnv_probe_idle_states(void) 1198bcef83a0SShreyas B. Prabhu { 1199d405a98cSShreyas B. Prabhu int i; 1200d405a98cSShreyas B. Prabhu 12019c7b185aSAkshay Adiga if (nr_pnv_idle_states < 0) { 12029c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: no idle states found in the DT\n"); 12039c7b185aSAkshay Adiga return; 12049c7b185aSAkshay Adiga } 12059c7b185aSAkshay Adiga 120610d91611SNicholas Piggin if (cpu_has_feature(CPU_FTR_ARCH_300)) 120710d91611SNicholas Piggin pnv_power9_idle_init(); 12089c7b185aSAkshay Adiga 12099c7b185aSAkshay Adiga for (i = 0; i < nr_pnv_idle_states; i++) 12109c7b185aSAkshay Adiga supported_cpuidle_states |= pnv_idle_states[i].flags; 12119c7b185aSAkshay Adiga } 12129c7b185aSAkshay Adiga 12139c7b185aSAkshay Adiga /* 12149c7b185aSAkshay Adiga * This function parses device-tree and populates all the information 12159c7b185aSAkshay Adiga * into pnv_idle_states structure. It also sets up nr_pnv_idle_states 12169c7b185aSAkshay Adiga * which is the number of cpuidle states discovered through device-tree. 12179c7b185aSAkshay Adiga */ 12189c7b185aSAkshay Adiga 12199c7b185aSAkshay Adiga static int pnv_parse_cpuidle_dt(void) 12209c7b185aSAkshay Adiga { 12219c7b185aSAkshay Adiga struct device_node *np; 12229c7b185aSAkshay Adiga int nr_idle_states, i; 12239c7b185aSAkshay Adiga int rc = 0; 12249c7b185aSAkshay Adiga u32 *temp_u32; 12259c7b185aSAkshay Adiga u64 *temp_u64; 12269c7b185aSAkshay Adiga const char **temp_string; 12279c7b185aSAkshay Adiga 1228bcef83a0SShreyas B. Prabhu np = of_find_node_by_path("/ibm,opal/power-mgt"); 1229bcef83a0SShreyas B. Prabhu if (!np) { 1230d405a98cSShreyas B. Prabhu pr_warn("opal: PowerMgmt Node not found\n"); 12319c7b185aSAkshay Adiga return -ENODEV; 1232d405a98cSShreyas B. Prabhu } 12339c7b185aSAkshay Adiga nr_idle_states = of_property_count_u32_elems(np, 1234d405a98cSShreyas B. Prabhu "ibm,cpu-idle-state-flags"); 12359c7b185aSAkshay Adiga 12369c7b185aSAkshay Adiga pnv_idle_states = kcalloc(nr_idle_states, sizeof(*pnv_idle_states), 12379c7b185aSAkshay Adiga GFP_KERNEL); 12389c7b185aSAkshay Adiga temp_u32 = kcalloc(nr_idle_states, sizeof(u32), GFP_KERNEL); 12399c7b185aSAkshay Adiga temp_u64 = kcalloc(nr_idle_states, sizeof(u64), GFP_KERNEL); 12409c7b185aSAkshay Adiga temp_string = kcalloc(nr_idle_states, sizeof(char *), GFP_KERNEL); 12419c7b185aSAkshay Adiga 12429c7b185aSAkshay Adiga if (!(pnv_idle_states && temp_u32 && temp_u64 && temp_string)) { 12439c7b185aSAkshay Adiga pr_err("Could not allocate memory for dt parsing\n"); 12449c7b185aSAkshay Adiga rc = -ENOMEM; 1245d405a98cSShreyas B. Prabhu goto out; 1246d405a98cSShreyas B. Prabhu } 1247d405a98cSShreyas B. Prabhu 12489c7b185aSAkshay Adiga /* Read flags */ 12499c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-flags", 12509c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 1251d405a98cSShreyas B. Prabhu pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n"); 12529c7b185aSAkshay Adiga rc = -EINVAL; 1253bcef83a0SShreyas B. Prabhu goto out; 1254bcef83a0SShreyas B. Prabhu } 12559c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12569c7b185aSAkshay Adiga pnv_idle_states[i].flags = temp_u32[i]; 1257bcef83a0SShreyas B. Prabhu 12589c7b185aSAkshay Adiga /* Read latencies */ 12599c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-latencies-ns", 12609c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 12619c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-latencies-ns in DT\n"); 12629c7b185aSAkshay Adiga rc = -EINVAL; 12639c7b185aSAkshay Adiga goto out; 12649c7b185aSAkshay Adiga } 12659c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12669c7b185aSAkshay Adiga pnv_idle_states[i].latency_ns = temp_u32[i]; 12679c7b185aSAkshay Adiga 12689c7b185aSAkshay Adiga /* Read residencies */ 12699c7b185aSAkshay Adiga if (of_property_read_u32_array(np, "ibm,cpu-idle-state-residency-ns", 12709c7b185aSAkshay Adiga temp_u32, nr_idle_states)) { 12719c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-latencies-ns in DT\n"); 12729c7b185aSAkshay Adiga rc = -EINVAL; 12739c7b185aSAkshay Adiga goto out; 12749c7b185aSAkshay Adiga } 12759c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12769c7b185aSAkshay Adiga pnv_idle_states[i].residency_ns = temp_u32[i]; 12779c7b185aSAkshay Adiga 12789c7b185aSAkshay Adiga /* For power9 */ 1279bcef83a0SShreyas B. Prabhu if (cpu_has_feature(CPU_FTR_ARCH_300)) { 12809c7b185aSAkshay Adiga /* Read pm_crtl_val */ 12819c7b185aSAkshay Adiga if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr", 12829c7b185aSAkshay Adiga temp_u64, nr_idle_states)) { 12839c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n"); 12849c7b185aSAkshay Adiga rc = -EINVAL; 1285bcef83a0SShreyas B. Prabhu goto out; 1286d405a98cSShreyas B. Prabhu } 12879c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12889c7b185aSAkshay Adiga pnv_idle_states[i].psscr_val = temp_u64[i]; 1289d405a98cSShreyas B. Prabhu 12909c7b185aSAkshay Adiga /* Read pm_crtl_mask */ 12919c7b185aSAkshay Adiga if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr-mask", 12929c7b185aSAkshay Adiga temp_u64, nr_idle_states)) { 12939c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n"); 12949c7b185aSAkshay Adiga rc = -EINVAL; 12959c7b185aSAkshay Adiga goto out; 1296bcef83a0SShreyas B. Prabhu } 12979c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 12989c7b185aSAkshay Adiga pnv_idle_states[i].psscr_mask = temp_u64[i]; 12999c7b185aSAkshay Adiga } 13009c7b185aSAkshay Adiga 13019c7b185aSAkshay Adiga /* 13029c7b185aSAkshay Adiga * power8 specific properties ibm,cpu-idle-state-pmicr-mask and 13039c7b185aSAkshay Adiga * ibm,cpu-idle-state-pmicr-val were never used and there is no 13049c7b185aSAkshay Adiga * plan to use it in near future. Hence, not parsing these properties 13059c7b185aSAkshay Adiga */ 13069c7b185aSAkshay Adiga 13079c7b185aSAkshay Adiga if (of_property_read_string_array(np, "ibm,cpu-idle-state-names", 13089c7b185aSAkshay Adiga temp_string, nr_idle_states) < 0) { 13099c7b185aSAkshay Adiga pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-names in DT\n"); 13109c7b185aSAkshay Adiga rc = -EINVAL; 13119c7b185aSAkshay Adiga goto out; 13129c7b185aSAkshay Adiga } 13139c7b185aSAkshay Adiga for (i = 0; i < nr_idle_states; i++) 1314ae24ce5eSAneesh Kumar K.V strlcpy(pnv_idle_states[i].name, temp_string[i], 13159c7b185aSAkshay Adiga PNV_IDLE_NAME_LEN); 13169c7b185aSAkshay Adiga nr_pnv_idle_states = nr_idle_states; 13179c7b185aSAkshay Adiga rc = 0; 13189c7b185aSAkshay Adiga out: 13199c7b185aSAkshay Adiga kfree(temp_u32); 13209c7b185aSAkshay Adiga kfree(temp_u64); 13219c7b185aSAkshay Adiga kfree(temp_string); 13229c7b185aSAkshay Adiga return rc; 13239c7b185aSAkshay Adiga } 13249c7b185aSAkshay Adiga 1325bcef83a0SShreyas B. Prabhu static int __init pnv_init_idle_states(void) 1326bcef83a0SShreyas B. Prabhu { 132710d91611SNicholas Piggin int cpu; 13289c7b185aSAkshay Adiga int rc = 0; 132910d91611SNicholas Piggin 133010d91611SNicholas Piggin /* Set up PACA fields */ 133110d91611SNicholas Piggin for_each_present_cpu(cpu) { 133210d91611SNicholas Piggin struct paca_struct *p = paca_ptrs[cpu]; 133310d91611SNicholas Piggin 133410d91611SNicholas Piggin p->idle_state = 0; 133510d91611SNicholas Piggin if (cpu == cpu_first_thread_sibling(cpu)) 133610d91611SNicholas Piggin p->idle_state = (1 << threads_per_core) - 1; 133710d91611SNicholas Piggin 133810d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 133910d91611SNicholas Piggin /* P7/P8 nap */ 134010d91611SNicholas Piggin p->thread_idle_state = PNV_THREAD_RUNNING; 134110d91611SNicholas Piggin } else { 134210d91611SNicholas Piggin /* P9 stop */ 134310d91611SNicholas Piggin #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 134410d91611SNicholas Piggin p->requested_psscr = 0; 134510d91611SNicholas Piggin atomic_set(&p->dont_stop, 0); 134610d91611SNicholas Piggin #endif 134710d91611SNicholas Piggin } 134810d91611SNicholas Piggin } 1349bcef83a0SShreyas B. Prabhu 13509c7b185aSAkshay Adiga /* In case we error out nr_pnv_idle_states will be zero */ 13519c7b185aSAkshay Adiga nr_pnv_idle_states = 0; 135210d91611SNicholas Piggin supported_cpuidle_states = 0; 135310d91611SNicholas Piggin 1354bcef83a0SShreyas B. Prabhu if (cpuidle_disable != IDLE_NO_OVERRIDE) 1355bcef83a0SShreyas B. Prabhu goto out; 13569c7b185aSAkshay Adiga rc = pnv_parse_cpuidle_dt(); 13579c7b185aSAkshay Adiga if (rc) 13589c7b185aSAkshay Adiga return rc; 1359bcef83a0SShreyas B. Prabhu pnv_probe_idle_states(); 1360bcef83a0SShreyas B. Prabhu 136110d91611SNicholas Piggin if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1362d405a98cSShreyas B. Prabhu if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { 136310d91611SNicholas Piggin power7_fastsleep_workaround_entry = false; 136410d91611SNicholas Piggin power7_fastsleep_workaround_exit = false; 13655703d2f4SShreyas B. Prabhu } else { 13665703d2f4SShreyas B. Prabhu /* 13675703d2f4SShreyas B. Prabhu * OPAL_PM_SLEEP_ENABLED_ER1 is set. It indicates that 13685703d2f4SShreyas B. Prabhu * workaround is needed to use fastsleep. Provide sysfs 136910d91611SNicholas Piggin * control to choose how this workaround has to be 137010d91611SNicholas Piggin * applied. 13715703d2f4SShreyas B. Prabhu */ 13725703d2f4SShreyas B. Prabhu device_create_file(cpu_subsys.dev_root, 13735703d2f4SShreyas B. Prabhu &dev_attr_fastsleep_workaround_applyonce); 1374d405a98cSShreyas B. Prabhu } 13755703d2f4SShreyas B. Prabhu 137610d91611SNicholas Piggin update_subcore_sibling_mask(); 13775593e303SShreyas B. Prabhu 137810d91611SNicholas Piggin if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED) { 13795593e303SShreyas B. Prabhu ppc_md.power_save = power7_idle; 138010d91611SNicholas Piggin power7_offline_type = PNV_THREAD_NAP; 138110d91611SNicholas Piggin } 138210d91611SNicholas Piggin 138310d91611SNicholas Piggin if ((supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED) && 138410d91611SNicholas Piggin (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT)) 138510d91611SNicholas Piggin power7_offline_type = PNV_THREAD_WINKLE; 138610d91611SNicholas Piggin else if ((supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED) || 138710d91611SNicholas Piggin (supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) 138810d91611SNicholas Piggin power7_offline_type = PNV_THREAD_SLEEP; 138910d91611SNicholas Piggin } 139010d91611SNicholas Piggin 139110d91611SNicholas Piggin if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) { 139210d91611SNicholas Piggin if (pnv_save_sprs_for_deep_states()) 139310d91611SNicholas Piggin pnv_disable_deep_states(); 139410d91611SNicholas Piggin } 1395bcef83a0SShreyas B. Prabhu 1396d405a98cSShreyas B. Prabhu out: 1397d405a98cSShreyas B. Prabhu return 0; 1398d405a98cSShreyas B. Prabhu } 13994bece972SMichael Ellerman machine_subsys_initcall(powernv, pnv_init_idle_states); 1400